if_gm.c revision 1.54
1 /* $NetBSD: if_gm.c,v 1.54 2019/05/23 10:57:27 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.54 2019/05/23 10:57:27 msaitoh Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <sys/rndsource.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/ofw/openfirm.h> 66 #include <macppc/dev/if_gmreg.h> 67 #include <machine/pio.h> 68 69 #define NTXBUF 4 70 #define NRXBUF 32 71 72 struct gmac_softc { 73 device_t sc_dev; 74 struct ethercom sc_ethercom; 75 vaddr_t sc_reg; 76 struct gmac_dma *sc_txlist; 77 struct gmac_dma *sc_rxlist; 78 int sc_txnext; 79 int sc_rxlast; 80 void *sc_txbuf[NTXBUF]; 81 void *sc_rxbuf[NRXBUF]; 82 struct mii_data sc_mii; 83 struct callout sc_tick_ch; 84 char sc_laddr[6]; 85 86 krndsource_t sc_rnd_source; /* random source */ 87 }; 88 89 #define sc_if sc_ethercom.ec_if 90 91 int gmac_match(device_t, cfdata_t, void *); 92 void gmac_attach(device_t, device_t, void *); 93 94 static inline u_int gmac_read_reg(struct gmac_softc *, int); 95 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 96 97 static inline void gmac_start_txdma(struct gmac_softc *); 98 static inline void gmac_start_rxdma(struct gmac_softc *); 99 static inline void gmac_stop_txdma(struct gmac_softc *); 100 static inline void gmac_stop_rxdma(struct gmac_softc *); 101 102 int gmac_intr(void *); 103 void gmac_tint(struct gmac_softc *); 104 void gmac_rint(struct gmac_softc *); 105 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 106 void gmac_start(struct ifnet *); 107 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 108 109 void gmac_stop(struct gmac_softc *); 110 void gmac_reset(struct gmac_softc *); 111 void gmac_init(struct gmac_softc *); 112 void gmac_init_mac(struct gmac_softc *); 113 void gmac_setladrf(struct gmac_softc *); 114 115 int gmac_ioctl(struct ifnet *, u_long, void *); 116 void gmac_watchdog(struct ifnet *); 117 118 int gmac_mii_readreg(device_t, int, int, uint16_t *); 119 int gmac_mii_writereg(device_t, int, int, uint16_t); 120 void gmac_mii_statchg(struct ifnet *); 121 void gmac_mii_tick(void *); 122 123 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 124 gmac_match, gmac_attach, NULL, NULL); 125 126 int 127 gmac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 132 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 134 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 135 return 1; 136 137 return 0; 138 } 139 140 void 141 gmac_attach(device_t parent, device_t self, void *aux) 142 { 143 struct gmac_softc * const sc = device_private(self); 144 struct pci_attach_args * const pa = aux; 145 struct ifnet * const ifp = &sc->sc_if; 146 struct mii_data * const mii = &sc->sc_mii; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 const char * const xname = device_xname(self); 150 int node, i; 151 char *p; 152 struct gmac_dma *dp; 153 uint32_t reg[10]; 154 u_char laddr[6]; 155 char buf[PCI_INTRSTR_LEN]; 156 157 sc->sc_dev = self; 158 159 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 160 if (node == 0) { 161 printf(": cannot find gmac node\n"); 162 return; 163 } 164 165 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 166 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 167 168 memcpy(sc->sc_laddr, laddr, sizeof laddr); 169 sc->sc_reg = reg[2]; 170 171 if (pci_intr_map(pa, &ih)) { 172 printf(": unable to map interrupt\n"); 173 return; 174 } 175 intrstr = pci_intr_string(pa->pa_pc, ih, buf, sizeof(buf)); 176 177 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 178 printf(": unable to establish interrupt"); 179 if (intrstr) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 return; 183 } 184 185 /* Setup packet buffers and DMA descriptors. */ 186 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 187 if (p == NULL) { 188 printf(": cannot malloc buffers\n"); 189 return; 190 } 191 p = (void *)roundup((vaddr_t)p, 0x800); 192 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 193 194 sc->sc_rxlist = (void *)p; 195 p += 0x800; 196 sc->sc_txlist = (void *)p; 197 p += 0x800; 198 199 dp = sc->sc_rxlist; 200 for (i = 0; i < NRXBUF; i++) { 201 sc->sc_rxbuf[i] = p; 202 dp->address = htole32(vtophys((vaddr_t)p)); 203 dp->cmd = htole32(GMAC_OWN); 204 dp++; 205 p += 2048; 206 } 207 208 dp = sc->sc_txlist; 209 for (i = 0; i < NTXBUF; i++) { 210 sc->sc_txbuf[i] = p; 211 dp->address = htole32(vtophys((vaddr_t)p)); 212 dp++; 213 p += 2048; 214 } 215 216 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 217 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 218 219 callout_init(&sc->sc_tick_ch, 0); 220 221 gmac_reset(sc); 222 gmac_init_mac(sc); 223 224 memcpy(ifp->if_xname, xname, IFNAMSIZ); 225 ifp->if_softc = sc; 226 ifp->if_ioctl = gmac_ioctl; 227 ifp->if_start = gmac_start; 228 ifp->if_watchdog = gmac_watchdog; 229 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 230 IFQ_SET_READY(&ifp->if_snd); 231 232 mii->mii_ifp = ifp; 233 mii->mii_readreg = gmac_mii_readreg; 234 mii->mii_writereg = gmac_mii_writereg; 235 mii->mii_statchg = gmac_mii_statchg; 236 237 sc->sc_ethercom.ec_mii = mii; 238 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 239 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 240 241 /* Choose a default media. */ 242 if (LIST_FIRST(&mii->mii_phys) == NULL) { 243 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 244 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 245 } else 246 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 247 248 if_attach(ifp); 249 if_deferred_start_init(ifp, NULL); 250 ether_ifattach(ifp, laddr); 251 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 252 RND_FLAG_DEFAULT); 253 } 254 255 u_int 256 gmac_read_reg(struct gmac_softc *sc, int reg) 257 { 258 return in32rb(sc->sc_reg + reg); 259 } 260 261 void 262 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 263 { 264 out32rb(sc->sc_reg + reg, val); 265 } 266 267 void 268 gmac_start_txdma(struct gmac_softc *sc) 269 { 270 u_int x; 271 272 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 273 x |= 1; 274 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 275 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 276 x |= 1; 277 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 278 } 279 280 void 281 gmac_start_rxdma(struct gmac_softc *sc) 282 { 283 u_int x; 284 285 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 286 x |= 1; 287 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 288 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 289 x |= 1; 290 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 291 } 292 293 void 294 gmac_stop_txdma(struct gmac_softc *sc) 295 { 296 u_int x; 297 298 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 299 x &= ~1; 300 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 301 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 302 x &= ~1; 303 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 304 } 305 306 void 307 gmac_stop_rxdma(struct gmac_softc *sc) 308 { 309 u_int x; 310 311 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 312 x &= ~1; 313 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 314 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 315 x &= ~1; 316 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 317 } 318 319 int 320 gmac_intr(void *v) 321 { 322 struct gmac_softc *sc = v; 323 u_int status; 324 325 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 326 if (status == 0) 327 return 0; 328 329 if (status & GMAC_INT_RXDONE) 330 gmac_rint(sc); 331 332 if (status & GMAC_INT_TXEMPTY) 333 gmac_tint(sc); 334 335 rnd_add_uint32(&sc->sc_rnd_source, status); 336 return 1; 337 } 338 339 void 340 gmac_tint(struct gmac_softc *sc) 341 { 342 struct ifnet *ifp = &sc->sc_if; 343 344 ifp->if_flags &= ~IFF_OACTIVE; 345 ifp->if_timer = 0; 346 if_schedule_deferred_start(ifp); 347 } 348 349 void 350 gmac_rint(struct gmac_softc *sc) 351 { 352 struct ifnet *ifp = &sc->sc_if; 353 volatile struct gmac_dma *dp; 354 struct mbuf *m; 355 int i, j, len; 356 u_int cmd; 357 358 for (i = sc->sc_rxlast;; i++) { 359 if (i == NRXBUF) 360 i = 0; 361 362 dp = &sc->sc_rxlist[i]; 363 cmd = le32toh(dp->cmd); 364 if (cmd & GMAC_OWN) 365 break; 366 len = (cmd >> 16) & GMAC_LEN_MASK; 367 len -= 4; /* CRC */ 368 369 if (le32toh(dp->cmd_hi) & 0x40000000) { 370 ifp->if_ierrors++; 371 goto next; 372 } 373 374 m = gmac_get(sc, sc->sc_rxbuf[i], len); 375 if (m == NULL) { 376 ifp->if_ierrors++; 377 goto next; 378 } 379 380 if_percpuq_enqueue(ifp->if_percpuq, m); 381 382 next: 383 dp->cmd_hi = 0; 384 __asm volatile ("sync"); 385 dp->cmd = htole32(GMAC_OWN); 386 } 387 sc->sc_rxlast = i; 388 389 /* XXX Make sure free buffers have GMAC_OWN. */ 390 i++; 391 for (j = 1; j < NRXBUF; j++) { 392 if (i == NRXBUF) 393 i = 0; 394 dp = &sc->sc_rxlist[i++]; 395 dp->cmd = htole32(GMAC_OWN); 396 } 397 } 398 399 struct mbuf * 400 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 401 { 402 struct mbuf *m; 403 struct mbuf *top, **mp; 404 int len; 405 406 MGETHDR(m, M_DONTWAIT, MT_DATA); 407 if (m == 0) 408 return 0; 409 m_set_rcvif(m, &sc->sc_if); 410 m->m_pkthdr.len = totlen; 411 len = MHLEN; 412 top = 0; 413 mp = ⊤ 414 415 while (totlen > 0) { 416 if (top) { 417 MGET(m, M_DONTWAIT, MT_DATA); 418 if (m == 0) { 419 m_freem(top); 420 return 0; 421 } 422 len = MLEN; 423 } 424 if (totlen >= MINCLSIZE) { 425 MCLGET(m, M_DONTWAIT); 426 if ((m->m_flags & M_EXT) == 0) { 427 m_free(m); 428 m_freem(top); 429 return 0; 430 } 431 len = MCLBYTES; 432 } 433 m->m_len = len = min(totlen, len); 434 memcpy(mtod(m, void *), pkt, len); 435 pkt += len; 436 totlen -= len; 437 *mp = m; 438 mp = &m->m_next; 439 } 440 441 return top; 442 } 443 444 void 445 gmac_start(struct ifnet *ifp) 446 { 447 struct gmac_softc *sc = ifp->if_softc; 448 struct mbuf *m; 449 void *buff; 450 int i, tlen; 451 volatile struct gmac_dma *dp; 452 453 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 454 return; 455 456 for (;;) { 457 if (ifp->if_flags & IFF_OACTIVE) 458 break; 459 460 IFQ_DEQUEUE(&ifp->if_snd, m); 461 if (m == 0) 462 break; 463 464 /* 5 seconds to watch for failing to transmit */ 465 ifp->if_timer = 5; 466 ifp->if_opackets++; /* # of pkts */ 467 468 i = sc->sc_txnext; 469 buff = sc->sc_txbuf[i]; 470 tlen = gmac_put(sc, buff, m); 471 472 dp = &sc->sc_txlist[i]; 473 dp->cmd_hi = 0; 474 dp->address_hi = 0; 475 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 476 477 i++; 478 if (i == NTXBUF) 479 i = 0; 480 __asm volatile ("sync"); 481 482 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 483 sc->sc_txnext = i; 484 485 /* 486 * If BPF is listening on this interface, let it see the 487 * packet before we commit it to the wire. 488 */ 489 bpf_mtap(ifp, m, BPF_D_OUT); 490 m_freem(m); 491 492 i++; 493 if (i == NTXBUF) 494 i = 0; 495 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 496 ifp->if_flags |= IFF_OACTIVE; 497 break; 498 } 499 } 500 } 501 502 int 503 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 504 { 505 int len, tlen = 0; 506 507 for (; m; m = m->m_next) { 508 len = m->m_len; 509 if (len == 0) 510 continue; 511 memcpy(buff, mtod(m, void *), len); 512 buff += len; 513 tlen += len; 514 } 515 if (tlen > 2048) 516 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 517 518 return tlen; 519 } 520 521 void 522 gmac_reset(struct gmac_softc *sc) 523 { 524 int i, s; 525 526 s = splnet(); 527 528 gmac_stop_txdma(sc); 529 gmac_stop_rxdma(sc); 530 531 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 532 for (i = 10; i > 0; i--) { 533 delay(300000); /* XXX long delay */ 534 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 535 break; 536 } 537 if (i == 0) 538 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 539 540 sc->sc_txnext = 0; 541 sc->sc_rxlast = 0; 542 for (i = 0; i < NRXBUF; i++) 543 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 544 __asm volatile ("sync"); 545 546 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 547 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 548 vtophys((vaddr_t)sc->sc_txlist)); 549 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 550 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 551 vtophys((vaddr_t)sc->sc_rxlist)); 552 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 553 554 splx(s); 555 } 556 557 void 558 gmac_stop(struct gmac_softc *sc) 559 { 560 struct ifnet *ifp = &sc->sc_if; 561 int s; 562 563 s = splnet(); 564 565 callout_stop(&sc->sc_tick_ch); 566 mii_down(&sc->sc_mii); 567 568 gmac_stop_txdma(sc); 569 gmac_stop_rxdma(sc); 570 571 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 572 573 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 574 ifp->if_timer = 0; 575 576 splx(s); 577 } 578 579 void 580 gmac_init_mac(struct gmac_softc *sc) 581 { 582 int i, tb; 583 char *laddr = sc->sc_laddr; 584 585 if ((mfpvr() >> 16) == MPC601) 586 tb = mfrtcl(); 587 else 588 tb = mftbl(); 589 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 590 591 /* init-mii */ 592 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 593 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 594 595 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 596 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 597 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 598 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 599 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 600 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 601 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 602 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 603 gmac_write_reg(sc, GMAC_PASIZE, 7); 604 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 605 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT, 0x10); 606 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 607 608 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 609 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 610 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 611 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 612 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 613 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 614 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 615 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 616 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 617 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 618 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 619 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 620 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 621 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 622 623 for (i = 0; i < 0x6c; i += 4) 624 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 625 626 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 627 628 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 629 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 630 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 631 } else { 632 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 633 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 634 } 635 636 if (0) /* g-bit? */ 637 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 638 else 639 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 640 } 641 642 void 643 gmac_setladrf(struct gmac_softc *sc) 644 { 645 struct ifnet *ifp = &sc->sc_if; 646 struct ether_multi *enm; 647 struct ether_multistep step; 648 struct ethercom *ec = &sc->sc_ethercom; 649 uint32_t crc; 650 uint32_t hash[16]; 651 u_int v; 652 int i; 653 654 /* Clear hash table */ 655 for (i = 0; i < 16; i++) 656 hash[i] = 0; 657 658 /* Get current RX configuration */ 659 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 660 661 if ((ifp->if_flags & IFF_PROMISC) != 0) { 662 /* Turn on promiscuous mode; turn off the hash filter */ 663 v |= GMAC_RXMAC_PR; 664 v &= ~GMAC_RXMAC_HEN; 665 ifp->if_flags |= IFF_ALLMULTI; 666 goto chipit; 667 } 668 669 /* Turn off promiscuous mode; turn on the hash filter */ 670 v &= ~GMAC_RXMAC_PR; 671 v |= GMAC_RXMAC_HEN; 672 673 /* 674 * Set up multicast address filter by passing all multicast addresses 675 * through a crc generator, and then using the high order 8 bits as an 676 * index into the 256 bit logical address filter. The high order bit 677 * selects the word, while the rest of the bits select the bit within 678 * the word. 679 */ 680 681 ETHER_FIRST_MULTI(step, ec, enm); 682 while (enm != NULL) { 683 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 684 /* 685 * We must listen to a range of multicast addresses. 686 * For now, just accept all multicasts, rather than 687 * trying to set only those filter bits needed to match 688 * the range. (At this time, the only use of address 689 * ranges is for IP multicast routing, for which the 690 * range is big enough to require all bits set.) 691 */ 692 for (i = 0; i < 16; i++) 693 hash[i] = 0xffff; 694 ifp->if_flags |= IFF_ALLMULTI; 695 goto chipit; 696 } 697 698 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 699 700 /* Just want the 8 most significant bits. */ 701 crc >>= 24; 702 703 /* Set the corresponding bit in the filter. */ 704 hash[crc >> 4] |= 1 << (crc & 0xf); 705 706 ETHER_NEXT_MULTI(step, enm); 707 } 708 709 ifp->if_flags &= ~IFF_ALLMULTI; 710 711 chipit: 712 /* Now load the hash table into the chip */ 713 for (i = 0; i < 16; i++) 714 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 715 716 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 717 } 718 719 void 720 gmac_init(struct gmac_softc *sc) 721 { 722 struct ifnet *ifp = &sc->sc_if; 723 724 gmac_stop_txdma(sc); 725 gmac_stop_rxdma(sc); 726 727 gmac_init_mac(sc); 728 gmac_setladrf(sc); 729 730 gmac_start_txdma(sc); 731 gmac_start_rxdma(sc); 732 733 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 734 735 ifp->if_flags |= IFF_RUNNING; 736 ifp->if_flags &= ~IFF_OACTIVE; 737 ifp->if_timer = 0; 738 739 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 740 741 gmac_start(ifp); 742 } 743 744 int 745 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 746 { 747 struct gmac_softc *sc = ifp->if_softc; 748 struct ifaddr *ifa = (struct ifaddr *)data; 749 struct ifreq *ifr = (struct ifreq *)data; 750 int s, error = 0; 751 752 s = splnet(); 753 754 switch (cmd) { 755 756 case SIOCINITIFADDR: 757 ifp->if_flags |= IFF_UP; 758 759 gmac_init(sc); 760 switch (ifa->ifa_addr->sa_family) { 761 #ifdef INET 762 case AF_INET: 763 arp_ifinit(ifp, ifa); 764 break; 765 #endif 766 default: 767 break; 768 } 769 break; 770 771 case SIOCSIFFLAGS: 772 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 773 break; 774 /* XXX see the comment in ed_ioctl() about code re-use */ 775 if ((ifp->if_flags & IFF_UP) == 0 && 776 (ifp->if_flags & IFF_RUNNING) != 0) { 777 /* 778 * If interface is marked down and it is running, then 779 * stop it. 780 */ 781 gmac_stop(sc); 782 ifp->if_flags &= ~IFF_RUNNING; 783 } else if ((ifp->if_flags & IFF_UP) != 0 && 784 (ifp->if_flags & IFF_RUNNING) == 0) { 785 /* 786 * If interface is marked up and it is stopped, then 787 * start it. 788 */ 789 gmac_init(sc); 790 } else { 791 /* 792 * Reset the interface to pick up changes in any other 793 * flags that affect hardware registers. 794 */ 795 gmac_reset(sc); 796 gmac_init(sc); 797 } 798 #ifdef GMAC_DEBUG 799 if (ifp->if_flags & IFF_DEBUG) 800 sc->sc_flags |= GMAC_DEBUGFLAG; 801 #endif 802 break; 803 804 default: 805 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 806 /* 807 * Multicast list has changed; set the hardware filter 808 * accordingly. 809 */ 810 if (ifp->if_flags & IFF_RUNNING) { 811 gmac_init(sc); 812 /* gmac_setladrf(sc); */ 813 } 814 error = 0; 815 } 816 break; 817 } 818 819 splx(s); 820 return error; 821 } 822 823 void 824 gmac_watchdog(struct ifnet *ifp) 825 { 826 struct gmac_softc *sc = ifp->if_softc; 827 828 printf("%s: device timeout\n", ifp->if_xname); 829 ifp->if_oerrors++; 830 831 gmac_reset(sc); 832 gmac_init(sc); 833 } 834 835 int 836 gmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 837 { 838 struct gmac_softc *sc = device_private(self); 839 int i; 840 841 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 842 0x60020000 | (phy << 23) | (reg << 18)); 843 844 for (i = 1000; i >= 0; i -= 10) { 845 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 846 break; 847 delay(10); 848 } 849 if (i < 0) { 850 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 851 return ETIMEDOUT; 852 } 853 854 *val = gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 855 return 0; 856 } 857 858 int 859 gmac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 860 { 861 struct gmac_softc *sc = device_private(self); 862 int i; 863 864 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 865 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 866 867 for (i = 1000; i >= 0; i -= 10) { 868 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 869 break; 870 delay(10); 871 } 872 if (i < 0) { 873 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 874 return ETIMEDOUT; 875 } 876 877 return 0; 878 } 879 880 void 881 gmac_mii_statchg(struct ifnet *ifp) 882 { 883 struct gmac_softc *sc = ifp->if_softc; 884 885 gmac_stop_txdma(sc); 886 gmac_stop_rxdma(sc); 887 888 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 889 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 890 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 891 } else { 892 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 893 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 894 } 895 896 if (0) /* g-bit? */ 897 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 898 else 899 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 900 901 gmac_start_txdma(sc); 902 gmac_start_rxdma(sc); 903 } 904 905 void 906 gmac_mii_tick(void *v) 907 { 908 struct gmac_softc *sc = v; 909 int s; 910 911 s = splnet(); 912 mii_tick(&sc->sc_mii); 913 splx(s); 914 915 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 916 } 917
Indexes created Wed Oct 01 07:09:59 GMT 2025