if_gm.c revision 1.56
1 /* $NetBSD: if_gm.c,v 1.56 2019/11/10 21:16:29 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.56 2019/11/10 21:16:29 chs Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <sys/rndsource.h> 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 49 #include <net/bpf.h> 50 51 #ifdef INET 52 #include <netinet/in.h> 53 #include <netinet/if_inarp.h> 54 #endif 55 56 #include <dev/mii/mii.h> 57 #include <dev/mii/miivar.h> 58 59 #include <dev/pci/pcivar.h> 60 #include <dev/pci/pcireg.h> 61 #include <dev/pci/pcidevs.h> 62 63 #include <dev/ofw/openfirm.h> 64 #include <macppc/dev/if_gmreg.h> 65 #include <machine/pio.h> 66 #include <powerpc/oea/spr.h> 67 68 #define NTXBUF 4 69 #define NRXBUF 32 70 71 struct gmac_softc { 72 device_t sc_dev; 73 struct ethercom sc_ethercom; 74 vaddr_t sc_reg; 75 struct gmac_dma *sc_txlist; 76 struct gmac_dma *sc_rxlist; 77 int sc_txnext; 78 int sc_rxlast; 79 void *sc_txbuf[NTXBUF]; 80 void *sc_rxbuf[NRXBUF]; 81 struct mii_data sc_mii; 82 struct callout sc_tick_ch; 83 char sc_laddr[6]; 84 85 krndsource_t sc_rnd_source; /* random source */ 86 }; 87 88 #define sc_if sc_ethercom.ec_if 89 90 int gmac_match(device_t, cfdata_t, void *); 91 void gmac_attach(device_t, device_t, void *); 92 93 static inline u_int gmac_read_reg(struct gmac_softc *, int); 94 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 95 96 static inline void gmac_start_txdma(struct gmac_softc *); 97 static inline void gmac_start_rxdma(struct gmac_softc *); 98 static inline void gmac_stop_txdma(struct gmac_softc *); 99 static inline void gmac_stop_rxdma(struct gmac_softc *); 100 101 int gmac_intr(void *); 102 void gmac_tint(struct gmac_softc *); 103 void gmac_rint(struct gmac_softc *); 104 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 105 void gmac_start(struct ifnet *); 106 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 107 108 void gmac_stop(struct gmac_softc *); 109 void gmac_reset(struct gmac_softc *); 110 void gmac_init(struct gmac_softc *); 111 void gmac_init_mac(struct gmac_softc *); 112 void gmac_setladrf(struct gmac_softc *); 113 114 int gmac_ioctl(struct ifnet *, u_long, void *); 115 void gmac_watchdog(struct ifnet *); 116 117 int gmac_mii_readreg(device_t, int, int, uint16_t *); 118 int gmac_mii_writereg(device_t, int, int, uint16_t); 119 void gmac_mii_statchg(struct ifnet *); 120 void gmac_mii_tick(void *); 121 122 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 123 gmac_match, gmac_attach, NULL, NULL); 124 125 int 126 gmac_match(device_t parent, cfdata_t match, void *aux) 127 { 128 struct pci_attach_args *pa = aux; 129 130 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 131 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 132 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 134 return 1; 135 136 return 0; 137 } 138 139 void 140 gmac_attach(device_t parent, device_t self, void *aux) 141 { 142 struct gmac_softc * const sc = device_private(self); 143 struct pci_attach_args * const pa = aux; 144 struct ifnet * const ifp = &sc->sc_if; 145 struct mii_data * const mii = &sc->sc_mii; 146 pci_intr_handle_t ih; 147 const char *intrstr = NULL; 148 const char * const xname = device_xname(self); 149 int node, i; 150 char *p; 151 struct gmac_dma *dp; 152 uint32_t reg[10]; 153 u_char laddr[6]; 154 char buf[PCI_INTRSTR_LEN]; 155 156 sc->sc_dev = self; 157 158 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 159 if (node == 0) { 160 printf(": cannot find gmac node\n"); 161 return; 162 } 163 164 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 165 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 166 167 memcpy(sc->sc_laddr, laddr, sizeof laddr); 168 sc->sc_reg = reg[2]; 169 170 if (pci_intr_map(pa, &ih)) { 171 printf(": unable to map interrupt\n"); 172 return; 173 } 174 intrstr = pci_intr_string(pa->pa_pc, ih, buf, sizeof(buf)); 175 176 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 177 printf(": unable to establish interrupt"); 178 if (intrstr) 179 printf(" at %s", intrstr); 180 printf("\n"); 181 return; 182 } 183 184 /* Setup packet buffers and DMA descriptors. */ 185 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_WAITOK); 186 p = (void *)roundup((vaddr_t)p, 0x800); 187 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 188 189 sc->sc_rxlist = (void *)p; 190 p += 0x800; 191 sc->sc_txlist = (void *)p; 192 p += 0x800; 193 194 dp = sc->sc_rxlist; 195 for (i = 0; i < NRXBUF; i++) { 196 sc->sc_rxbuf[i] = p; 197 dp->address = htole32(vtophys((vaddr_t)p)); 198 dp->cmd = htole32(GMAC_OWN); 199 dp++; 200 p += 2048; 201 } 202 203 dp = sc->sc_txlist; 204 for (i = 0; i < NTXBUF; i++) { 205 sc->sc_txbuf[i] = p; 206 dp->address = htole32(vtophys((vaddr_t)p)); 207 dp++; 208 p += 2048; 209 } 210 211 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 212 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 213 214 callout_init(&sc->sc_tick_ch, 0); 215 216 gmac_reset(sc); 217 gmac_init_mac(sc); 218 219 memcpy(ifp->if_xname, xname, IFNAMSIZ); 220 ifp->if_softc = sc; 221 ifp->if_ioctl = gmac_ioctl; 222 ifp->if_start = gmac_start; 223 ifp->if_watchdog = gmac_watchdog; 224 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 225 IFQ_SET_READY(&ifp->if_snd); 226 227 mii->mii_ifp = ifp; 228 mii->mii_readreg = gmac_mii_readreg; 229 mii->mii_writereg = gmac_mii_writereg; 230 mii->mii_statchg = gmac_mii_statchg; 231 232 sc->sc_ethercom.ec_mii = mii; 233 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 234 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 235 236 /* Choose a default media. */ 237 if (LIST_FIRST(&mii->mii_phys) == NULL) { 238 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 239 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 240 } else 241 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 242 243 if_attach(ifp); 244 if_deferred_start_init(ifp, NULL); 245 ether_ifattach(ifp, laddr); 246 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 247 RND_FLAG_DEFAULT); 248 } 249 250 u_int 251 gmac_read_reg(struct gmac_softc *sc, int reg) 252 { 253 return in32rb(sc->sc_reg + reg); 254 } 255 256 void 257 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 258 { 259 out32rb(sc->sc_reg + reg, val); 260 } 261 262 void 263 gmac_start_txdma(struct gmac_softc *sc) 264 { 265 u_int x; 266 267 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 268 x |= 1; 269 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 270 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 271 x |= 1; 272 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 273 } 274 275 void 276 gmac_start_rxdma(struct gmac_softc *sc) 277 { 278 u_int x; 279 280 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 281 x |= 1; 282 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 283 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 284 x |= 1; 285 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 286 } 287 288 void 289 gmac_stop_txdma(struct gmac_softc *sc) 290 { 291 u_int x; 292 293 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 294 x &= ~1; 295 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 296 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 297 x &= ~1; 298 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 299 } 300 301 void 302 gmac_stop_rxdma(struct gmac_softc *sc) 303 { 304 u_int x; 305 306 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 307 x &= ~1; 308 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 309 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 310 x &= ~1; 311 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 312 } 313 314 int 315 gmac_intr(void *v) 316 { 317 struct gmac_softc *sc = v; 318 u_int status; 319 320 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 321 if (status == 0) 322 return 0; 323 324 if (status & GMAC_INT_RXDONE) 325 gmac_rint(sc); 326 327 if (status & GMAC_INT_TXEMPTY) 328 gmac_tint(sc); 329 330 rnd_add_uint32(&sc->sc_rnd_source, status); 331 return 1; 332 } 333 334 void 335 gmac_tint(struct gmac_softc *sc) 336 { 337 struct ifnet *ifp = &sc->sc_if; 338 339 ifp->if_flags &= ~IFF_OACTIVE; 340 ifp->if_timer = 0; 341 if_schedule_deferred_start(ifp); 342 } 343 344 void 345 gmac_rint(struct gmac_softc *sc) 346 { 347 struct ifnet *ifp = &sc->sc_if; 348 volatile struct gmac_dma *dp; 349 struct mbuf *m; 350 int i, j, len; 351 u_int cmd; 352 353 for (i = sc->sc_rxlast;; i++) { 354 if (i == NRXBUF) 355 i = 0; 356 357 dp = &sc->sc_rxlist[i]; 358 cmd = le32toh(dp->cmd); 359 if (cmd & GMAC_OWN) 360 break; 361 len = (cmd >> 16) & GMAC_LEN_MASK; 362 len -= 4; /* CRC */ 363 364 if (le32toh(dp->cmd_hi) & 0x40000000) { 365 ifp->if_ierrors++; 366 goto next; 367 } 368 369 m = gmac_get(sc, sc->sc_rxbuf[i], len); 370 if (m == NULL) { 371 ifp->if_ierrors++; 372 goto next; 373 } 374 375 if_percpuq_enqueue(ifp->if_percpuq, m); 376 377 next: 378 dp->cmd_hi = 0; 379 __asm volatile ("sync"); 380 dp->cmd = htole32(GMAC_OWN); 381 } 382 sc->sc_rxlast = i; 383 384 /* XXX Make sure free buffers have GMAC_OWN. */ 385 i++; 386 for (j = 1; j < NRXBUF; j++) { 387 if (i == NRXBUF) 388 i = 0; 389 dp = &sc->sc_rxlist[i++]; 390 dp->cmd = htole32(GMAC_OWN); 391 } 392 } 393 394 struct mbuf * 395 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 396 { 397 struct mbuf *m; 398 struct mbuf *top, **mp; 399 int len; 400 401 MGETHDR(m, M_DONTWAIT, MT_DATA); 402 if (m == 0) 403 return 0; 404 m_set_rcvif(m, &sc->sc_if); 405 m->m_pkthdr.len = totlen; 406 len = MHLEN; 407 top = 0; 408 mp = ⊤ 409 410 while (totlen > 0) { 411 if (top) { 412 MGET(m, M_DONTWAIT, MT_DATA); 413 if (m == 0) { 414 m_freem(top); 415 return 0; 416 } 417 len = MLEN; 418 } 419 if (totlen >= MINCLSIZE) { 420 MCLGET(m, M_DONTWAIT); 421 if ((m->m_flags & M_EXT) == 0) { 422 m_free(m); 423 m_freem(top); 424 return 0; 425 } 426 len = MCLBYTES; 427 } 428 m->m_len = len = imin(totlen, len); 429 memcpy(mtod(m, void *), pkt, len); 430 pkt = (char *)pkt + len; 431 totlen -= len; 432 *mp = m; 433 mp = &m->m_next; 434 } 435 436 return top; 437 } 438 439 void 440 gmac_start(struct ifnet *ifp) 441 { 442 struct gmac_softc *sc = ifp->if_softc; 443 struct mbuf *m; 444 void *buff; 445 int i, tlen; 446 volatile struct gmac_dma *dp; 447 448 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 449 return; 450 451 for (;;) { 452 if (ifp->if_flags & IFF_OACTIVE) 453 break; 454 455 IFQ_DEQUEUE(&ifp->if_snd, m); 456 if (m == 0) 457 break; 458 459 /* 5 seconds to watch for failing to transmit */ 460 ifp->if_timer = 5; 461 ifp->if_opackets++; /* # of pkts */ 462 463 i = sc->sc_txnext; 464 buff = sc->sc_txbuf[i]; 465 tlen = gmac_put(sc, buff, m); 466 467 dp = &sc->sc_txlist[i]; 468 dp->cmd_hi = 0; 469 dp->address_hi = 0; 470 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 471 472 i++; 473 if (i == NTXBUF) 474 i = 0; 475 __asm volatile ("sync"); 476 477 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 478 sc->sc_txnext = i; 479 480 /* 481 * If BPF is listening on this interface, let it see the 482 * packet before we commit it to the wire. 483 */ 484 bpf_mtap(ifp, m, BPF_D_OUT); 485 m_freem(m); 486 487 i++; 488 if (i == NTXBUF) 489 i = 0; 490 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 491 ifp->if_flags |= IFF_OACTIVE; 492 break; 493 } 494 } 495 } 496 497 int 498 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 499 { 500 int len, tlen = 0; 501 502 for (; m; m = m->m_next) { 503 len = m->m_len; 504 if (len == 0) 505 continue; 506 memcpy(buff, mtod(m, void *), len); 507 buff = (char *)buff + len; 508 tlen += len; 509 } 510 if (tlen > 2048) 511 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 512 513 return tlen; 514 } 515 516 void 517 gmac_reset(struct gmac_softc *sc) 518 { 519 int i, s; 520 521 s = splnet(); 522 523 gmac_stop_txdma(sc); 524 gmac_stop_rxdma(sc); 525 526 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 527 for (i = 10; i > 0; i--) { 528 delay(300000); /* XXX long delay */ 529 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 530 break; 531 } 532 if (i == 0) 533 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 534 535 sc->sc_txnext = 0; 536 sc->sc_rxlast = 0; 537 for (i = 0; i < NRXBUF; i++) 538 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 539 __asm volatile ("sync"); 540 541 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 542 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 543 vtophys((vaddr_t)sc->sc_txlist)); 544 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 545 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 546 vtophys((vaddr_t)sc->sc_rxlist)); 547 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 548 549 splx(s); 550 } 551 552 void 553 gmac_stop(struct gmac_softc *sc) 554 { 555 struct ifnet *ifp = &sc->sc_if; 556 int s; 557 558 s = splnet(); 559 560 callout_stop(&sc->sc_tick_ch); 561 mii_down(&sc->sc_mii); 562 563 gmac_stop_txdma(sc); 564 gmac_stop_rxdma(sc); 565 566 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 567 568 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 569 ifp->if_timer = 0; 570 571 splx(s); 572 } 573 574 void 575 gmac_init_mac(struct gmac_softc *sc) 576 { 577 int i, tb; 578 char *laddr = sc->sc_laddr; 579 580 if ((mfpvr() >> 16) == MPC601) 581 tb = mfrtcl(); 582 else 583 tb = mftbl(); 584 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 585 586 /* init-mii */ 587 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 588 gmac_mii_writereg(sc->sc_dev, 0, 0, 0x1000); 589 590 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 591 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 592 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 593 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 594 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 595 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 596 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 597 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 598 gmac_write_reg(sc, GMAC_PASIZE, 7); 599 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 600 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT, 0x10); 601 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 602 603 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 604 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 605 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 606 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 607 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 608 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 609 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 610 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 611 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 612 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 613 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 614 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 615 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 616 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 617 618 for (i = 0; i < 0x6c; i += 4) 619 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 620 621 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 622 623 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 624 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 625 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 626 } else { 627 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 628 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 629 } 630 631 if (0) /* g-bit? */ 632 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 633 else 634 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 635 } 636 637 void 638 gmac_setladrf(struct gmac_softc *sc) 639 { 640 struct ifnet *ifp = &sc->sc_if; 641 struct ether_multi *enm; 642 struct ether_multistep step; 643 struct ethercom *ec = &sc->sc_ethercom; 644 uint32_t crc; 645 uint32_t hash[16]; 646 u_int v; 647 int i; 648 649 /* Clear hash table */ 650 for (i = 0; i < 16; i++) 651 hash[i] = 0; 652 653 /* Get current RX configuration */ 654 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 655 656 if ((ifp->if_flags & IFF_PROMISC) != 0) { 657 /* Turn on promiscuous mode; turn off the hash filter */ 658 v |= GMAC_RXMAC_PR; 659 v &= ~GMAC_RXMAC_HEN; 660 ifp->if_flags |= IFF_ALLMULTI; 661 goto chipit; 662 } 663 664 /* Turn off promiscuous mode; turn on the hash filter */ 665 v &= ~GMAC_RXMAC_PR; 666 v |= GMAC_RXMAC_HEN; 667 668 /* 669 * Set up multicast address filter by passing all multicast addresses 670 * through a crc generator, and then using the high order 8 bits as an 671 * index into the 256 bit logical address filter. The high order bit 672 * selects the word, while the rest of the bits select the bit within 673 * the word. 674 */ 675 676 ETHER_LOCK(ec); 677 ETHER_FIRST_MULTI(step, ec, enm); 678 while (enm != NULL) { 679 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 680 /* 681 * We must listen to a range of multicast addresses. 682 * For now, just accept all multicasts, rather than 683 * trying to set only those filter bits needed to match 684 * the range. (At this time, the only use of address 685 * ranges is for IP multicast routing, for which the 686 * range is big enough to require all bits set.) 687 */ 688 for (i = 0; i < 16; i++) 689 hash[i] = 0xffff; 690 ifp->if_flags |= IFF_ALLMULTI; 691 ETHER_UNLOCK(ec); 692 goto chipit; 693 } 694 695 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 696 697 /* Just want the 8 most significant bits. */ 698 crc >>= 24; 699 700 /* Set the corresponding bit in the filter. */ 701 hash[crc >> 4] |= 1 << (crc & 0xf); 702 703 ETHER_NEXT_MULTI(step, enm); 704 } 705 ETHER_UNLOCK(ec); 706 707 ifp->if_flags &= ~IFF_ALLMULTI; 708 709 chipit: 710 /* Now load the hash table into the chip */ 711 for (i = 0; i < 16; i++) 712 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 713 714 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 715 } 716 717 void 718 gmac_init(struct gmac_softc *sc) 719 { 720 struct ifnet *ifp = &sc->sc_if; 721 722 gmac_stop_txdma(sc); 723 gmac_stop_rxdma(sc); 724 725 gmac_init_mac(sc); 726 gmac_setladrf(sc); 727 728 gmac_start_txdma(sc); 729 gmac_start_rxdma(sc); 730 731 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 732 733 ifp->if_flags |= IFF_RUNNING; 734 ifp->if_flags &= ~IFF_OACTIVE; 735 ifp->if_timer = 0; 736 737 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 738 739 gmac_start(ifp); 740 } 741 742 int 743 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 744 { 745 struct gmac_softc *sc = ifp->if_softc; 746 struct ifaddr *ifa = (struct ifaddr *)data; 747 int s, error = 0; 748 749 s = splnet(); 750 751 switch (cmd) { 752 753 case SIOCINITIFADDR: 754 ifp->if_flags |= IFF_UP; 755 756 gmac_init(sc); 757 switch (ifa->ifa_addr->sa_family) { 758 #ifdef INET 759 case AF_INET: 760 arp_ifinit(ifp, ifa); 761 break; 762 #endif 763 default: 764 break; 765 } 766 break; 767 768 case SIOCSIFFLAGS: 769 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 770 break; 771 /* XXX see the comment in ed_ioctl() about code re-use */ 772 if ((ifp->if_flags & IFF_UP) == 0 && 773 (ifp->if_flags & IFF_RUNNING) != 0) { 774 /* 775 * If interface is marked down and it is running, then 776 * stop it. 777 */ 778 gmac_stop(sc); 779 ifp->if_flags &= ~IFF_RUNNING; 780 } else if ((ifp->if_flags & IFF_UP) != 0 && 781 (ifp->if_flags & IFF_RUNNING) == 0) { 782 /* 783 * If interface is marked up and it is stopped, then 784 * start it. 785 */ 786 gmac_init(sc); 787 } else { 788 /* 789 * Reset the interface to pick up changes in any other 790 * flags that affect hardware registers. 791 */ 792 gmac_reset(sc); 793 gmac_init(sc); 794 } 795 #ifdef GMAC_DEBUG 796 if (ifp->if_flags & IFF_DEBUG) 797 sc->sc_flags |= GMAC_DEBUGFLAG; 798 #endif 799 break; 800 801 default: 802 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 803 /* 804 * Multicast list has changed; set the hardware filter 805 * accordingly. 806 */ 807 if (ifp->if_flags & IFF_RUNNING) { 808 gmac_init(sc); 809 /* gmac_setladrf(sc); */ 810 } 811 error = 0; 812 } 813 break; 814 } 815 816 splx(s); 817 return error; 818 } 819 820 void 821 gmac_watchdog(struct ifnet *ifp) 822 { 823 struct gmac_softc *sc = ifp->if_softc; 824 825 printf("%s: device timeout\n", ifp->if_xname); 826 ifp->if_oerrors++; 827 828 gmac_reset(sc); 829 gmac_init(sc); 830 } 831 832 int 833 gmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 834 { 835 struct gmac_softc *sc = device_private(self); 836 int i; 837 838 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 839 0x60020000 | (phy << 23) | (reg << 18)); 840 841 for (i = 1000; i >= 0; i -= 10) { 842 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 843 break; 844 delay(10); 845 } 846 if (i < 0) { 847 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 848 return ETIMEDOUT; 849 } 850 851 *val = gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 852 return 0; 853 } 854 855 int 856 gmac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 857 { 858 struct gmac_softc *sc = device_private(self); 859 int i; 860 861 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 862 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 863 864 for (i = 1000; i >= 0; i -= 10) { 865 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 866 break; 867 delay(10); 868 } 869 if (i < 0) { 870 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 871 return ETIMEDOUT; 872 } 873 874 return 0; 875 } 876 877 void 878 gmac_mii_statchg(struct ifnet *ifp) 879 { 880 struct gmac_softc *sc = ifp->if_softc; 881 882 gmac_stop_txdma(sc); 883 gmac_stop_rxdma(sc); 884 885 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 886 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 887 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 888 } else { 889 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 890 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 891 } 892 893 if (0) /* g-bit? */ 894 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 895 else 896 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 897 898 gmac_start_txdma(sc); 899 gmac_start_rxdma(sc); 900 } 901 902 void 903 gmac_mii_tick(void *v) 904 { 905 struct gmac_softc *sc = v; 906 int s; 907 908 s = splnet(); 909 mii_tick(&sc->sc_mii); 910 splx(s); 911 912 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 913 } 914
Indexes created Tue Sep 30 20:09:53 GMT 2025