kauai.c revision 1.21
1 /* $NetBSD: kauai.c,v 1.21 2007/10/17 19:55:18 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: kauai.c,v 1.21 2007/10/17 19:55:18 garbled Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <machine/bus.h> 40 #include <machine/pio.h> 41 42 #include <dev/ata/atareg.h> 43 #include <dev/ata/atavar.h> 44 #include <dev/ic/wdcvar.h> 45 46 #include <dev/ofw/openfirm.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <macppc/dev/dbdma.h> 53 54 #define WDC_REG_NPORTS 8 55 #define WDC_AUXREG_OFFSET 0x16 56 #define WDC_AUXREG_NPORTS 1 57 58 #define PIO_CONFIG_REG (0x200 >> 4) /* PIO and DMA access timing */ 59 #define DMA_CONFIG_REG (0x210 >> 4) /* UDMA access timing */ 60 61 struct kauai_softc { 62 struct wdc_softc sc_wdcdev; 63 struct ata_channel *sc_chanptr; 64 struct ata_channel sc_channel; 65 struct wdc_regs sc_wdc_regs; 66 struct ata_queue sc_queue; 67 dbdma_regmap_t *sc_dmareg; 68 dbdma_command_t *sc_dmacmd; 69 u_int sc_piotiming_r[2]; 70 u_int sc_piotiming_w[2]; 71 u_int sc_dmatiming_r[2]; 72 u_int sc_dmatiming_w[2]; 73 void (*sc_calc_timing)(struct kauai_softc *, int); 74 }; 75 76 int kauai_match __P((struct device *, struct cfdata *, void *)); 77 void kauai_attach __P((struct device *, struct device *, void *)); 78 int kauai_dma_init __P((void *, int, int, void *, size_t, int)); 79 void kauai_dma_start __P((void *, int, int)); 80 int kauai_dma_finish __P((void *, int, int, int)); 81 void kauai_set_modes __P((struct ata_channel *)); 82 static void calc_timing_kauai __P((struct kauai_softc *, int)); 83 static int getnodebypci(pci_chipset_tag_t, pcitag_t); 84 85 CFATTACH_DECL(kauai, sizeof(struct kauai_softc), 86 kauai_match, kauai_attach, NULL, wdcactivate); 87 88 int 89 kauai_match(parent, match, aux) 90 struct device *parent; 91 struct cfdata *match; 92 void *aux; 93 { 94 struct pci_attach_args *pa = aux; 95 96 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) { 97 switch (PCI_PRODUCT(pa->pa_id)) { 98 case PCI_PRODUCT_APPLE_KAUAI: 99 case PCI_PRODUCT_APPLE_UNINORTH_ATA: 100 case PCI_PRODUCT_APPLE_INTREPID2_ATA: 101 return 5; 102 } 103 } 104 105 return 0; 106 } 107 108 void 109 kauai_attach(parent, self, aux) 110 struct device *parent, *self; 111 void *aux; 112 { 113 struct kauai_softc *sc = (void *)self; 114 struct pci_attach_args *pa = aux; 115 struct ata_channel *chp = &sc->sc_channel; 116 struct wdc_regs *wdr; 117 pci_intr_handle_t ih; 118 paddr_t regbase, dmabase; 119 int node, reg[5], i; 120 121 #ifdef DIAGNOSTIC 122 if ((vaddr_t)sc->sc_dmacmd & 0x0f) { 123 printf(": bad dbdma alignment\n"); 124 return; 125 } 126 #endif 127 128 node = getnodebypci(pa->pa_pc, pa->pa_tag); 129 if (node == 0) { 130 printf(": cannot find kauai node\n"); 131 return; 132 } 133 134 if (OF_getprop(node, "assigned-addresses", reg, sizeof reg) < 12) { 135 printf(": cannot get address property\n"); 136 return; 137 } 138 regbase = reg[2] + 0x2000; 139 dmabase = reg[2] + 0x1000; 140 141 /* 142 * XXX PCI_INTERRUPT_REG seems to be wired to 0. 143 * XXX So use fixed intrpin and intrline values. 144 */ 145 if (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_INTERRUPT_REG) == 0) { 146 pa->pa_intrpin = 1; 147 pa->pa_intrline = 39; 148 } 149 150 if (pci_intr_map(pa, &ih)) { 151 printf(": unable to map interrupt\n"); 152 return; 153 } 154 printf(": interrupting at %s\n", pci_intr_string(pa->pa_pc, ih)); 155 156 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 157 158 wdr->cmd_iot = wdr->ctl_iot = pa->pa_memt; 159 160 if (bus_space_map(wdr->cmd_iot, regbase, WDC_REG_NPORTS << 4, 0, 161 &wdr->cmd_baseioh) || 162 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 163 WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) { 164 printf("%s: couldn't map registers\n", self->dv_xname); 165 return; 166 } 167 for (i = 0; i < WDC_NREG; i++) { 168 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4, 169 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 170 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 171 WDC_REG_NPORTS << 4); 172 printf("%s: couldn't subregion registers\n", 173 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 174 return; 175 } 176 } 177 178 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, wdcintr, chp) == NULL) { 179 printf("%s: unable to establish interrupt\n", self->dv_xname); 180 return; 181 } 182 183 184 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 185 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 186 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 187 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 188 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 189 sc->sc_chanptr = chp; 190 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 191 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 192 sc->sc_wdcdev.dma_arg = sc; 193 sc->sc_wdcdev.dma_init = kauai_dma_init; 194 sc->sc_wdcdev.dma_start = kauai_dma_start; 195 sc->sc_wdcdev.dma_finish = kauai_dma_finish; 196 sc->sc_wdcdev.sc_atac.atac_set_modes = kauai_set_modes; 197 sc->sc_calc_timing = calc_timing_kauai; 198 sc->sc_dmareg = (void *)dmabase; 199 200 chp->ch_channel = 0; 201 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 202 chp->ch_queue = &sc->sc_queue; 203 chp->ch_ndrive = 2; 204 wdc_init_shadow_regs(chp); 205 206 wdcattach(chp); 207 } 208 209 void 210 kauai_set_modes(chp) 211 struct ata_channel *chp; 212 { 213 struct kauai_softc *sc = (void *)chp->ch_atac; 214 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 215 struct ata_drive_datas *drvp0 = &chp->ch_drive[0]; 216 struct ata_drive_datas *drvp1 = &chp->ch_drive[1]; 217 struct ata_drive_datas *drvp; 218 int drive; 219 220 if ((drvp0->drive_flags & DRIVE) && (drvp1->drive_flags & DRIVE)) { 221 drvp0->PIO_mode = drvp1->PIO_mode = 222 min(drvp0->PIO_mode, drvp1->PIO_mode); 223 } 224 225 for (drive = 0; drive < 2; drive++) { 226 drvp = &chp->ch_drive[drive]; 227 if (drvp->drive_flags & DRIVE) { 228 (*sc->sc_calc_timing)(sc, drive); 229 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 230 PIO_CONFIG_REG, sc->sc_piotiming_r[drive]); 231 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 232 DMA_CONFIG_REG, sc->sc_dmatiming_r[drive]); 233 } 234 } 235 } 236 237 /* 238 * IDE transfer timings 239 */ 240 static const u_int pio_timing_kauai[] = { /* 0xff000fff */ 241 0x08000a92, /* Mode 0 */ 242 0x0800060f, /* 1 */ 243 0x0800038b, /* 2 */ 244 0x05000249, /* 3 */ 245 0x04000148 /* 4 */ 246 }; 247 static const u_int dma_timing_kauai[] = { /* 0x00fff000 */ 248 0x00618000, /* Mode 0 */ 249 0x00209000, /* 1 */ 250 0x00148000 /* 2 */ 251 }; 252 static const u_int udma_timing_kauai[] = { /* 0x0000ffff */ 253 0x000070c0, /* Mode 0 */ 254 0x00005d80, /* 1 */ 255 0x00004a60, /* 2 */ 256 0x00003a50, /* 3 */ 257 0x00002a30, /* 4 */ 258 0x00002921 /* 5 */ 259 }; 260 261 /* 262 * Timing calculation for Kauai. 263 */ 264 void 265 calc_timing_kauai(sc, drive) 266 struct kauai_softc *sc; 267 int drive; 268 { 269 struct ata_channel *chp = &sc->sc_channel; 270 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 271 int piomode = drvp->PIO_mode; 272 int dmamode = drvp->DMA_mode; 273 int udmamode = drvp->UDMA_mode; 274 u_int pioconf, dmaconf; 275 276 pioconf = pio_timing_kauai[piomode]; 277 278 dmaconf = 0; 279 if (drvp->drive_flags & DRIVE_DMA) 280 dmaconf |= dma_timing_kauai[dmamode]; 281 if (drvp->drive_flags & DRIVE_UDMA) 282 dmaconf |= udma_timing_kauai[udmamode]; 283 284 if (drvp->drive_flags & DRIVE_UDMA) 285 dmaconf |= 1; 286 287 sc->sc_piotiming_r[drive] = sc->sc_piotiming_w[drive] = pioconf; 288 sc->sc_dmatiming_r[drive] = sc->sc_dmatiming_w[drive] = dmaconf; 289 } 290 291 int 292 kauai_dma_init(v, channel, drive, databuf, datalen, flags) 293 void *v; 294 void *databuf; 295 size_t datalen; 296 int flags; 297 { 298 struct kauai_softc *sc = v; 299 dbdma_command_t *cmdp = sc->sc_dmacmd; 300 struct ata_channel *chp = &sc->sc_channel; 301 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 302 vaddr_t va = (vaddr_t)databuf; 303 int read = flags & WDC_DMA_READ; 304 int cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 305 u_int offset; 306 307 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG, 308 read ? sc->sc_dmatiming_r[drive] : sc->sc_dmatiming_w[drive]); 309 bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG); 310 311 offset = va & PGOFSET; 312 313 /* if va is not page-aligned, setup the first page */ 314 if (offset != 0) { 315 int rest = PAGE_SIZE - offset; /* the rest of the page */ 316 317 if (datalen > rest) { /* if continues to next page */ 318 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 319 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 320 DBDMA_BRANCH_NEVER); 321 datalen -= rest; 322 va += rest; 323 cmdp++; 324 } 325 } 326 327 /* now va is page-aligned */ 328 while (datalen > PAGE_SIZE) { 329 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 330 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 331 datalen -= PAGE_SIZE; 332 va += PAGE_SIZE; 333 cmdp++; 334 } 335 336 /* the last page (datalen <= PAGE_SIZE here) */ 337 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 338 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 339 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 340 cmdp++; 341 342 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 343 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 344 345 return 0; 346 } 347 348 void 349 kauai_dma_start(v, channel, drive) 350 void *v; 351 int channel, drive; 352 { 353 struct kauai_softc *sc = v; 354 355 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 356 } 357 358 int 359 kauai_dma_finish(v, channel, drive, read) 360 void *v; 361 int channel, drive; 362 int read; 363 { 364 struct kauai_softc *sc = v; 365 366 dbdma_stop(sc->sc_dmareg); 367 return 0; 368 } 369 370 /* 371 * Find OF-device corresponding to the PCI device. 372 */ 373 int 374 getnodebypci(pc, tag) 375 pci_chipset_tag_t pc; 376 pcitag_t tag; 377 { 378 int bus, dev, func; 379 u_int reg[5]; 380 int p, q; 381 int l, b, d, f; 382 383 pci_decompose_tag(pc, tag, &bus, &dev, &func); 384 385 for (q = OF_peer(0); q; q = p) { 386 l = OF_getprop(q, "assigned-addresses", reg, sizeof(reg)); 387 if (l > 4) { 388 b = (reg[0] >> 16) & 0xff; 389 d = (reg[0] >> 11) & 0x1f; 390 f = (reg[0] >> 8) & 0x07; 391 392 if (b == bus && d == dev && f == func) 393 return q; 394 } 395 if ((p = OF_child(q))) 396 continue; 397 while (q) { 398 if ((p = OF_peer(q))) 399 break; 400 q = OF_parent(q); 401 } 402 } 403 return 0; 404 } 405
Indexes created Thu Oct 02 14:10:14 GMT 2025