kauai.c revision 1.22
1 /* $NetBSD: kauai.c,v 1.22 2008/02/25 19:22:39 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: kauai.c,v 1.22 2008/02/25 19:22:39 matt Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <machine/bus.h> 40 #include <machine/pio.h> 41 42 #include <dev/ata/atareg.h> 43 #include <dev/ata/atavar.h> 44 #include <dev/ic/wdcvar.h> 45 46 #include <dev/ofw/openfirm.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <macppc/dev/dbdma.h> 53 54 #define WDC_REG_NPORTS 8 55 #define WDC_AUXREG_OFFSET 0x16 56 #define WDC_AUXREG_NPORTS 1 57 58 #define PIO_CONFIG_REG (0x200 >> 4) /* PIO and DMA access timing */ 59 #define DMA_CONFIG_REG (0x210 >> 4) /* UDMA access timing */ 60 61 struct kauai_softc { 62 struct wdc_softc sc_wdcdev; 63 struct ata_channel *sc_chanptr; 64 struct ata_channel sc_channel; 65 struct wdc_regs sc_wdc_regs; 66 struct ata_queue sc_queue; 67 dbdma_regmap_t *sc_dmareg; 68 dbdma_command_t *sc_dmacmd; 69 u_int sc_piotiming_r[2]; 70 u_int sc_piotiming_w[2]; 71 u_int sc_dmatiming_r[2]; 72 u_int sc_dmatiming_w[2]; 73 void (*sc_calc_timing)(struct kauai_softc *, int); 74 }; 75 76 static int kauai_match(device_t, cfdata_t, void *); 77 static void kauai_attach(device_t, device_t, void *); 78 static int kauai_dma_init(void *, int, int, void *, size_t, int); 79 static void kauai_dma_start(void *, int, int); 80 static int kauai_dma_finish(void *, int, int, int); 81 static void kauai_set_modes(struct ata_channel *); 82 static void calc_timing_kauai(struct kauai_softc *, int); 83 static int getnodebypci(pci_chipset_tag_t, pcitag_t); 84 85 CFATTACH_DECL(kauai, sizeof(struct kauai_softc), 86 kauai_match, kauai_attach, NULL, wdcactivate); 87 88 int 89 kauai_match(device_t parent, cfdata_t match, void *aux) 90 { 91 struct pci_attach_args *pa = aux; 92 93 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) { 94 switch (PCI_PRODUCT(pa->pa_id)) { 95 case PCI_PRODUCT_APPLE_KAUAI: 96 case PCI_PRODUCT_APPLE_UNINORTH_ATA: 97 case PCI_PRODUCT_APPLE_INTREPID2_ATA: 98 return 5; 99 } 100 } 101 102 return 0; 103 } 104 105 void 106 kauai_attach(device_t parent, device_t self, void *aux) 107 { 108 struct kauai_softc *sc = device_private(self); 109 struct pci_attach_args *pa = aux; 110 struct ata_channel *chp = &sc->sc_channel; 111 struct wdc_regs *wdr; 112 pci_intr_handle_t ih; 113 paddr_t regbase, dmabase; 114 int node, reg[5], i; 115 116 #ifdef DIAGNOSTIC 117 if ((vaddr_t)sc->sc_dmacmd & 0x0f) { 118 aprint_error(": bad dbdma alignment\n"); 119 return; 120 } 121 #endif 122 123 node = getnodebypci(pa->pa_pc, pa->pa_tag); 124 if (node == 0) { 125 aprint_error(": cannot find kauai node\n"); 126 return; 127 } 128 129 if (OF_getprop(node, "assigned-addresses", reg, sizeof reg) < 12) { 130 aprint_error(": cannot get address property\n"); 131 return; 132 } 133 regbase = reg[2] + 0x2000; 134 dmabase = reg[2] + 0x1000; 135 136 /* 137 * XXX PCI_INTERRUPT_REG seems to be wired to 0. 138 * XXX So use fixed intrpin and intrline values. 139 */ 140 if (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_INTERRUPT_REG) == 0) { 141 pa->pa_intrpin = 1; 142 pa->pa_intrline = 39; 143 } 144 145 if (pci_intr_map(pa, &ih)) { 146 aprint_error(": unable to map interrupt\n"); 147 return; 148 } 149 aprint_normal(": interrupting at %s\n", pci_intr_string(pa->pa_pc, ih)); 150 151 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 152 153 wdr->cmd_iot = wdr->ctl_iot = pa->pa_memt; 154 155 if (bus_space_map(wdr->cmd_iot, regbase, WDC_REG_NPORTS << 4, 0, 156 &wdr->cmd_baseioh) || 157 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 158 WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) { 159 aprint_error_dev(self, "couldn't map registers\n"); 160 return; 161 } 162 for (i = 0; i < WDC_NREG; i++) { 163 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4, 164 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 165 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 166 WDC_REG_NPORTS << 4); 167 aprint_error_dev(self, 168 "couldn't subregion registers\n"); 169 return; 170 } 171 } 172 173 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, wdcintr, chp) == NULL) { 174 aprint_error_dev(self, "unable to establish interrupt\n"); 175 return; 176 } 177 178 179 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 180 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 181 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 182 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 183 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 184 sc->sc_chanptr = chp; 185 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 186 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 187 sc->sc_wdcdev.dma_arg = sc; 188 sc->sc_wdcdev.dma_init = kauai_dma_init; 189 sc->sc_wdcdev.dma_start = kauai_dma_start; 190 sc->sc_wdcdev.dma_finish = kauai_dma_finish; 191 sc->sc_wdcdev.sc_atac.atac_set_modes = kauai_set_modes; 192 sc->sc_calc_timing = calc_timing_kauai; 193 sc->sc_dmareg = (void *)dmabase; 194 195 chp->ch_channel = 0; 196 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 197 chp->ch_queue = &sc->sc_queue; 198 chp->ch_ndrive = 2; 199 wdc_init_shadow_regs(chp); 200 201 wdcattach(chp); 202 } 203 204 void 205 kauai_set_modes(struct ata_channel *chp) 206 { 207 struct kauai_softc *sc = (void *)chp->ch_atac; 208 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 209 struct ata_drive_datas *drvp0 = &chp->ch_drive[0]; 210 struct ata_drive_datas *drvp1 = &chp->ch_drive[1]; 211 struct ata_drive_datas *drvp; 212 int drive; 213 214 if ((drvp0->drive_flags & DRIVE) && (drvp1->drive_flags & DRIVE)) { 215 drvp0->PIO_mode = drvp1->PIO_mode = 216 min(drvp0->PIO_mode, drvp1->PIO_mode); 217 } 218 219 for (drive = 0; drive < 2; drive++) { 220 drvp = &chp->ch_drive[drive]; 221 if (drvp->drive_flags & DRIVE) { 222 (*sc->sc_calc_timing)(sc, drive); 223 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 224 PIO_CONFIG_REG, sc->sc_piotiming_r[drive]); 225 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 226 DMA_CONFIG_REG, sc->sc_dmatiming_r[drive]); 227 } 228 } 229 } 230 231 /* 232 * IDE transfer timings 233 */ 234 static const u_int pio_timing_kauai[] = { /* 0xff000fff */ 235 0x08000a92, /* Mode 0 */ 236 0x0800060f, /* 1 */ 237 0x0800038b, /* 2 */ 238 0x05000249, /* 3 */ 239 0x04000148 /* 4 */ 240 }; 241 static const u_int dma_timing_kauai[] = { /* 0x00fff000 */ 242 0x00618000, /* Mode 0 */ 243 0x00209000, /* 1 */ 244 0x00148000 /* 2 */ 245 }; 246 static const u_int udma_timing_kauai[] = { /* 0x0000ffff */ 247 0x000070c0, /* Mode 0 */ 248 0x00005d80, /* 1 */ 249 0x00004a60, /* 2 */ 250 0x00003a50, /* 3 */ 251 0x00002a30, /* 4 */ 252 0x00002921 /* 5 */ 253 }; 254 255 /* 256 * Timing calculation for Kauai. 257 */ 258 void 259 calc_timing_kauai(struct kauai_softc *sc, int drive) 260 { 261 struct ata_channel *chp = &sc->sc_channel; 262 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 263 int piomode = drvp->PIO_mode; 264 int dmamode = drvp->DMA_mode; 265 int udmamode = drvp->UDMA_mode; 266 u_int pioconf, dmaconf; 267 268 pioconf = pio_timing_kauai[piomode]; 269 270 dmaconf = 0; 271 if (drvp->drive_flags & DRIVE_DMA) 272 dmaconf |= dma_timing_kauai[dmamode]; 273 if (drvp->drive_flags & DRIVE_UDMA) 274 dmaconf |= udma_timing_kauai[udmamode]; 275 276 if (drvp->drive_flags & DRIVE_UDMA) 277 dmaconf |= 1; 278 279 sc->sc_piotiming_r[drive] = sc->sc_piotiming_w[drive] = pioconf; 280 sc->sc_dmatiming_r[drive] = sc->sc_dmatiming_w[drive] = dmaconf; 281 } 282 283 int 284 kauai_dma_init(void *v, int channel, int drive, void *databuf, 285 size_t datalen, int flags) 286 { 287 struct kauai_softc *sc = v; 288 dbdma_command_t *cmdp = sc->sc_dmacmd; 289 struct ata_channel *chp = &sc->sc_channel; 290 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 291 vaddr_t va = (vaddr_t)databuf; 292 int read = flags & WDC_DMA_READ; 293 int cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 294 u_int offset; 295 296 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG, 297 read ? sc->sc_dmatiming_r[drive] : sc->sc_dmatiming_w[drive]); 298 bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG); 299 300 offset = va & PGOFSET; 301 302 /* if va is not page-aligned, setup the first page */ 303 if (offset != 0) { 304 int rest = PAGE_SIZE - offset; /* the rest of the page */ 305 306 if (datalen > rest) { /* if continues to next page */ 307 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 308 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 309 DBDMA_BRANCH_NEVER); 310 datalen -= rest; 311 va += rest; 312 cmdp++; 313 } 314 } 315 316 /* now va is page-aligned */ 317 while (datalen > PAGE_SIZE) { 318 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 319 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 320 datalen -= PAGE_SIZE; 321 va += PAGE_SIZE; 322 cmdp++; 323 } 324 325 /* the last page (datalen <= PAGE_SIZE here) */ 326 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 327 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 328 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 329 cmdp++; 330 331 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 332 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 333 334 return 0; 335 } 336 337 void 338 kauai_dma_start(void *v, int channel, int drive) 339 { 340 struct kauai_softc *sc = v; 341 342 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 343 } 344 345 int 346 kauai_dma_finish(void *v, int channel, int drive, int read) 347 { 348 struct kauai_softc *sc = v; 349 350 dbdma_stop(sc->sc_dmareg); 351 return 0; 352 } 353 354 /* 355 * Find OF-device corresponding to the PCI device. 356 */ 357 int 358 getnodebypci(pci_chipset_tag_t pc, pcitag_t tag) 359 { 360 int bus, dev, func; 361 u_int reg[5]; 362 int p, q; 363 int l, b, d, f; 364 365 pci_decompose_tag(pc, tag, &bus, &dev, &func); 366 367 for (q = OF_peer(0); q; q = p) { 368 l = OF_getprop(q, "assigned-addresses", reg, sizeof(reg)); 369 if (l > 4) { 370 b = (reg[0] >> 16) & 0xff; 371 d = (reg[0] >> 11) & 0x1f; 372 f = (reg[0] >> 8) & 0x07; 373 374 if (b == bus && d == dev && f == func) 375 return q; 376 } 377 if ((p = OF_child(q))) 378 continue; 379 while (q) { 380 if ((p = OF_peer(q))) 381 break; 382 q = OF_parent(q); 383 } 384 } 385 return 0; 386 } 387
Indexes created Thu Oct 02 14:10:14 GMT 2025