kauai.c revision 1.24
1 /* $NetBSD: kauai.c,v 1.24 2008/05/25 16:00:11 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: kauai.c,v 1.24 2008/05/25 16:00:11 chs Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 37 #include <uvm/uvm_extern.h> 38 39 #include <machine/bus.h> 40 #include <machine/pio.h> 41 42 #include <dev/ata/atareg.h> 43 #include <dev/ata/atavar.h> 44 #include <dev/ic/wdcvar.h> 45 46 #include <dev/ofw/openfirm.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcidevs.h> 51 52 #include <macppc/dev/dbdma.h> 53 54 #define WDC_REG_NPORTS 8 55 #define WDC_AUXREG_OFFSET 0x16 56 #define WDC_AUXREG_NPORTS 1 57 58 #define PIO_CONFIG_REG (0x200 >> 4) /* PIO and DMA access timing */ 59 #define DMA_CONFIG_REG (0x210 >> 4) /* UDMA access timing */ 60 61 struct kauai_softc { 62 struct wdc_softc sc_wdcdev; 63 struct ata_channel *sc_chanptr; 64 struct ata_channel sc_channel; 65 struct wdc_regs sc_wdc_regs; 66 struct ata_queue sc_queue; 67 dbdma_regmap_t *sc_dmareg; 68 dbdma_command_t *sc_dmacmd; 69 u_int sc_piotiming_r[2]; 70 u_int sc_piotiming_w[2]; 71 u_int sc_dmatiming_r[2]; 72 u_int sc_dmatiming_w[2]; 73 void (*sc_calc_timing)(struct kauai_softc *, int); 74 }; 75 76 static int kauai_match(device_t, cfdata_t, void *); 77 static void kauai_attach(device_t, device_t, void *); 78 static int kauai_dma_init(void *, int, int, void *, size_t, int); 79 static void kauai_dma_start(void *, int, int); 80 static int kauai_dma_finish(void *, int, int, int); 81 static void kauai_set_modes(struct ata_channel *); 82 static void calc_timing_kauai(struct kauai_softc *, int); 83 static int getnodebypci(pci_chipset_tag_t, pcitag_t); 84 85 CFATTACH_DECL_NEW(kauai, sizeof(struct kauai_softc), 86 kauai_match, kauai_attach, NULL, wdcactivate); 87 88 int 89 kauai_match(device_t parent, cfdata_t match, void *aux) 90 { 91 struct pci_attach_args *pa = aux; 92 93 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE) { 94 switch (PCI_PRODUCT(pa->pa_id)) { 95 case PCI_PRODUCT_APPLE_KAUAI: 96 case PCI_PRODUCT_APPLE_UNINORTH_ATA: 97 case PCI_PRODUCT_APPLE_INTREPID2_ATA: 98 case PCI_PRODUCT_APPLE_SHASTA_ATA: 99 return 5; 100 } 101 } 102 103 return 0; 104 } 105 106 void 107 kauai_attach(device_t parent, device_t self, void *aux) 108 { 109 struct kauai_softc *sc = device_private(self); 110 struct pci_attach_args *pa = aux; 111 struct ata_channel *chp = &sc->sc_channel; 112 struct wdc_regs *wdr; 113 pci_intr_handle_t ih; 114 paddr_t regbase, dmabase; 115 int node, reg[5], i; 116 117 sc->sc_wdcdev.sc_atac.atac_dev = self; 118 119 #ifdef DIAGNOSTIC 120 if ((vaddr_t)sc->sc_dmacmd & 0x0f) { 121 aprint_error(": bad dbdma alignment\n"); 122 return; 123 } 124 #endif 125 126 node = getnodebypci(pa->pa_pc, pa->pa_tag); 127 if (node == 0) { 128 aprint_error(": cannot find kauai node\n"); 129 return; 130 } 131 132 if (OF_getprop(node, "assigned-addresses", reg, sizeof reg) < 12) { 133 aprint_error(": cannot get address property\n"); 134 return; 135 } 136 regbase = reg[2] + 0x2000; 137 dmabase = reg[2] + 0x1000; 138 139 /* 140 * XXX PCI_INTERRUPT_REG seems to be wired to 0. 141 * XXX So use fixed intrpin and intrline values. 142 */ 143 if (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_INTERRUPT_REG) == 0) { 144 pa->pa_intrpin = 1; 145 pa->pa_intrline = 39; 146 } 147 148 if (pci_intr_map(pa, &ih)) { 149 aprint_error(": unable to map interrupt\n"); 150 return; 151 } 152 aprint_normal(": interrupting at %s\n", pci_intr_string(pa->pa_pc, ih)); 153 154 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 155 156 wdr->cmd_iot = wdr->ctl_iot = pa->pa_memt; 157 158 if (bus_space_map(wdr->cmd_iot, regbase, WDC_REG_NPORTS << 4, 0, 159 &wdr->cmd_baseioh) || 160 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 161 WDC_AUXREG_OFFSET << 4, 1, &wdr->ctl_ioh)) { 162 aprint_error_dev(self, "couldn't map registers\n"); 163 return; 164 } 165 for (i = 0; i < WDC_NREG; i++) { 166 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i << 4, 167 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 168 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 169 WDC_REG_NPORTS << 4); 170 aprint_error_dev(self, 171 "couldn't subregion registers\n"); 172 return; 173 } 174 } 175 176 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, wdcintr, chp) == NULL) { 177 aprint_error_dev(self, "unable to establish interrupt\n"); 178 return; 179 } 180 181 182 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 183 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 184 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 185 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 186 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 187 sc->sc_chanptr = chp; 188 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 189 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 190 sc->sc_wdcdev.dma_arg = sc; 191 sc->sc_wdcdev.dma_init = kauai_dma_init; 192 sc->sc_wdcdev.dma_start = kauai_dma_start; 193 sc->sc_wdcdev.dma_finish = kauai_dma_finish; 194 sc->sc_wdcdev.sc_atac.atac_set_modes = kauai_set_modes; 195 sc->sc_calc_timing = calc_timing_kauai; 196 sc->sc_dmareg = (void *)dmabase; 197 198 chp->ch_channel = 0; 199 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 200 chp->ch_queue = &sc->sc_queue; 201 chp->ch_ndrive = 2; 202 wdc_init_shadow_regs(chp); 203 204 wdcattach(chp); 205 } 206 207 void 208 kauai_set_modes(struct ata_channel *chp) 209 { 210 struct kauai_softc *sc = (void *)chp->ch_atac; 211 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 212 struct ata_drive_datas *drvp0 = &chp->ch_drive[0]; 213 struct ata_drive_datas *drvp1 = &chp->ch_drive[1]; 214 struct ata_drive_datas *drvp; 215 int drive; 216 217 if ((drvp0->drive_flags & DRIVE) && (drvp1->drive_flags & DRIVE)) { 218 drvp0->PIO_mode = drvp1->PIO_mode = 219 min(drvp0->PIO_mode, drvp1->PIO_mode); 220 } 221 222 for (drive = 0; drive < 2; drive++) { 223 drvp = &chp->ch_drive[drive]; 224 if (drvp->drive_flags & DRIVE) { 225 (*sc->sc_calc_timing)(sc, drive); 226 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 227 PIO_CONFIG_REG, sc->sc_piotiming_r[drive]); 228 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 229 DMA_CONFIG_REG, sc->sc_dmatiming_r[drive]); 230 } 231 } 232 } 233 234 /* 235 * IDE transfer timings 236 */ 237 static const u_int pio_timing_kauai[] = { /* 0xff000fff */ 238 0x08000a92, /* Mode 0 */ 239 0x0800060f, /* 1 */ 240 0x0800038b, /* 2 */ 241 0x05000249, /* 3 */ 242 0x04000148 /* 4 */ 243 }; 244 static const u_int dma_timing_kauai[] = { /* 0x00fff000 */ 245 0x00618000, /* Mode 0 */ 246 0x00209000, /* 1 */ 247 0x00148000 /* 2 */ 248 }; 249 static const u_int udma_timing_kauai[] = { /* 0x0000ffff */ 250 0x000070c0, /* Mode 0 */ 251 0x00005d80, /* 1 */ 252 0x00004a60, /* 2 */ 253 0x00003a50, /* 3 */ 254 0x00002a30, /* 4 */ 255 0x00002921 /* 5 */ 256 }; 257 258 /* 259 * Timing calculation for Kauai. 260 */ 261 void 262 calc_timing_kauai(struct kauai_softc *sc, int drive) 263 { 264 struct ata_channel *chp = &sc->sc_channel; 265 struct ata_drive_datas *drvp = &chp->ch_drive[drive]; 266 int piomode = drvp->PIO_mode; 267 int dmamode = drvp->DMA_mode; 268 int udmamode = drvp->UDMA_mode; 269 u_int pioconf, dmaconf; 270 271 pioconf = pio_timing_kauai[piomode]; 272 273 dmaconf = 0; 274 if (drvp->drive_flags & DRIVE_DMA) 275 dmaconf |= dma_timing_kauai[dmamode]; 276 if (drvp->drive_flags & DRIVE_UDMA) 277 dmaconf |= udma_timing_kauai[udmamode]; 278 279 if (drvp->drive_flags & DRIVE_UDMA) 280 dmaconf |= 1; 281 282 sc->sc_piotiming_r[drive] = sc->sc_piotiming_w[drive] = pioconf; 283 sc->sc_dmatiming_r[drive] = sc->sc_dmatiming_w[drive] = dmaconf; 284 } 285 286 int 287 kauai_dma_init(void *v, int channel, int drive, void *databuf, 288 size_t datalen, int flags) 289 { 290 struct kauai_softc *sc = v; 291 dbdma_command_t *cmdp = sc->sc_dmacmd; 292 struct ata_channel *chp = &sc->sc_channel; 293 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 294 vaddr_t va = (vaddr_t)databuf; 295 int read = flags & WDC_DMA_READ; 296 int cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 297 u_int offset; 298 299 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG, 300 read ? sc->sc_dmatiming_r[drive] : sc->sc_dmatiming_w[drive]); 301 bus_space_read_4(wdr->cmd_iot, wdr->cmd_baseioh, DMA_CONFIG_REG); 302 303 offset = va & PGOFSET; 304 305 /* if va is not page-aligned, setup the first page */ 306 if (offset != 0) { 307 int rest = PAGE_SIZE - offset; /* the rest of the page */ 308 309 if (datalen > rest) { /* if continues to next page */ 310 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 311 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 312 DBDMA_BRANCH_NEVER); 313 datalen -= rest; 314 va += rest; 315 cmdp++; 316 } 317 } 318 319 /* now va is page-aligned */ 320 while (datalen > PAGE_SIZE) { 321 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 322 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 323 datalen -= PAGE_SIZE; 324 va += PAGE_SIZE; 325 cmdp++; 326 } 327 328 /* the last page (datalen <= PAGE_SIZE here) */ 329 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 330 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 331 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 332 cmdp++; 333 334 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 335 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 336 337 return 0; 338 } 339 340 void 341 kauai_dma_start(void *v, int channel, int drive) 342 { 343 struct kauai_softc *sc = v; 344 345 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 346 } 347 348 int 349 kauai_dma_finish(void *v, int channel, int drive, int read) 350 { 351 struct kauai_softc *sc = v; 352 353 dbdma_stop(sc->sc_dmareg); 354 return 0; 355 } 356 357 /* 358 * Find OF-device corresponding to the PCI device. 359 */ 360 int 361 getnodebypci(pci_chipset_tag_t pc, pcitag_t tag) 362 { 363 int bus, dev, func; 364 u_int reg[5]; 365 int p, q; 366 int l, b, d, f; 367 368 pci_decompose_tag(pc, tag, &bus, &dev, &func); 369 370 for (q = OF_peer(0); q; q = p) { 371 l = OF_getprop(q, "assigned-addresses", reg, sizeof(reg)); 372 if (l > 4) { 373 b = (reg[0] >> 16) & 0xff; 374 d = (reg[0] >> 11) & 0x1f; 375 f = (reg[0] >> 8) & 0x07; 376 377 if (b == bus && d == dev && f == func) 378 return q; 379 } 380 if ((p = OF_child(q))) 381 continue; 382 while (q) { 383 if ((p = OF_peer(q))) 384 break; 385 q = OF_parent(q); 386 } 387 } 388 return 0; 389 } 390
Indexes created Fri Oct 03 02:09:57 GMT 2025