wdc_obio.c revision 1.15
1 /* $NetBSD: wdc_obio.c,v 1.15 2001/07/25 20:26:33 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/autoconf.h> 48 49 #include <dev/ata/atareg.h> 50 #include <dev/ata/atavar.h> 51 #include <dev/ic/wdcvar.h> 52 53 #include <dev/ofw/openfirm.h> 54 55 #include <macppc/dev/dbdma.h> 56 57 #define WDC_REG_NPORTS 8 58 #define WDC_AUXREG_OFFSET 0x16 59 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 60 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 61 62 #define WDC_OPTIONS_DMA 0x01 63 64 /* 65 * XXX This code currently doesn't even try to allow 32-bit data port use. 66 */ 67 68 struct wdc_obio_softc { 69 struct wdc_softc sc_wdcdev; 70 struct channel_softc *wdc_chanptr; 71 struct channel_softc wdc_channel; 72 dbdma_regmap_t *sc_dmareg; 73 dbdma_command_t *sc_dmacmd; 74 void *sc_ih; 75 }; 76 77 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 78 void wdc_obio_attach __P((struct device *, struct device *, void *)); 79 int wdc_obio_detach __P((struct device *, int)); 80 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 81 void wdc_obio_dma_start __P((void *, int, int)); 82 int wdc_obio_dma_finish __P((void *, int, int, int)); 83 static void adjust_timing __P((struct channel_softc *)); 84 85 struct cfattach wdc_obio_ca = { 86 sizeof(struct wdc_obio_softc), wdc_obio_probe, wdc_obio_attach, 87 wdc_obio_detach, wdcactivate 88 }; 89 90 91 int 92 wdc_obio_probe(parent, match, aux) 93 struct device *parent; 94 struct cfdata *match; 95 void *aux; 96 { 97 struct confargs *ca = aux; 98 char compat[32]; 99 100 /* XXX should not use name */ 101 if (strcmp(ca->ca_name, "ATA") == 0 || 102 strcmp(ca->ca_name, "ata") == 0 || 103 strcmp(ca->ca_name, "ata0") == 0 || 104 strcmp(ca->ca_name, "ide") == 0) 105 return 1; 106 107 memset(compat, 0, sizeof(compat)); 108 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 109 if (strcmp(compat, "heathrow-ata") == 0 || 110 strcmp(compat, "keylargo-ata") == 0) 111 return 1; 112 113 return 0; 114 } 115 116 void 117 wdc_obio_attach(parent, self, aux) 118 struct device *parent, *self; 119 void *aux; 120 { 121 struct wdc_obio_softc *sc = (void *)self; 122 struct confargs *ca = aux; 123 struct channel_softc *chp = &sc->wdc_channel; 124 int intr; 125 int use_dma = 0; 126 char path[80]; 127 128 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { 129 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 130 use_dma = 1; /* XXX Don't work yet. */ 131 } 132 133 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 134 intr = ca->ca_intr[0]; 135 printf(" irq %d", intr); 136 } else if (ca->ca_nintr == -1) { 137 intr = WDC_DEFAULT_PIO_IRQ; 138 printf(" irq property not found; using %d", intr); 139 } else { 140 printf(": couldn't get irq property\n"); 141 return; 142 } 143 144 if (use_dma) 145 printf(": DMA transfer"); 146 147 printf("\n"); 148 149 chp->cmd_iot = chp->ctl_iot = 150 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 151 152 if (bus_space_map(chp->cmd_iot, 0, WDC_REG_NPORTS, 0, &chp->cmd_ioh) || 153 bus_space_subregion(chp->cmd_iot, chp->cmd_ioh, 154 WDC_AUXREG_OFFSET, 1, &chp->ctl_ioh)) { 155 printf("%s: couldn't map registers\n", 156 sc->sc_wdcdev.sc_dev.dv_xname); 157 return; 158 } 159 #if 0 160 chp->data32iot = chp->cmd_iot; 161 chp->data32ioh = chp->cmd_ioh; 162 #endif 163 164 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 165 166 if (use_dma) { 167 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 168 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 169 ca->ca_reg[3]); 170 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 171 sc->sc_wdcdev.DMA_cap = 2; 172 #ifdef notyet 173 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 174 if (ohare) { 175 sc->sc_wdcdev.PIO_cap = 3; 176 sc->sc_wdcdev.DMA_cap = 1; 177 } 178 #endif 179 } 180 sc->sc_wdcdev.PIO_cap = 4; 181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 182 sc->wdc_chanptr = chp; 183 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 184 sc->sc_wdcdev.nchannels = 1; 185 sc->sc_wdcdev.dma_arg = sc; 186 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 187 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 188 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 189 sc->sc_wdcdev.set_modes = adjust_timing; 190 chp->channel = 0; 191 chp->wdc = &sc->sc_wdcdev; 192 chp->ch_queue = malloc(sizeof(struct channel_queue), 193 M_DEVBUF, M_NOWAIT); 194 if (chp->ch_queue == NULL) { 195 printf("%s: can't allocate memory for command queue", 196 sc->sc_wdcdev.sc_dev.dv_xname); 197 return; 198 } 199 200 #define OHARE_FEATURE_REG 0xf3000038 201 202 /* XXX Enable wdc1 by feature reg. */ 203 memset(path, 0, sizeof(path)); 204 OF_package_to_path(ca->ca_node, path, sizeof(path)); 205 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 206 u_int x; 207 208 x = in32rb(OHARE_FEATURE_REG); 209 x |= 8; 210 out32rb(OHARE_FEATURE_REG, x); 211 } 212 213 wdcattach(chp); 214 215 /* modify DMA access timings */ 216 if (use_dma) 217 adjust_timing(chp); 218 219 } 220 221 /* Multiword DMA transfer timings */ 222 struct ide_timings { 223 int cycle; /* minimum cycle time [ns] */ 224 int active; /* minimum command active time [ns] */ 225 }; 226 static struct ide_timings pio_timing[5] = { 227 { 600, 165 }, /* Mode 0 */ 228 { 383, 125 }, /* 1 */ 229 { 240, 100 }, /* 2 */ 230 { 180, 80 }, /* 3 */ 231 { 120, 70 } /* 4 */ 232 }; 233 static struct ide_timings dma_timing[3] = { 234 { 480, 215 }, /* Mode 0 */ 235 { 150, 80 }, /* Mode 1 */ 236 { 120, 70 }, /* Mode 2 */ 237 }; 238 239 #define TIME_TO_TICK(time) howmany((time), 30) 240 241 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 242 243 void 244 adjust_timing(chp) 245 struct channel_softc *chp; 246 { 247 struct ata_drive_datas *drvp; 248 u_int conf; 249 int drive; 250 int piomode = -1, dmamode = -1; 251 int min_cycle, min_active; 252 int cycle_tick, act_tick, inact_tick, half_tick; 253 254 255 for (drive = 0; drive < 2; drive++) { 256 drvp = &chp->ch_drive[drive]; 257 if ((drvp->drive_flags & DRIVE) == 0) 258 continue; 259 if (piomode == -1 || piomode > drvp->PIO_mode) 260 piomode = drvp->PIO_mode; 261 if (drvp->drive_flags & DRIVE_DMA) { 262 if (dmamode == -1 || dmamode > drvp->DMA_mode) 263 dmamode = drvp->DMA_mode; 264 } 265 } 266 if (piomode == -1) 267 return; /* No drive */ 268 for (drive = 0; drive < 2; drive++) { 269 drvp = &chp->ch_drive[drive]; 270 if (drvp->drive_flags & DRIVE) { 271 drvp->PIO_mode = piomode; 272 if (drvp->drive_flags & DRIVE_DMA) 273 drvp->DMA_mode = dmamode; 274 } 275 } 276 min_cycle = pio_timing[piomode].cycle; 277 min_active = pio_timing[piomode].active; 278 279 cycle_tick = TIME_TO_TICK(min_cycle); 280 act_tick = TIME_TO_TICK(min_active); 281 inact_tick = cycle_tick - act_tick - 1; 282 if (inact_tick < 1) 283 inact_tick = 1; 284 conf = (inact_tick << 5) | act_tick; 285 if (dmamode != -1) { 286 /* there are active DMA mode */ 287 288 min_cycle = dma_timing[dmamode].cycle; 289 min_active = dma_timing[dmamode].active; 290 291 cycle_tick = TIME_TO_TICK(min_cycle); 292 act_tick = TIME_TO_TICK(min_active); 293 inact_tick = cycle_tick - act_tick - 1; 294 if (inact_tick < 1) 295 inact_tick = 1; 296 half_tick = 0; /* XXX */ 297 conf |= 298 (half_tick << 21) | (inact_tick << 16) | (act_tick << 11); 299 } 300 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, CONFIG_REG, conf); 301 #if 0 302 printf("conf = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 303 conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 304 #endif 305 wdc_print_modes(chp); 306 } 307 308 int 309 wdc_obio_detach(self, flags) 310 struct device *self; 311 int flags; 312 { 313 struct wdc_obio_softc *sc = (void *)self; 314 int error; 315 316 if ((error = wdcdetach(self, flags)) != 0) 317 return error; 318 319 intr_disestablish(sc->sc_ih); 320 321 free(sc->wdc_channel.ch_queue, M_DEVBUF); 322 323 /* Unmap our i/o space. */ 324 bus_space_unmap(chp->cmd_iot, chp->cmd_ioh, WDC_REG_NPORTS); 325 326 /* Unmap DMA registers. */ 327 /* XXX unmapiodev(sc->sc_dmareg); */ 328 /* XXX free(sc->sc_dmacmd); */ 329 330 return 0; 331 } 332 333 int 334 wdc_obio_dma_init(v, channel, drive, databuf, datalen, read) 335 void *v; 336 void *databuf; 337 size_t datalen; 338 int read; 339 { 340 struct wdc_obio_softc *sc = v; 341 vaddr_t va = (vaddr_t)databuf; 342 dbdma_command_t *cmdp; 343 u_int cmd, offset; 344 345 cmdp = sc->sc_dmacmd; 346 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 347 348 offset = va & PGOFSET; 349 350 /* if va is not page-aligned, setup the first page */ 351 if (offset != 0) { 352 int rest = NBPG - offset; /* the rest of the page */ 353 354 if (datalen > rest) { /* if continues to next page */ 355 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 356 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 357 DBDMA_BRANCH_NEVER); 358 datalen -= rest; 359 va += rest; 360 cmdp++; 361 } 362 } 363 364 /* now va is page-aligned */ 365 while (datalen > NBPG) { 366 DBDMA_BUILD(cmdp, cmd, 0, NBPG, vtophys(va), 367 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 368 datalen -= NBPG; 369 va += NBPG; 370 cmdp++; 371 } 372 373 /* the last page (datalen <= NBPG here) */ 374 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 375 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 376 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 377 cmdp++; 378 379 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 380 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 381 382 return 0; 383 } 384 385 void 386 wdc_obio_dma_start(v, channel, drive) 387 void *v; 388 int channel, drive; 389 { 390 struct wdc_obio_softc *sc = v; 391 392 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 393 } 394 395 int 396 wdc_obio_dma_finish(v, channel, drive, read) 397 void *v; 398 int channel, drive; 399 int read; 400 { 401 struct wdc_obio_softc *sc = v; 402 403 dbdma_stop(sc->sc_dmareg); 404 return 0; 405 } 406
Indexes created Mon Sep 29 21:09:56 GMT 2025