wdc_obio.c revision 1.16
1 /* $NetBSD: wdc_obio.c,v 1.16 2001/08/02 12:41:39 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/bus.h> 47 #include <machine/autoconf.h> 48 49 #include <dev/ata/atareg.h> 50 #include <dev/ata/atavar.h> 51 #include <dev/ic/wdcvar.h> 52 53 #include <dev/ofw/openfirm.h> 54 55 #include <macppc/dev/dbdma.h> 56 57 #define WDC_REG_NPORTS 8 58 #define WDC_AUXREG_OFFSET 0x16 59 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 60 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 61 62 #define WDC_OPTIONS_DMA 0x01 63 64 /* 65 * XXX This code currently doesn't even try to allow 32-bit data port use. 66 */ 67 68 struct wdc_obio_softc { 69 struct wdc_softc sc_wdcdev; 70 struct channel_softc *wdc_chanptr; 71 struct channel_softc wdc_channel; 72 dbdma_regmap_t *sc_dmareg; 73 dbdma_command_t *sc_dmacmd; 74 void *sc_ih; 75 }; 76 77 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 78 void wdc_obio_attach __P((struct device *, struct device *, void *)); 79 int wdc_obio_detach __P((struct device *, int)); 80 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 81 void wdc_obio_dma_start __P((void *, int, int)); 82 int wdc_obio_dma_finish __P((void *, int, int, int)); 83 static void adjust_timing __P((struct channel_softc *)); 84 static void ata4_adjust_timing __P((struct channel_softc *)); 85 86 struct cfattach wdc_obio_ca = { 87 sizeof(struct wdc_obio_softc), wdc_obio_probe, wdc_obio_attach, 88 wdc_obio_detach, wdcactivate 89 }; 90 91 92 int 93 wdc_obio_probe(parent, match, aux) 94 struct device *parent; 95 struct cfdata *match; 96 void *aux; 97 { 98 struct confargs *ca = aux; 99 char compat[32]; 100 101 /* XXX should not use name */ 102 if (strcmp(ca->ca_name, "ATA") == 0 || 103 strcmp(ca->ca_name, "ata") == 0 || 104 strcmp(ca->ca_name, "ata0") == 0 || 105 strcmp(ca->ca_name, "ide") == 0) 106 return 1; 107 108 memset(compat, 0, sizeof(compat)); 109 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 110 if (strcmp(compat, "heathrow-ata") == 0 || 111 strcmp(compat, "keylargo-ata") == 0) 112 return 1; 113 114 return 0; 115 } 116 117 void 118 wdc_obio_attach(parent, self, aux) 119 struct device *parent, *self; 120 void *aux; 121 { 122 struct wdc_obio_softc *sc = (void *)self; 123 struct confargs *ca = aux; 124 struct channel_softc *chp = &sc->wdc_channel; 125 int intr; 126 int use_dma = 0; 127 char path[80]; 128 129 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { 130 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 131 use_dma = 1; /* XXX Don't work yet. */ 132 } 133 134 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 135 intr = ca->ca_intr[0]; 136 printf(" irq %d", intr); 137 } else if (ca->ca_nintr == -1) { 138 intr = WDC_DEFAULT_PIO_IRQ; 139 printf(" irq property not found; using %d", intr); 140 } else { 141 printf(": couldn't get irq property\n"); 142 return; 143 } 144 145 if (use_dma) 146 printf(": DMA transfer"); 147 148 printf("\n"); 149 150 chp->cmd_iot = chp->ctl_iot = 151 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 152 153 if (bus_space_map(chp->cmd_iot, 0, WDC_REG_NPORTS, 0, &chp->cmd_ioh) || 154 bus_space_subregion(chp->cmd_iot, chp->cmd_ioh, 155 WDC_AUXREG_OFFSET, 1, &chp->ctl_ioh)) { 156 printf("%s: couldn't map registers\n", 157 sc->sc_wdcdev.sc_dev.dv_xname); 158 return; 159 } 160 #if 0 161 chp->data32iot = chp->cmd_iot; 162 chp->data32ioh = chp->cmd_ioh; 163 #endif 164 165 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 166 167 if (use_dma) { 168 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 169 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 170 ca->ca_reg[3]); 171 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 172 sc->sc_wdcdev.DMA_cap = 2; 173 if (strcmp(ca->ca_name, "ata-4") == 0) { 174 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 175 sc->sc_wdcdev.UDMA_cap = 4; 176 sc->sc_wdcdev.set_modes = ata4_adjust_timing; 177 } else { 178 sc->sc_wdcdev.set_modes = adjust_timing; 179 } 180 #ifdef notyet 181 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 182 if (ohare) { 183 sc->sc_wdcdev.PIO_cap = 3; 184 sc->sc_wdcdev.DMA_cap = 1; 185 } 186 #endif 187 } 188 sc->sc_wdcdev.PIO_cap = 4; 189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 190 sc->wdc_chanptr = chp; 191 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 192 sc->sc_wdcdev.nchannels = 1; 193 sc->sc_wdcdev.dma_arg = sc; 194 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 195 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 196 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 197 chp->channel = 0; 198 chp->wdc = &sc->sc_wdcdev; 199 chp->ch_queue = malloc(sizeof(struct channel_queue), 200 M_DEVBUF, M_NOWAIT); 201 if (chp->ch_queue == NULL) { 202 printf("%s: can't allocate memory for command queue", 203 sc->sc_wdcdev.sc_dev.dv_xname); 204 return; 205 } 206 207 #define OHARE_FEATURE_REG 0xf3000038 208 209 /* XXX Enable wdc1 by feature reg. */ 210 memset(path, 0, sizeof(path)); 211 OF_package_to_path(ca->ca_node, path, sizeof(path)); 212 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 213 u_int x; 214 215 x = in32rb(OHARE_FEATURE_REG); 216 x |= 8; 217 out32rb(OHARE_FEATURE_REG, x); 218 } 219 220 wdcattach(chp); 221 sc->sc_wdcdev.set_modes(chp); 222 223 } 224 225 /* Multiword DMA transfer timings */ 226 struct ide_timings { 227 int cycle; /* minimum cycle time [ns] */ 228 int active; /* minimum command active time [ns] */ 229 }; 230 static struct ide_timings pio_timing[5] = { 231 { 600, 165 }, /* Mode 0 */ 232 { 383, 125 }, /* 1 */ 233 { 240, 100 }, /* 2 */ 234 { 180, 80 }, /* 3 */ 235 { 120, 70 } /* 4 */ 236 }; 237 static struct ide_timings dma_timing[3] = { 238 { 480, 215 }, /* Mode 0 */ 239 { 150, 80 }, /* Mode 1 */ 240 { 120, 70 }, /* Mode 2 */ 241 }; 242 243 static struct ide_timings udma_timing[5] = { 244 {114, 0}, /* Mode 0 */ 245 { 75, 0}, /* Mode 1 */ 246 { 55, 0}, /* Mode 2 */ 247 { 45, 100}, /* Mode 3 */ 248 { 25, 100} /* Mode 4 */ 249 }; 250 251 #define TIME_TO_TICK(time) howmany((time), 30) 252 #define PIO_REC_OFFSET 4 253 #define PIO_REC_MIN 1 254 #define PIO_ACT_MIN 1 255 #define DMA_REC_OFFSET 1 256 #define DMA_REC_MIN 1 257 #define DMA_ACT_MIN 1 258 259 #define ATA4_TIME_TO_TICK(time) howmany((time) * 1000, 7500) 260 261 262 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 263 264 void 265 adjust_timing(chp) 266 struct channel_softc *chp; 267 { 268 struct ata_drive_datas *drvp; 269 u_int conf; 270 int drive; 271 int piomode = -1, dmamode = -1; 272 int min_cycle, min_active; 273 int cycle_tick, act_tick, inact_tick, half_tick; 274 275 276 for (drive = 0; drive < 2; drive++) { 277 drvp = &chp->ch_drive[drive]; 278 if ((drvp->drive_flags & DRIVE) == 0) 279 continue; 280 if (piomode == -1 || piomode > drvp->PIO_mode) 281 piomode = drvp->PIO_mode; 282 if (drvp->drive_flags & DRIVE_DMA) { 283 if (dmamode == -1 || dmamode > drvp->DMA_mode) 284 dmamode = drvp->DMA_mode; 285 } 286 } 287 if (piomode == -1) 288 return; /* No drive */ 289 for (drive = 0; drive < 2; drive++) { 290 drvp = &chp->ch_drive[drive]; 291 if (drvp->drive_flags & DRIVE) { 292 drvp->PIO_mode = piomode; 293 if (drvp->drive_flags & DRIVE_DMA) 294 drvp->DMA_mode = dmamode; 295 } 296 } 297 min_cycle = pio_timing[piomode].cycle; 298 min_active = pio_timing[piomode].active; 299 300 cycle_tick = TIME_TO_TICK(min_cycle); 301 act_tick = TIME_TO_TICK(min_active); 302 if (act_tick < PIO_ACT_MIN) 303 act_tick = PIO_ACT_MIN; 304 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 305 if (inact_tick < PIO_REC_MIN) 306 inact_tick = PIO_REC_MIN; 307 /* mask: 0x000007ff */ 308 conf = (inact_tick << 5) | act_tick; 309 if (dmamode != -1) { 310 /* there are active DMA mode */ 311 312 min_cycle = dma_timing[dmamode].cycle; 313 min_active = dma_timing[dmamode].active; 314 cycle_tick = TIME_TO_TICK(min_cycle); 315 act_tick = TIME_TO_TICK(min_active); 316 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 317 if (inact_tick < DMA_REC_MIN) 318 inact_tick = DMA_REC_MIN; 319 half_tick = 0; /* XXX */ 320 /* mask: 0xfffff800 */ 321 conf |= 322 (half_tick << 21) | 323 (inact_tick << 16) | (act_tick << 11); 324 } 325 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, CONFIG_REG, conf); 326 printf("conf = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 327 conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 328 wdc_print_modes(chp); 329 } 330 331 void 332 ata4_adjust_timing(chp) 333 struct channel_softc *chp; 334 { 335 struct ata_drive_datas *drvp; 336 u_int conf; 337 int drive; 338 int piomode = -1, dmamode = -1; 339 int min_cycle, min_active; 340 int cycle_tick, act_tick, inact_tick; 341 int udmamode = -1; 342 343 344 for (drive = 0; drive < 2; drive++) { 345 drvp = &chp->ch_drive[drive]; 346 if ((drvp->drive_flags & DRIVE) == 0) 347 continue; 348 if (piomode == -1 || piomode > drvp->PIO_mode) 349 piomode = drvp->PIO_mode; 350 if (drvp->drive_flags & DRIVE_DMA) { 351 if (dmamode == -1 || dmamode > drvp->DMA_mode) 352 dmamode = drvp->DMA_mode; 353 } 354 if (drvp->drive_flags & DRIVE_UDMA) { 355 if (udmamode == -1 || udmamode > drvp->UDMA_mode) 356 udmamode = drvp->UDMA_mode; 357 } 358 } 359 if (piomode == -1) 360 return; /* No drive */ 361 for (drive = 0; drive < 2; drive++) { 362 drvp = &chp->ch_drive[drive]; 363 if (drvp->drive_flags & DRIVE) { 364 drvp->PIO_mode = piomode; 365 if (drvp->drive_flags & DRIVE_DMA) 366 drvp->DMA_mode = dmamode; 367 if (drvp->drive_flags & DRIVE_UDMA) 368 drvp->UDMA_mode = udmamode; 369 } 370 } 371 min_cycle = pio_timing[piomode].cycle; 372 min_active = pio_timing[piomode].active; 373 374 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 375 act_tick = ATA4_TIME_TO_TICK(min_active); 376 inact_tick = cycle_tick - act_tick; 377 /* mask: 0x000003ff */ 378 conf = (inact_tick << 5) | act_tick; 379 if (dmamode != -1) { 380 /* there are active DMA mode */ 381 382 min_cycle = dma_timing[dmamode].cycle; 383 min_active = dma_timing[dmamode].active; 384 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 385 act_tick = ATA4_TIME_TO_TICK(min_active); 386 inact_tick = cycle_tick - act_tick; 387 /* mask: 0x001ffc00 */ 388 conf |= (act_tick << 10) | (inact_tick << 15); 389 } 390 if (udmamode != -1) { 391 min_cycle = udma_timing[udmamode].cycle; 392 min_active = udma_timing[udmamode].active; 393 act_tick = ATA4_TIME_TO_TICK(min_active); 394 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 395 /* mask: 0x1ff00000 */ 396 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 397 } 398 399 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, CONFIG_REG, conf); 400 printf("ata4 conf = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 401 conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 402 wdc_print_modes(chp); 403 } 404 405 int 406 wdc_obio_detach(self, flags) 407 struct device *self; 408 int flags; 409 { 410 struct wdc_obio_softc *sc = (void *)self; 411 int error; 412 413 if ((error = wdcdetach(self, flags)) != 0) 414 return error; 415 416 intr_disestablish(sc->sc_ih); 417 418 free(sc->wdc_channel.ch_queue, M_DEVBUF); 419 420 /* Unmap our i/o space. */ 421 bus_space_unmap(chp->cmd_iot, chp->cmd_ioh, WDC_REG_NPORTS); 422 423 /* Unmap DMA registers. */ 424 /* XXX unmapiodev(sc->sc_dmareg); */ 425 /* XXX free(sc->sc_dmacmd); */ 426 427 return 0; 428 } 429 430 int 431 wdc_obio_dma_init(v, channel, drive, databuf, datalen, read) 432 void *v; 433 void *databuf; 434 size_t datalen; 435 int read; 436 { 437 struct wdc_obio_softc *sc = v; 438 vaddr_t va = (vaddr_t)databuf; 439 dbdma_command_t *cmdp; 440 u_int cmd, offset; 441 442 cmdp = sc->sc_dmacmd; 443 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 444 445 offset = va & PGOFSET; 446 447 /* if va is not page-aligned, setup the first page */ 448 if (offset != 0) { 449 int rest = NBPG - offset; /* the rest of the page */ 450 451 if (datalen > rest) { /* if continues to next page */ 452 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 453 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 454 DBDMA_BRANCH_NEVER); 455 datalen -= rest; 456 va += rest; 457 cmdp++; 458 } 459 } 460 461 /* now va is page-aligned */ 462 while (datalen > NBPG) { 463 DBDMA_BUILD(cmdp, cmd, 0, NBPG, vtophys(va), 464 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 465 datalen -= NBPG; 466 va += NBPG; 467 cmdp++; 468 } 469 470 /* the last page (datalen <= NBPG here) */ 471 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 472 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 473 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 474 cmdp++; 475 476 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 477 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 478 479 return 0; 480 } 481 482 void 483 wdc_obio_dma_start(v, channel, drive) 484 void *v; 485 int channel, drive; 486 { 487 struct wdc_obio_softc *sc = v; 488 489 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 490 } 491 492 int 493 wdc_obio_dma_finish(v, channel, drive, read) 494 void *v; 495 int channel, drive; 496 int read; 497 { 498 struct wdc_obio_softc *sc = v; 499 500 dbdma_stop(sc->sc_dmareg); 501 return 0; 502 } 503
Indexes created Mon Sep 29 03:10:08 GMT 2025