wdc_obio.c revision 1.30
1 /* $NetBSD: wdc_obio.c,v 1.30 2003/12/03 12:09:32 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.30 2003/12/03 12:09:32 bouyer Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <dev/ata/atareg.h> 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 #include <macppc/dev/dbdma.h> 59 60 #define WDC_REG_NPORTS 8 61 #define WDC_AUXREG_OFFSET 0x16 62 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 63 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 64 65 #define WDC_OPTIONS_DMA 0x01 66 67 /* 68 * XXX This code currently doesn't even try to allow 32-bit data port use. 69 */ 70 71 struct wdc_obio_softc { 72 struct wdc_softc sc_wdcdev; 73 struct channel_softc *wdc_chanptr; 74 struct channel_softc wdc_channel; 75 dbdma_regmap_t *sc_dmareg; 76 dbdma_command_t *sc_dmacmd; 77 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 78 void *sc_ih; 79 }; 80 81 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 82 void wdc_obio_attach __P((struct device *, struct device *, void *)); 83 int wdc_obio_detach __P((struct device *, int)); 84 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 85 void wdc_obio_dma_start __P((void *, int, int)); 86 int wdc_obio_dma_finish __P((void *, int, int, int)); 87 88 static void wdc_obio_select __P((struct channel_softc *, int)); 89 static void adjust_timing __P((struct channel_softc *)); 90 static void ata4_adjust_timing __P((struct channel_softc *)); 91 92 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 93 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 94 95 int 96 wdc_obio_probe(parent, match, aux) 97 struct device *parent; 98 struct cfdata *match; 99 void *aux; 100 { 101 struct confargs *ca = aux; 102 char compat[32]; 103 104 /* XXX should not use name */ 105 if (strcmp(ca->ca_name, "ATA") == 0 || 106 strcmp(ca->ca_name, "ata") == 0 || 107 strcmp(ca->ca_name, "ata0") == 0 || 108 strcmp(ca->ca_name, "ide") == 0) 109 return 1; 110 111 memset(compat, 0, sizeof(compat)); 112 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 113 if (strcmp(compat, "heathrow-ata") == 0 || 114 strcmp(compat, "keylargo-ata") == 0) 115 return 1; 116 117 return 0; 118 } 119 120 void 121 wdc_obio_attach(parent, self, aux) 122 struct device *parent, *self; 123 void *aux; 124 { 125 struct wdc_obio_softc *sc = (void *)self; 126 struct confargs *ca = aux; 127 struct channel_softc *chp = &sc->wdc_channel; 128 int intr, i; 129 int use_dma = 0; 130 char path[80]; 131 132 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { 133 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 134 use_dma = 1; /* XXX Don't work yet. */ 135 } 136 137 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 138 intr = ca->ca_intr[0]; 139 printf(" irq %d", intr); 140 } else if (ca->ca_nintr == -1) { 141 intr = WDC_DEFAULT_PIO_IRQ; 142 printf(" irq property not found; using %d", intr); 143 } else { 144 printf(": couldn't get irq property\n"); 145 return; 146 } 147 148 if (use_dma) 149 printf(": DMA transfer"); 150 151 printf("\n"); 152 153 chp->cmd_iot = chp->ctl_iot = 154 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 155 156 if (bus_space_map(chp->cmd_iot, 0, WDC_REG_NPORTS, 0, 157 &chp->cmd_baseioh) || 158 bus_space_subregion(chp->cmd_iot, chp->cmd_baseioh, 159 WDC_AUXREG_OFFSET, 1, &chp->ctl_ioh)) { 160 printf("%s: couldn't map registers\n", 161 sc->sc_wdcdev.sc_dev.dv_xname); 162 return; 163 } 164 for (i = 0; i < WDC_NREG; i++) { 165 if (bus_space_subregion(chp->cmd_iot, chp->cmd_baseioh, i, 166 i == 0 ? 4 : 1, &chp->cmd_iohs[i]) != 0) { 167 bus_space_unmap(chp->cmd_iot, chp->cmd_baseioh, 168 WDC_REG_NPORTS); 169 printf("%s: couldn't subregion registers\n", 170 sc->sc_wdcdev.sc_dev.dv_xname); 171 return; 172 } 173 } 174 #if 0 175 chp->data32iot = chp->cmd_iot; 176 chp->data32ioh = chp->cmd_ioh; 177 #endif 178 179 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 180 181 if (use_dma) { 182 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 183 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 184 ca->ca_reg[3]); 185 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 186 sc->sc_wdcdev.DMA_cap = 2; 187 if (strcmp(ca->ca_name, "ata-4") == 0) { 188 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 189 sc->sc_wdcdev.UDMA_cap = 4; 190 sc->sc_wdcdev.set_modes = ata4_adjust_timing; 191 } else { 192 sc->sc_wdcdev.set_modes = adjust_timing; 193 } 194 #ifdef notyet 195 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 196 if (ohare) { 197 sc->sc_wdcdev.PIO_cap = 3; 198 sc->sc_wdcdev.DMA_cap = 1; 199 } 200 #endif 201 } else { 202 /* all non-DMA controllers can use adjust_timing */ 203 sc->sc_wdcdev.set_modes = adjust_timing; 204 } 205 206 sc->sc_wdcdev.PIO_cap = 4; 207 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 208 sc->wdc_chanptr = chp; 209 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 210 sc->sc_wdcdev.nchannels = 1; 211 sc->sc_wdcdev.dma_arg = sc; 212 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 213 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 214 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 215 chp->channel = 0; 216 chp->wdc = &sc->sc_wdcdev; 217 chp->ch_queue = malloc(sizeof(struct channel_queue), 218 M_DEVBUF, M_NOWAIT); 219 if (chp->ch_queue == NULL) { 220 printf("%s: can't allocate memory for command queue", 221 sc->sc_wdcdev.sc_dev.dv_xname); 222 return; 223 } 224 225 #define OHARE_FEATURE_REG 0xf3000038 226 227 /* XXX Enable wdc1 by feature reg. */ 228 memset(path, 0, sizeof(path)); 229 OF_package_to_path(ca->ca_node, path, sizeof(path)); 230 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 231 u_int x; 232 233 x = in32rb(OHARE_FEATURE_REG); 234 x |= 8; 235 out32rb(OHARE_FEATURE_REG, x); 236 } 237 238 wdcattach(chp); 239 } 240 241 /* Multiword DMA transfer timings */ 242 struct ide_timings { 243 int cycle; /* minimum cycle time [ns] */ 244 int active; /* minimum command active time [ns] */ 245 }; 246 static struct ide_timings pio_timing[5] = { 247 { 600, 180 }, /* Mode 0 */ 248 { 390, 150 }, /* 1 */ 249 { 240, 105 }, /* 2 */ 250 { 180, 90 }, /* 3 */ 251 { 120, 75 } /* 4 */ 252 }; 253 static struct ide_timings dma_timing[3] = { 254 { 480, 240 }, /* Mode 0 */ 255 { 165, 90 }, /* Mode 1 */ 256 { 120, 75 } /* Mode 2 */ 257 }; 258 259 static struct ide_timings udma_timing[5] = { 260 {120, 180}, /* Mode 0 */ 261 { 90, 150}, /* Mode 1 */ 262 { 60, 120}, /* Mode 2 */ 263 { 45, 90}, /* Mode 3 */ 264 { 30, 90} /* Mode 4 */ 265 }; 266 267 #define TIME_TO_TICK(time) howmany((time), 30) 268 #define PIO_REC_OFFSET 4 269 #define PIO_REC_MIN 1 270 #define PIO_ACT_MIN 1 271 #define DMA_REC_OFFSET 1 272 #define DMA_REC_MIN 1 273 #define DMA_ACT_MIN 1 274 275 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 276 277 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 278 279 void 280 wdc_obio_select(chp, drive) 281 struct channel_softc *chp; 282 int drive; 283 { 284 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 285 bus_space_write_4(chp->cmd_iot, chp->cmd_baseioh, 286 CONFIG_REG, sc->sc_dmaconf[drive]); 287 } 288 289 void 290 adjust_timing(chp) 291 struct channel_softc *chp; 292 { 293 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 294 int drive; 295 int min_cycle, min_active; 296 int cycle_tick, act_tick, inact_tick, half_tick; 297 298 for (drive = 0; drive < 2; drive++) { 299 u_int conf = 0; 300 struct ata_drive_datas *drvp; 301 302 drvp = &chp->ch_drive[drive]; 303 /* set up pio mode timings */ 304 if (drvp->drive_flags & DRIVE) { 305 int piomode = drvp->PIO_mode; 306 min_cycle = pio_timing[piomode].cycle; 307 min_active = pio_timing[piomode].active; 308 309 cycle_tick = TIME_TO_TICK(min_cycle); 310 act_tick = TIME_TO_TICK(min_active); 311 if (act_tick < PIO_ACT_MIN) 312 act_tick = PIO_ACT_MIN; 313 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 314 if (inact_tick < PIO_REC_MIN) 315 inact_tick = PIO_REC_MIN; 316 /* mask: 0x000007ff */ 317 conf |= (inact_tick << 5) | act_tick; 318 } 319 /* Set up DMA mode timings */ 320 if (drvp->drive_flags & DRIVE_DMA) { 321 int dmamode = drvp->DMA_mode; 322 min_cycle = dma_timing[dmamode].cycle; 323 min_active = dma_timing[dmamode].active; 324 cycle_tick = TIME_TO_TICK(min_cycle); 325 act_tick = TIME_TO_TICK(min_active); 326 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 327 if (inact_tick < DMA_REC_MIN) 328 inact_tick = DMA_REC_MIN; 329 half_tick = 0; /* XXX */ 330 /* mask: 0xfffff800 */ 331 conf |= 332 (half_tick << 21) | 333 (inact_tick << 16) | (act_tick << 11); 334 } 335 #ifdef DEBUG 336 if (conf) { 337 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 338 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 339 } 340 #endif 341 sc->sc_dmaconf[drive] = conf; 342 } 343 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_SELECT; 344 sc->sc_wdcdev.select = 0; 345 if (sc->sc_dmaconf[0]) { 346 wdc_obio_select(chp,0); 347 if (sc->sc_dmaconf[1] && (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 348 sc->sc_wdcdev.select = wdc_obio_select; 349 sc->sc_wdcdev.cap |= WDC_CAPABILITY_SELECT; 350 } 351 } else if (sc->sc_dmaconf[1]) { 352 wdc_obio_select(chp,1); 353 } 354 } 355 356 void 357 ata4_adjust_timing(chp) 358 struct channel_softc *chp; 359 { 360 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 361 int drive; 362 int min_cycle, min_active; 363 int cycle_tick, act_tick, inact_tick; 364 365 for (drive = 0; drive < 2; drive++) { 366 u_int conf = 0; 367 struct ata_drive_datas *drvp; 368 369 drvp = &chp->ch_drive[drive]; 370 /* set up pio mode timings */ 371 372 if (drvp->drive_flags & DRIVE) { 373 int piomode = drvp->PIO_mode; 374 min_cycle = pio_timing[piomode].cycle; 375 min_active = pio_timing[piomode].active; 376 377 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 378 act_tick = ATA4_TIME_TO_TICK(min_active); 379 inact_tick = cycle_tick - act_tick; 380 /* mask: 0x000003ff */ 381 conf |= (inact_tick << 5) | act_tick; 382 } 383 /* set up dma mode timings */ 384 if (drvp->drive_flags & DRIVE_DMA) { 385 int dmamode = drvp->DMA_mode; 386 min_cycle = dma_timing[dmamode].cycle; 387 min_active = dma_timing[dmamode].active; 388 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 389 act_tick = ATA4_TIME_TO_TICK(min_active); 390 inact_tick = cycle_tick - act_tick; 391 /* mask: 0x001ffc00 */ 392 conf |= (act_tick << 10) | (inact_tick << 15); 393 } 394 /* set up udma mode timings */ 395 if (drvp->drive_flags & DRIVE_UDMA) { 396 int udmamode = drvp->UDMA_mode; 397 min_cycle = udma_timing[udmamode].cycle; 398 min_active = udma_timing[udmamode].active; 399 act_tick = ATA4_TIME_TO_TICK(min_active); 400 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 401 /* mask: 0x1ff00000 */ 402 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 403 } 404 #ifdef DEBUG 405 if (conf) { 406 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 407 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 408 } 409 #endif 410 sc->sc_dmaconf[drive] = conf; 411 } 412 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_SELECT; 413 sc->sc_wdcdev.select = 0; 414 if (sc->sc_dmaconf[0]) { 415 wdc_obio_select(chp,0); 416 if (sc->sc_dmaconf[1] && (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 417 sc->sc_wdcdev.select = wdc_obio_select; 418 sc->sc_wdcdev.cap |= WDC_CAPABILITY_SELECT; 419 } 420 } else if (sc->sc_dmaconf[1]) { 421 wdc_obio_select(chp,1); 422 } 423 } 424 425 int 426 wdc_obio_detach(self, flags) 427 struct device *self; 428 int flags; 429 { 430 struct wdc_obio_softc *sc = (void *)self; 431 int error; 432 433 if ((error = wdcdetach(self, flags)) != 0) 434 return error; 435 436 intr_disestablish(sc->sc_ih); 437 438 free(sc->wdc_channel.ch_queue, M_DEVBUF); 439 440 /* Unmap our i/o space. */ 441 bus_space_unmap(chp->cmd_iot, chp->cmd_ioh, WDC_REG_NPORTS); 442 443 /* Unmap DMA registers. */ 444 /* XXX unmapiodev(sc->sc_dmareg); */ 445 /* XXX free(sc->sc_dmacmd); */ 446 447 return 0; 448 } 449 450 int 451 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 452 void *v; 453 void *databuf; 454 size_t datalen; 455 int flags; 456 { 457 struct wdc_obio_softc *sc = v; 458 vaddr_t va = (vaddr_t)databuf; 459 dbdma_command_t *cmdp; 460 u_int cmd, offset; 461 int read = flags & WDC_DMA_READ; 462 463 cmdp = sc->sc_dmacmd; 464 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 465 466 offset = va & PGOFSET; 467 468 /* if va is not page-aligned, setup the first page */ 469 if (offset != 0) { 470 int rest = PAGE_SIZE - offset; /* the rest of the page */ 471 472 if (datalen > rest) { /* if continues to next page */ 473 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 474 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 475 DBDMA_BRANCH_NEVER); 476 datalen -= rest; 477 va += rest; 478 cmdp++; 479 } 480 } 481 482 /* now va is page-aligned */ 483 while (datalen > PAGE_SIZE) { 484 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 485 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 486 datalen -= PAGE_SIZE; 487 va += PAGE_SIZE; 488 cmdp++; 489 } 490 491 /* the last page (datalen <= PAGE_SIZE here) */ 492 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 493 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 494 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 495 cmdp++; 496 497 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 498 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 499 500 return 0; 501 } 502 503 void 504 wdc_obio_dma_start(v, channel, drive) 505 void *v; 506 int channel, drive; 507 { 508 struct wdc_obio_softc *sc = v; 509 510 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 511 } 512 513 int 514 wdc_obio_dma_finish(v, channel, drive, read) 515 void *v; 516 int channel, drive; 517 int read; 518 { 519 struct wdc_obio_softc *sc = v; 520 521 dbdma_stop(sc->sc_dmareg); 522 return 0; 523 } 524
Indexes created Mon Sep 29 03:10:08 GMT 2025