wdc_obio.c revision 1.34
1 /* $NetBSD: wdc_obio.c,v 1.34 2004/01/03 01:50:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.34 2004/01/03 01:50:53 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <dev/ata/atareg.h> 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 #include <macppc/dev/dbdma.h> 59 60 #define WDC_REG_NPORTS 8 61 #define WDC_AUXREG_OFFSET 0x16 62 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 63 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 64 65 #define WDC_OPTIONS_DMA 0x01 66 67 /* 68 * XXX This code currently doesn't even try to allow 32-bit data port use. 69 */ 70 71 struct wdc_obio_softc { 72 struct wdc_softc sc_wdcdev; 73 struct wdc_channel wdc_chanptr[1]; 74 struct wdc_channel wdc_channel; 75 struct ata_queue wdc_chqueue; 76 dbdma_regmap_t *sc_dmareg; 77 dbdma_command_t *sc_dmacmd; 78 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 79 void *sc_ih; 80 }; 81 82 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 83 void wdc_obio_attach __P((struct device *, struct device *, void *)); 84 int wdc_obio_detach __P((struct device *, int)); 85 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 86 void wdc_obio_dma_start __P((void *, int, int)); 87 int wdc_obio_dma_finish __P((void *, int, int, int)); 88 89 static void wdc_obio_select __P((struct wdc_channel *, int)); 90 static void adjust_timing __P((struct wdc_channel *)); 91 static void ata4_adjust_timing __P((struct wdc_channel *)); 92 93 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 94 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 95 96 int 97 wdc_obio_probe(parent, match, aux) 98 struct device *parent; 99 struct cfdata *match; 100 void *aux; 101 { 102 struct confargs *ca = aux; 103 char compat[32]; 104 105 /* XXX should not use name */ 106 if (strcmp(ca->ca_name, "ATA") == 0 || 107 strcmp(ca->ca_name, "ata") == 0 || 108 strcmp(ca->ca_name, "ata0") == 0 || 109 strcmp(ca->ca_name, "ide") == 0) 110 return 1; 111 112 memset(compat, 0, sizeof(compat)); 113 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 114 if (strcmp(compat, "heathrow-ata") == 0 || 115 strcmp(compat, "keylargo-ata") == 0) 116 return 1; 117 118 return 0; 119 } 120 121 void 122 wdc_obio_attach(parent, self, aux) 123 struct device *parent, *self; 124 void *aux; 125 { 126 struct wdc_obio_softc *sc = (void *)self; 127 struct confargs *ca = aux; 128 struct wdc_channel *chp = &sc->wdc_channel; 129 int intr, i; 130 int use_dma = 0; 131 char path[80]; 132 133 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { 134 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 135 use_dma = 1; /* XXX Don't work yet. */ 136 } 137 138 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 139 intr = ca->ca_intr[0]; 140 printf(" irq %d", intr); 141 } else if (ca->ca_nintr == -1) { 142 intr = WDC_DEFAULT_PIO_IRQ; 143 printf(" irq property not found; using %d", intr); 144 } else { 145 printf(": couldn't get irq property\n"); 146 return; 147 } 148 149 if (use_dma) 150 printf(": DMA transfer"); 151 152 printf("\n"); 153 154 chp->cmd_iot = chp->ctl_iot = 155 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 156 157 if (bus_space_map(chp->cmd_iot, 0, WDC_REG_NPORTS, 0, 158 &chp->cmd_baseioh) || 159 bus_space_subregion(chp->cmd_iot, chp->cmd_baseioh, 160 WDC_AUXREG_OFFSET, 1, &chp->ctl_ioh)) { 161 printf("%s: couldn't map registers\n", 162 sc->sc_wdcdev.sc_dev.dv_xname); 163 return; 164 } 165 for (i = 0; i < WDC_NREG; i++) { 166 if (bus_space_subregion(chp->cmd_iot, chp->cmd_baseioh, i, 167 i == 0 ? 4 : 1, &chp->cmd_iohs[i]) != 0) { 168 bus_space_unmap(chp->cmd_iot, chp->cmd_baseioh, 169 WDC_REG_NPORTS); 170 printf("%s: couldn't subregion registers\n", 171 sc->sc_wdcdev.sc_dev.dv_xname); 172 return; 173 } 174 } 175 #if 0 176 chp->data32iot = chp->cmd_iot; 177 chp->data32ioh = chp->cmd_ioh; 178 #endif 179 180 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 181 182 if (use_dma) { 183 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 184 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 185 ca->ca_reg[3]); 186 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 187 sc->sc_wdcdev.DMA_cap = 2; 188 if (strcmp(ca->ca_name, "ata-4") == 0) { 189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 190 sc->sc_wdcdev.UDMA_cap = 4; 191 sc->sc_wdcdev.set_modes = ata4_adjust_timing; 192 } else { 193 sc->sc_wdcdev.set_modes = adjust_timing; 194 } 195 #ifdef notyet 196 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 197 if (ohare) { 198 sc->sc_wdcdev.PIO_cap = 3; 199 sc->sc_wdcdev.DMA_cap = 1; 200 } 201 #endif 202 } else { 203 /* all non-DMA controllers can use adjust_timing */ 204 sc->sc_wdcdev.set_modes = adjust_timing; 205 } 206 207 sc->sc_wdcdev.PIO_cap = 4; 208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 209 sc->wdc_chanlist[0] = chp; 210 sc->sc_wdcdev.channels = sc->wdc_chanlist; 211 sc->sc_wdcdev.nchannels = 1; 212 sc->sc_wdcdev.dma_arg = sc; 213 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 214 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 215 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 216 chp->channel = 0; 217 chp->wdc = &sc->sc_wdcdev; 218 chp->ch_queue = &sc->wdc_chqueue; 219 220 #define OHARE_FEATURE_REG 0xf3000038 221 222 /* XXX Enable wdc1 by feature reg. */ 223 memset(path, 0, sizeof(path)); 224 OF_package_to_path(ca->ca_node, path, sizeof(path)); 225 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 226 u_int x; 227 228 x = in32rb(OHARE_FEATURE_REG); 229 x |= 8; 230 out32rb(OHARE_FEATURE_REG, x); 231 } 232 233 wdcattach(chp); 234 } 235 236 /* Multiword DMA transfer timings */ 237 struct ide_timings { 238 int cycle; /* minimum cycle time [ns] */ 239 int active; /* minimum command active time [ns] */ 240 }; 241 static struct ide_timings pio_timing[5] = { 242 { 600, 180 }, /* Mode 0 */ 243 { 390, 150 }, /* 1 */ 244 { 240, 105 }, /* 2 */ 245 { 180, 90 }, /* 3 */ 246 { 120, 75 } /* 4 */ 247 }; 248 static struct ide_timings dma_timing[3] = { 249 { 480, 240 }, /* Mode 0 */ 250 { 165, 90 }, /* Mode 1 */ 251 { 120, 75 } /* Mode 2 */ 252 }; 253 254 static struct ide_timings udma_timing[5] = { 255 {120, 180}, /* Mode 0 */ 256 { 90, 150}, /* Mode 1 */ 257 { 60, 120}, /* Mode 2 */ 258 { 45, 90}, /* Mode 3 */ 259 { 30, 90} /* Mode 4 */ 260 }; 261 262 #define TIME_TO_TICK(time) howmany((time), 30) 263 #define PIO_REC_OFFSET 4 264 #define PIO_REC_MIN 1 265 #define PIO_ACT_MIN 1 266 #define DMA_REC_OFFSET 1 267 #define DMA_REC_MIN 1 268 #define DMA_ACT_MIN 1 269 270 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 271 272 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 273 274 void 275 wdc_obio_select(chp, drive) 276 struct wdc_channel *chp; 277 int drive; 278 { 279 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 280 bus_space_write_4(chp->cmd_iot, chp->cmd_baseioh, 281 CONFIG_REG, sc->sc_dmaconf[drive]); 282 } 283 284 void 285 adjust_timing(chp) 286 struct wdc_channel *chp; 287 { 288 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 289 int drive; 290 int min_cycle = 0, min_active = 0; 291 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 292 293 for (drive = 0; drive < 2; drive++) { 294 u_int conf = 0; 295 struct ata_drive_datas *drvp; 296 297 drvp = &chp->ch_drive[drive]; 298 /* set up pio mode timings */ 299 if (drvp->drive_flags & DRIVE) { 300 int piomode = drvp->PIO_mode; 301 min_cycle = pio_timing[piomode].cycle; 302 min_active = pio_timing[piomode].active; 303 304 cycle_tick = TIME_TO_TICK(min_cycle); 305 act_tick = TIME_TO_TICK(min_active); 306 if (act_tick < PIO_ACT_MIN) 307 act_tick = PIO_ACT_MIN; 308 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 309 if (inact_tick < PIO_REC_MIN) 310 inact_tick = PIO_REC_MIN; 311 /* mask: 0x000007ff */ 312 conf |= (inact_tick << 5) | act_tick; 313 } 314 /* Set up DMA mode timings */ 315 if (drvp->drive_flags & DRIVE_DMA) { 316 int dmamode = drvp->DMA_mode; 317 min_cycle = dma_timing[dmamode].cycle; 318 min_active = dma_timing[dmamode].active; 319 cycle_tick = TIME_TO_TICK(min_cycle); 320 act_tick = TIME_TO_TICK(min_active); 321 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 322 if (inact_tick < DMA_REC_MIN) 323 inact_tick = DMA_REC_MIN; 324 half_tick = 0; /* XXX */ 325 /* mask: 0xfffff800 */ 326 conf |= 327 (half_tick << 21) | 328 (inact_tick << 16) | (act_tick << 11); 329 } 330 #ifdef DEBUG 331 if (conf) { 332 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 333 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 334 } 335 #endif 336 sc->sc_dmaconf[drive] = conf; 337 } 338 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_SELECT; 339 sc->sc_wdcdev.select = 0; 340 if (sc->sc_dmaconf[0]) { 341 wdc_obio_select(chp,0); 342 if (sc->sc_dmaconf[1] && (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 343 sc->sc_wdcdev.select = wdc_obio_select; 344 sc->sc_wdcdev.cap |= WDC_CAPABILITY_SELECT; 345 } 346 } else if (sc->sc_dmaconf[1]) { 347 wdc_obio_select(chp,1); 348 } 349 } 350 351 void 352 ata4_adjust_timing(chp) 353 struct wdc_channel *chp; 354 { 355 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->wdc; 356 int drive; 357 int min_cycle = 0, min_active = 0; 358 int cycle_tick = 0, act_tick = 0, inact_tick = 0; 359 360 for (drive = 0; drive < 2; drive++) { 361 u_int conf = 0; 362 struct ata_drive_datas *drvp; 363 364 drvp = &chp->ch_drive[drive]; 365 /* set up pio mode timings */ 366 367 if (drvp->drive_flags & DRIVE) { 368 int piomode = drvp->PIO_mode; 369 min_cycle = pio_timing[piomode].cycle; 370 min_active = pio_timing[piomode].active; 371 372 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 373 act_tick = ATA4_TIME_TO_TICK(min_active); 374 inact_tick = cycle_tick - act_tick; 375 /* mask: 0x000003ff */ 376 conf |= (inact_tick << 5) | act_tick; 377 } 378 /* set up dma mode timings */ 379 if (drvp->drive_flags & DRIVE_DMA) { 380 int dmamode = drvp->DMA_mode; 381 min_cycle = dma_timing[dmamode].cycle; 382 min_active = dma_timing[dmamode].active; 383 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 384 act_tick = ATA4_TIME_TO_TICK(min_active); 385 inact_tick = cycle_tick - act_tick; 386 /* mask: 0x001ffc00 */ 387 conf |= (act_tick << 10) | (inact_tick << 15); 388 } 389 /* set up udma mode timings */ 390 if (drvp->drive_flags & DRIVE_UDMA) { 391 int udmamode = drvp->UDMA_mode; 392 min_cycle = udma_timing[udmamode].cycle; 393 min_active = udma_timing[udmamode].active; 394 act_tick = ATA4_TIME_TO_TICK(min_active); 395 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 396 /* mask: 0x1ff00000 */ 397 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 398 } 399 #ifdef DEBUG 400 if (conf) { 401 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 402 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 403 } 404 #endif 405 sc->sc_dmaconf[drive] = conf; 406 } 407 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_SELECT; 408 sc->sc_wdcdev.select = 0; 409 if (sc->sc_dmaconf[0]) { 410 wdc_obio_select(chp,0); 411 if (sc->sc_dmaconf[1] && (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 412 sc->sc_wdcdev.select = wdc_obio_select; 413 sc->sc_wdcdev.cap |= WDC_CAPABILITY_SELECT; 414 } 415 } else if (sc->sc_dmaconf[1]) { 416 wdc_obio_select(chp,1); 417 } 418 } 419 420 int 421 wdc_obio_detach(self, flags) 422 struct device *self; 423 int flags; 424 { 425 struct wdc_obio_softc *sc = (void *)self; 426 int error; 427 428 if ((error = wdcdetach(self, flags)) != 0) 429 return error; 430 431 intr_disestablish(sc->sc_ih); 432 433 /* Unmap our i/o space. */ 434 bus_space_unmap(chp->cmd_iot, chp->cmd_ioh, WDC_REG_NPORTS); 435 436 /* Unmap DMA registers. */ 437 /* XXX unmapiodev(sc->sc_dmareg); */ 438 /* XXX free(sc->sc_dmacmd); */ 439 440 return 0; 441 } 442 443 int 444 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 445 void *v; 446 void *databuf; 447 size_t datalen; 448 int flags; 449 { 450 struct wdc_obio_softc *sc = v; 451 vaddr_t va = (vaddr_t)databuf; 452 dbdma_command_t *cmdp; 453 u_int cmd, offset; 454 int read = flags & WDC_DMA_READ; 455 456 cmdp = sc->sc_dmacmd; 457 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 458 459 offset = va & PGOFSET; 460 461 /* if va is not page-aligned, setup the first page */ 462 if (offset != 0) { 463 int rest = PAGE_SIZE - offset; /* the rest of the page */ 464 465 if (datalen > rest) { /* if continues to next page */ 466 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 467 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 468 DBDMA_BRANCH_NEVER); 469 datalen -= rest; 470 va += rest; 471 cmdp++; 472 } 473 } 474 475 /* now va is page-aligned */ 476 while (datalen > PAGE_SIZE) { 477 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 478 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 479 datalen -= PAGE_SIZE; 480 va += PAGE_SIZE; 481 cmdp++; 482 } 483 484 /* the last page (datalen <= PAGE_SIZE here) */ 485 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 486 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 487 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 488 cmdp++; 489 490 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 491 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 492 493 return 0; 494 } 495 496 void 497 wdc_obio_dma_start(v, channel, drive) 498 void *v; 499 int channel, drive; 500 { 501 struct wdc_obio_softc *sc = v; 502 503 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 504 } 505 506 int 507 wdc_obio_dma_finish(v, channel, drive, read) 508 void *v; 509 int channel, drive; 510 int read; 511 { 512 struct wdc_obio_softc *sc = v; 513 514 dbdma_stop(sc->sc_dmareg); 515 return 0; 516 } 517
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