wdc_obio.c revision 1.44
1 /* $NetBSD: wdc_obio.c,v 1.44 2006/03/29 04:16:45 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.44 2006/03/29 04:16:45 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <dev/ata/atareg.h> 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 #include <macppc/dev/dbdma.h> 59 60 #define WDC_REG_NPORTS 8 61 #define WDC_AUXREG_OFFSET 0x16 62 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 63 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 64 65 #define WDC_OPTIONS_DMA 0x01 66 67 /* 68 * XXX This code currently doesn't even try to allow 32-bit data port use. 69 */ 70 71 struct wdc_obio_softc { 72 struct wdc_softc sc_wdcdev; 73 struct ata_channel *sc_chanptr; 74 struct ata_channel sc_channel; 75 struct ata_queue sc_chqueue; 76 struct wdc_regs sc_wdc_regs; 77 dbdma_regmap_t *sc_dmareg; 78 dbdma_command_t *sc_dmacmd; 79 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 80 void *sc_ih; 81 }; 82 83 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 84 void wdc_obio_attach __P((struct device *, struct device *, void *)); 85 int wdc_obio_detach __P((struct device *, int)); 86 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 87 void wdc_obio_dma_start __P((void *, int, int)); 88 int wdc_obio_dma_finish __P((void *, int, int, int)); 89 90 static void wdc_obio_select __P((struct ata_channel *, int)); 91 static void adjust_timing __P((struct ata_channel *)); 92 static void ata4_adjust_timing __P((struct ata_channel *)); 93 94 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 95 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 96 97 int 98 wdc_obio_probe(parent, match, aux) 99 struct device *parent; 100 struct cfdata *match; 101 void *aux; 102 { 103 struct confargs *ca = aux; 104 char compat[32]; 105 106 /* XXX should not use name */ 107 if (strcmp(ca->ca_name, "ATA") == 0 || 108 strcmp(ca->ca_name, "ata") == 0 || 109 strcmp(ca->ca_name, "ata0") == 0 || 110 strcmp(ca->ca_name, "ide") == 0) 111 return 1; 112 113 memset(compat, 0, sizeof(compat)); 114 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 115 if (strcmp(compat, "heathrow-ata") == 0 || 116 strcmp(compat, "keylargo-ata") == 0) 117 return 1; 118 119 return 0; 120 } 121 122 void 123 wdc_obio_attach(parent, self, aux) 124 struct device *parent, *self; 125 void *aux; 126 { 127 struct wdc_obio_softc *sc = (void *)self; 128 struct wdc_regs *wdr; 129 struct confargs *ca = aux; 130 struct ata_channel *chp = &sc->sc_channel; 131 int intr, i; 132 int use_dma = 0; 133 char path[80]; 134 135 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 136 WDC_OPTIONS_DMA) { 137 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 138 use_dma = 1; /* XXX Don't work yet. */ 139 } 140 141 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 142 intr = ca->ca_intr[0]; 143 printf(" irq %d", intr); 144 } else if (ca->ca_nintr == -1) { 145 intr = WDC_DEFAULT_PIO_IRQ; 146 printf(" irq property not found; using %d", intr); 147 } else { 148 printf(": couldn't get irq property\n"); 149 return; 150 } 151 152 if (use_dma) 153 printf(": DMA transfer"); 154 155 printf("\n"); 156 157 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 158 159 wdr->cmd_iot = wdr->ctl_iot = 160 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 161 162 if (bus_space_map(wdr->cmd_iot, 0, WDC_REG_NPORTS, 0, 163 &wdr->cmd_baseioh) || 164 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 165 WDC_AUXREG_OFFSET, 1, &wdr->ctl_ioh)) { 166 printf("%s: couldn't map registers\n", 167 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 168 return; 169 } 170 for (i = 0; i < WDC_NREG; i++) { 171 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 172 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 173 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 174 WDC_REG_NPORTS); 175 printf("%s: couldn't subregion registers\n", 176 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 177 return; 178 } 179 } 180 #if 0 181 wdr->data32iot = wdr->cmd_iot; 182 wdr->data32ioh = wdr->cmd_ioh; 183 #endif 184 185 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 186 187 if (use_dma) { 188 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 189 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 190 ca->ca_reg[3]); 191 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 192 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 193 if (strcmp(ca->ca_name, "ata-4") == 0) { 194 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 195 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 196 sc->sc_wdcdev.sc_atac.atac_set_modes = ata4_adjust_timing; 197 } else { 198 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 199 } 200 #ifdef notyet 201 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 202 if (ohare) { 203 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3; 204 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1; 205 } 206 #endif 207 } else { 208 /* all non-DMA controllers can use adjust_timing */ 209 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 210 } 211 212 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 213 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 214 sc->sc_chanptr = chp; 215 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 216 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 217 sc->sc_wdcdev.dma_arg = sc; 218 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 219 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 220 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 221 chp->ch_channel = 0; 222 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 223 chp->ch_queue = &sc->sc_chqueue; 224 chp->ch_ndrive = 2; 225 226 wdc_init_shadow_regs(chp); 227 228 #define OHARE_FEATURE_REG 0xf3000038 229 230 /* XXX Enable wdc1 by feature reg. */ 231 memset(path, 0, sizeof(path)); 232 OF_package_to_path(ca->ca_node, path, sizeof(path)); 233 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 234 u_int x; 235 236 x = in32rb(OHARE_FEATURE_REG); 237 x |= 8; 238 out32rb(OHARE_FEATURE_REG, x); 239 } 240 241 wdcattach(chp); 242 } 243 244 /* Multiword DMA transfer timings */ 245 struct ide_timings { 246 int cycle; /* minimum cycle time [ns] */ 247 int active; /* minimum command active time [ns] */ 248 }; 249 static struct ide_timings pio_timing[5] = { 250 { 600, 180 }, /* Mode 0 */ 251 { 390, 150 }, /* 1 */ 252 { 240, 105 }, /* 2 */ 253 { 180, 90 }, /* 3 */ 254 { 120, 75 } /* 4 */ 255 }; 256 static struct ide_timings dma_timing[3] = { 257 { 480, 240 }, /* Mode 0 */ 258 { 165, 90 }, /* Mode 1 */ 259 { 120, 75 } /* Mode 2 */ 260 }; 261 262 static struct ide_timings udma_timing[5] = { 263 {120, 180}, /* Mode 0 */ 264 { 90, 150}, /* Mode 1 */ 265 { 60, 120}, /* Mode 2 */ 266 { 45, 90}, /* Mode 3 */ 267 { 30, 90} /* Mode 4 */ 268 }; 269 270 #define TIME_TO_TICK(time) howmany((time), 30) 271 #define PIO_REC_OFFSET 4 272 #define PIO_REC_MIN 1 273 #define PIO_ACT_MIN 1 274 #define DMA_REC_OFFSET 1 275 #define DMA_REC_MIN 1 276 #define DMA_ACT_MIN 1 277 278 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 279 280 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 281 282 void 283 wdc_obio_select(chp, drive) 284 struct ata_channel *chp; 285 int drive; 286 { 287 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 288 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 289 290 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 291 CONFIG_REG, sc->sc_dmaconf[drive]); 292 } 293 294 void 295 adjust_timing(chp) 296 struct ata_channel *chp; 297 { 298 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 299 int drive; 300 int min_cycle = 0, min_active = 0; 301 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 302 303 for (drive = 0; drive < 2; drive++) { 304 u_int conf = 0; 305 struct ata_drive_datas *drvp; 306 307 drvp = &chp->ch_drive[drive]; 308 /* set up pio mode timings */ 309 if (drvp->drive_flags & DRIVE) { 310 int piomode = drvp->PIO_mode; 311 min_cycle = pio_timing[piomode].cycle; 312 min_active = pio_timing[piomode].active; 313 314 cycle_tick = TIME_TO_TICK(min_cycle); 315 act_tick = TIME_TO_TICK(min_active); 316 if (act_tick < PIO_ACT_MIN) 317 act_tick = PIO_ACT_MIN; 318 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 319 if (inact_tick < PIO_REC_MIN) 320 inact_tick = PIO_REC_MIN; 321 /* mask: 0x000007ff */ 322 conf |= (inact_tick << 5) | act_tick; 323 } 324 /* Set up DMA mode timings */ 325 if (drvp->drive_flags & DRIVE_DMA) { 326 int dmamode = drvp->DMA_mode; 327 min_cycle = dma_timing[dmamode].cycle; 328 min_active = dma_timing[dmamode].active; 329 cycle_tick = TIME_TO_TICK(min_cycle); 330 act_tick = TIME_TO_TICK(min_active); 331 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 332 if (inact_tick < DMA_REC_MIN) 333 inact_tick = DMA_REC_MIN; 334 half_tick = 0; /* XXX */ 335 /* mask: 0xfffff800 */ 336 conf |= 337 (half_tick << 21) | 338 (inact_tick << 16) | (act_tick << 11); 339 } 340 #ifdef DEBUG 341 if (conf) { 342 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 343 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 344 } 345 #endif 346 sc->sc_dmaconf[drive] = conf; 347 } 348 sc->sc_wdcdev.select = 0; 349 if (sc->sc_dmaconf[0]) { 350 wdc_obio_select(chp,0); 351 if (sc->sc_dmaconf[1] && 352 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 353 sc->sc_wdcdev.select = wdc_obio_select; 354 } 355 } else if (sc->sc_dmaconf[1]) { 356 wdc_obio_select(chp,1); 357 } 358 } 359 360 void 361 ata4_adjust_timing(chp) 362 struct ata_channel *chp; 363 { 364 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 365 int drive; 366 int min_cycle = 0, min_active = 0; 367 int cycle_tick = 0, act_tick = 0, inact_tick = 0; 368 369 for (drive = 0; drive < 2; drive++) { 370 u_int conf = 0; 371 struct ata_drive_datas *drvp; 372 373 drvp = &chp->ch_drive[drive]; 374 /* set up pio mode timings */ 375 376 if (drvp->drive_flags & DRIVE) { 377 int piomode = drvp->PIO_mode; 378 min_cycle = pio_timing[piomode].cycle; 379 min_active = pio_timing[piomode].active; 380 381 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 382 act_tick = ATA4_TIME_TO_TICK(min_active); 383 inact_tick = cycle_tick - act_tick; 384 /* mask: 0x000003ff */ 385 conf |= (inact_tick << 5) | act_tick; 386 } 387 /* set up dma mode timings */ 388 if (drvp->drive_flags & DRIVE_DMA) { 389 int dmamode = drvp->DMA_mode; 390 min_cycle = dma_timing[dmamode].cycle; 391 min_active = dma_timing[dmamode].active; 392 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 393 act_tick = ATA4_TIME_TO_TICK(min_active); 394 inact_tick = cycle_tick - act_tick; 395 /* mask: 0x001ffc00 */ 396 conf |= (act_tick << 10) | (inact_tick << 15); 397 } 398 /* set up udma mode timings */ 399 if (drvp->drive_flags & DRIVE_UDMA) { 400 int udmamode = drvp->UDMA_mode; 401 min_cycle = udma_timing[udmamode].cycle; 402 min_active = udma_timing[udmamode].active; 403 act_tick = ATA4_TIME_TO_TICK(min_active); 404 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 405 /* mask: 0x1ff00000 */ 406 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 407 } 408 #ifdef DEBUG 409 if (conf) { 410 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 411 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 412 } 413 #endif 414 sc->sc_dmaconf[drive] = conf; 415 } 416 sc->sc_wdcdev.select = 0; 417 if (sc->sc_dmaconf[0]) { 418 wdc_obio_select(chp,0); 419 if (sc->sc_dmaconf[1] && 420 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 421 sc->sc_wdcdev.select = wdc_obio_select; 422 } 423 } else if (sc->sc_dmaconf[1]) { 424 wdc_obio_select(chp,1); 425 } 426 } 427 428 int 429 wdc_obio_detach(self, flags) 430 struct device *self; 431 int flags; 432 { 433 struct wdc_obio_softc *sc = (void *)self; 434 int error; 435 436 if ((error = wdcdetach(self, flags)) != 0) 437 return error; 438 439 intr_disestablish(sc->sc_ih); 440 441 /* Unmap our i/o space. */ 442 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot, 443 sc->sc_wdcdev.regs->cmd_ioh, WDC_REG_NPORTS); 444 445 /* Unmap DMA registers. */ 446 /* XXX unmapiodev(sc->sc_dmareg); */ 447 /* XXX free(sc->sc_dmacmd); */ 448 449 return 0; 450 } 451 452 int 453 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 454 void *v; 455 void *databuf; 456 size_t datalen; 457 int flags; 458 { 459 struct wdc_obio_softc *sc = v; 460 vaddr_t va = (vaddr_t)databuf; 461 dbdma_command_t *cmdp; 462 u_int cmd, offset; 463 int read = flags & WDC_DMA_READ; 464 465 cmdp = sc->sc_dmacmd; 466 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 467 468 offset = va & PGOFSET; 469 470 /* if va is not page-aligned, setup the first page */ 471 if (offset != 0) { 472 int rest = PAGE_SIZE - offset; /* the rest of the page */ 473 474 if (datalen > rest) { /* if continues to next page */ 475 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 476 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 477 DBDMA_BRANCH_NEVER); 478 datalen -= rest; 479 va += rest; 480 cmdp++; 481 } 482 } 483 484 /* now va is page-aligned */ 485 while (datalen > PAGE_SIZE) { 486 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 487 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 488 datalen -= PAGE_SIZE; 489 va += PAGE_SIZE; 490 cmdp++; 491 } 492 493 /* the last page (datalen <= PAGE_SIZE here) */ 494 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 495 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 496 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 497 cmdp++; 498 499 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 500 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 501 502 return 0; 503 } 504 505 void 506 wdc_obio_dma_start(v, channel, drive) 507 void *v; 508 int channel, drive; 509 { 510 struct wdc_obio_softc *sc = v; 511 512 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 513 } 514 515 int 516 wdc_obio_dma_finish(v, channel, drive, read) 517 void *v; 518 int channel, drive; 519 int read; 520 { 521 struct wdc_obio_softc *sc = v; 522 523 dbdma_stop(sc->sc_dmareg); 524 return 0; 525 } 526
Indexes created Mon Sep 29 21:09:56 GMT 2025