wdc_obio.c revision 1.45
1 /* $NetBSD: wdc_obio.c,v 1.45 2006/09/04 03:44:10 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.45 2006/09/04 03:44:10 macallan Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <dev/ata/atareg.h> 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 #include <macppc/dev/dbdma.h> 59 60 #define WDC_REG_NPORTS 8 61 #define WDC_AUXREG_OFFSET 0x16 62 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 63 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 64 65 #define WDC_OPTIONS_DMA 0x01 66 67 /* 68 * XXX This code currently doesn't even try to allow 32-bit data port use. 69 */ 70 71 struct wdc_obio_softc { 72 struct wdc_softc sc_wdcdev; 73 struct ata_channel *sc_chanptr; 74 struct ata_channel sc_channel; 75 struct ata_queue sc_chqueue; 76 struct wdc_regs sc_wdc_regs; 77 dbdma_regmap_t *sc_dmareg; 78 dbdma_command_t *sc_dmacmd; 79 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 80 void *sc_ih; 81 }; 82 83 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 84 void wdc_obio_attach __P((struct device *, struct device *, void *)); 85 int wdc_obio_detach __P((struct device *, int)); 86 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 87 void wdc_obio_dma_start __P((void *, int, int)); 88 int wdc_obio_dma_finish __P((void *, int, int, int)); 89 90 static void wdc_obio_select __P((struct ata_channel *, int)); 91 static void adjust_timing __P((struct ata_channel *)); 92 static void ata4_adjust_timing __P((struct ata_channel *)); 93 94 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 95 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 96 97 int 98 wdc_obio_probe(parent, match, aux) 99 struct device *parent; 100 struct cfdata *match; 101 void *aux; 102 { 103 struct confargs *ca = aux; 104 char compat[32]; 105 106 /* XXX should not use name */ 107 if (strcmp(ca->ca_name, "ATA") == 0 || 108 strcmp(ca->ca_name, "ata") == 0 || 109 strcmp(ca->ca_name, "ata0") == 0 || 110 strcmp(ca->ca_name, "ide") == 0) 111 return 1; 112 113 memset(compat, 0, sizeof(compat)); 114 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 115 if (strcmp(compat, "heathrow-ata") == 0 || 116 strcmp(compat, "keylargo-ata") == 0) 117 return 1; 118 119 return 0; 120 } 121 122 void 123 wdc_obio_attach(parent, self, aux) 124 struct device *parent, *self; 125 void *aux; 126 { 127 struct wdc_obio_softc *sc = (void *)self; 128 struct wdc_regs *wdr; 129 struct confargs *ca = aux; 130 struct ata_channel *chp = &sc->sc_channel; 131 int intr, i; 132 int use_dma = 0; 133 char path[80], compat[32]; 134 135 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 136 137 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 138 WDC_OPTIONS_DMA) { 139 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 140 use_dma = 1; /* XXX Don't work yet. */ 141 } 142 143 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 144 intr = ca->ca_intr[0]; 145 printf(" irq %d", intr); 146 } else if (ca->ca_nintr == -1) { 147 intr = WDC_DEFAULT_PIO_IRQ; 148 printf(" irq property not found; using %d", intr); 149 } else { 150 printf(": couldn't get irq property\n"); 151 return; 152 } 153 154 /* disable DMA on Heathrow */ 155 if (strcmp(compat, "heathrow-ata") == 0) { 156 use_dma = 0; 157 printf(": DMA disabled"); 158 } 159 160 if (use_dma) 161 printf(": DMA transfer"); 162 163 printf("\n"); 164 165 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 166 167 wdr->cmd_iot = wdr->ctl_iot = 168 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 169 170 if (bus_space_map(wdr->cmd_iot, 0, WDC_REG_NPORTS, 0, 171 &wdr->cmd_baseioh) || 172 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 173 WDC_AUXREG_OFFSET, 1, &wdr->ctl_ioh)) { 174 printf("%s: couldn't map registers\n", 175 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 176 return; 177 } 178 for (i = 0; i < WDC_NREG; i++) { 179 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 180 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 181 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 182 WDC_REG_NPORTS); 183 printf("%s: couldn't subregion registers\n", 184 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 185 return; 186 } 187 } 188 #if 0 189 wdr->data32iot = wdr->cmd_iot; 190 wdr->data32ioh = wdr->cmd_ioh; 191 #endif 192 193 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 194 195 if (use_dma) { 196 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 197 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 198 ca->ca_reg[3]); 199 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 200 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 201 if (strcmp(ca->ca_name, "ata-4") == 0) { 202 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 203 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 204 sc->sc_wdcdev.sc_atac.atac_set_modes = 205 ata4_adjust_timing; 206 } else { 207 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 208 } 209 #ifdef notyet 210 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 211 if (ohare) { 212 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3; 213 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1; 214 } 215 #endif 216 } else { 217 /* all non-DMA controllers can use adjust_timing */ 218 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 219 } 220 221 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 222 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 223 sc->sc_chanptr = chp; 224 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 225 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 226 sc->sc_wdcdev.dma_arg = sc; 227 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 228 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 229 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 230 chp->ch_channel = 0; 231 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 232 chp->ch_queue = &sc->sc_chqueue; 233 chp->ch_ndrive = 2; 234 235 wdc_init_shadow_regs(chp); 236 237 #define OHARE_FEATURE_REG 0xf3000038 238 239 /* XXX Enable wdc1 by feature reg. */ 240 memset(path, 0, sizeof(path)); 241 OF_package_to_path(ca->ca_node, path, sizeof(path)); 242 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 243 u_int x; 244 245 x = in32rb(OHARE_FEATURE_REG); 246 x |= 8; 247 out32rb(OHARE_FEATURE_REG, x); 248 } 249 250 wdcattach(chp); 251 } 252 253 /* Multiword DMA transfer timings */ 254 struct ide_timings { 255 int cycle; /* minimum cycle time [ns] */ 256 int active; /* minimum command active time [ns] */ 257 }; 258 static struct ide_timings pio_timing[5] = { 259 { 600, 180 }, /* Mode 0 */ 260 { 390, 150 }, /* 1 */ 261 { 240, 105 }, /* 2 */ 262 { 180, 90 }, /* 3 */ 263 { 120, 75 } /* 4 */ 264 }; 265 static struct ide_timings dma_timing[3] = { 266 { 480, 240 }, /* Mode 0 */ 267 { 165, 90 }, /* Mode 1 */ 268 { 120, 75 } /* Mode 2 */ 269 }; 270 271 static struct ide_timings udma_timing[5] = { 272 {120, 180}, /* Mode 0 */ 273 { 90, 150}, /* Mode 1 */ 274 { 60, 120}, /* Mode 2 */ 275 { 45, 90}, /* Mode 3 */ 276 { 30, 90} /* Mode 4 */ 277 }; 278 279 #define TIME_TO_TICK(time) howmany((time), 30) 280 #define PIO_REC_OFFSET 4 281 #define PIO_REC_MIN 1 282 #define PIO_ACT_MIN 1 283 #define DMA_REC_OFFSET 1 284 #define DMA_REC_MIN 1 285 #define DMA_ACT_MIN 1 286 287 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 288 289 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 290 291 void 292 wdc_obio_select(chp, drive) 293 struct ata_channel *chp; 294 int drive; 295 { 296 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 297 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 298 299 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 300 CONFIG_REG, sc->sc_dmaconf[drive]); 301 } 302 303 void 304 adjust_timing(chp) 305 struct ata_channel *chp; 306 { 307 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 308 int drive; 309 int min_cycle = 0, min_active = 0; 310 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 311 312 for (drive = 0; drive < 2; drive++) { 313 u_int conf = 0; 314 struct ata_drive_datas *drvp; 315 316 drvp = &chp->ch_drive[drive]; 317 /* set up pio mode timings */ 318 if (drvp->drive_flags & DRIVE) { 319 int piomode = drvp->PIO_mode; 320 min_cycle = pio_timing[piomode].cycle; 321 min_active = pio_timing[piomode].active; 322 323 cycle_tick = TIME_TO_TICK(min_cycle); 324 act_tick = TIME_TO_TICK(min_active); 325 if (act_tick < PIO_ACT_MIN) 326 act_tick = PIO_ACT_MIN; 327 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 328 if (inact_tick < PIO_REC_MIN) 329 inact_tick = PIO_REC_MIN; 330 /* mask: 0x000007ff */ 331 conf |= (inact_tick << 5) | act_tick; 332 } 333 /* Set up DMA mode timings */ 334 if (drvp->drive_flags & DRIVE_DMA) { 335 int dmamode = drvp->DMA_mode; 336 min_cycle = dma_timing[dmamode].cycle; 337 min_active = dma_timing[dmamode].active; 338 cycle_tick = TIME_TO_TICK(min_cycle); 339 act_tick = TIME_TO_TICK(min_active); 340 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 341 if (inact_tick < DMA_REC_MIN) 342 inact_tick = DMA_REC_MIN; 343 half_tick = 0; /* XXX */ 344 /* mask: 0xfffff800 */ 345 conf |= 346 (half_tick << 21) | 347 (inact_tick << 16) | (act_tick << 11); 348 } 349 #ifdef DEBUG 350 if (conf) { 351 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 352 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 353 } 354 #endif 355 sc->sc_dmaconf[drive] = conf; 356 } 357 sc->sc_wdcdev.select = 0; 358 if (sc->sc_dmaconf[0]) { 359 wdc_obio_select(chp,0); 360 if (sc->sc_dmaconf[1] && 361 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 362 sc->sc_wdcdev.select = wdc_obio_select; 363 } 364 } else if (sc->sc_dmaconf[1]) { 365 wdc_obio_select(chp,1); 366 } 367 } 368 369 void 370 ata4_adjust_timing(chp) 371 struct ata_channel *chp; 372 { 373 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 374 int drive; 375 int min_cycle = 0, min_active = 0; 376 int cycle_tick = 0, act_tick = 0, inact_tick = 0; 377 378 for (drive = 0; drive < 2; drive++) { 379 u_int conf = 0; 380 struct ata_drive_datas *drvp; 381 382 drvp = &chp->ch_drive[drive]; 383 /* set up pio mode timings */ 384 385 if (drvp->drive_flags & DRIVE) { 386 int piomode = drvp->PIO_mode; 387 min_cycle = pio_timing[piomode].cycle; 388 min_active = pio_timing[piomode].active; 389 390 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 391 act_tick = ATA4_TIME_TO_TICK(min_active); 392 inact_tick = cycle_tick - act_tick; 393 /* mask: 0x000003ff */ 394 conf |= (inact_tick << 5) | act_tick; 395 } 396 /* set up dma mode timings */ 397 if (drvp->drive_flags & DRIVE_DMA) { 398 int dmamode = drvp->DMA_mode; 399 min_cycle = dma_timing[dmamode].cycle; 400 min_active = dma_timing[dmamode].active; 401 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 402 act_tick = ATA4_TIME_TO_TICK(min_active); 403 inact_tick = cycle_tick - act_tick; 404 /* mask: 0x001ffc00 */ 405 conf |= (act_tick << 10) | (inact_tick << 15); 406 } 407 /* set up udma mode timings */ 408 if (drvp->drive_flags & DRIVE_UDMA) { 409 int udmamode = drvp->UDMA_mode; 410 min_cycle = udma_timing[udmamode].cycle; 411 min_active = udma_timing[udmamode].active; 412 act_tick = ATA4_TIME_TO_TICK(min_active); 413 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 414 /* mask: 0x1ff00000 */ 415 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 416 } 417 #ifdef DEBUG 418 if (conf) { 419 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 420 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 421 } 422 #endif 423 sc->sc_dmaconf[drive] = conf; 424 } 425 sc->sc_wdcdev.select = 0; 426 if (sc->sc_dmaconf[0]) { 427 wdc_obio_select(chp,0); 428 if (sc->sc_dmaconf[1] && 429 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 430 sc->sc_wdcdev.select = wdc_obio_select; 431 } 432 } else if (sc->sc_dmaconf[1]) { 433 wdc_obio_select(chp,1); 434 } 435 } 436 437 int 438 wdc_obio_detach(self, flags) 439 struct device *self; 440 int flags; 441 { 442 struct wdc_obio_softc *sc = (void *)self; 443 int error; 444 445 if ((error = wdcdetach(self, flags)) != 0) 446 return error; 447 448 intr_disestablish(sc->sc_ih); 449 450 /* Unmap our i/o space. */ 451 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot, 452 sc->sc_wdcdev.regs->cmd_ioh, WDC_REG_NPORTS); 453 454 /* Unmap DMA registers. */ 455 /* XXX unmapiodev(sc->sc_dmareg); */ 456 /* XXX free(sc->sc_dmacmd); */ 457 458 return 0; 459 } 460 461 int 462 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 463 void *v; 464 void *databuf; 465 size_t datalen; 466 int flags; 467 { 468 struct wdc_obio_softc *sc = v; 469 vaddr_t va = (vaddr_t)databuf; 470 dbdma_command_t *cmdp; 471 u_int cmd, offset; 472 int read = flags & WDC_DMA_READ; 473 474 cmdp = sc->sc_dmacmd; 475 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 476 477 offset = va & PGOFSET; 478 479 /* if va is not page-aligned, setup the first page */ 480 if (offset != 0) { 481 int rest = PAGE_SIZE - offset; /* the rest of the page */ 482 483 if (datalen > rest) { /* if continues to next page */ 484 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 485 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 486 DBDMA_BRANCH_NEVER); 487 datalen -= rest; 488 va += rest; 489 cmdp++; 490 } 491 } 492 493 /* now va is page-aligned */ 494 while (datalen > PAGE_SIZE) { 495 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 496 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 497 datalen -= PAGE_SIZE; 498 va += PAGE_SIZE; 499 cmdp++; 500 } 501 502 /* the last page (datalen <= PAGE_SIZE here) */ 503 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 504 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 505 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 506 cmdp++; 507 508 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 509 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 510 511 return 0; 512 } 513 514 void 515 wdc_obio_dma_start(v, channel, drive) 516 void *v; 517 int channel, drive; 518 { 519 struct wdc_obio_softc *sc = v; 520 521 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 522 } 523 524 int 525 wdc_obio_dma_finish(v, channel, drive, read) 526 void *v; 527 int channel, drive; 528 int read; 529 { 530 struct wdc_obio_softc *sc = v; 531 532 dbdma_stop(sc->sc_dmareg); 533 return 0; 534 } 535
Indexes created Mon Sep 29 13:09:55 GMT 2025