wdc_obio.c revision 1.46
1 /* $NetBSD: wdc_obio.c,v 1.46 2006/11/07 02:23:27 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.46 2006/11/07 02:23:27 macallan Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 52 #include <dev/ata/atareg.h> 53 #include <dev/ata/atavar.h> 54 #include <dev/ic/wdcvar.h> 55 56 #include <dev/ofw/openfirm.h> 57 58 #include <macppc/dev/dbdma.h> 59 60 #define WDC_REG_NPORTS 8 61 #define WDC_AUXREG_OFFSET 0x16 62 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 63 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 64 65 #define WDC_OPTIONS_DMA 0x01 66 67 /* 68 * XXX This code currently doesn't even try to allow 32-bit data port use. 69 */ 70 71 struct wdc_obio_softc { 72 struct wdc_softc sc_wdcdev; 73 struct ata_channel *sc_chanptr; 74 struct ata_channel sc_channel; 75 struct ata_queue sc_chqueue; 76 struct wdc_regs sc_wdc_regs; 77 dbdma_regmap_t *sc_dmareg; 78 dbdma_command_t *sc_dmacmd; 79 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 80 void *sc_ih; 81 }; 82 83 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 84 void wdc_obio_attach __P((struct device *, struct device *, void *)); 85 int wdc_obio_detach __P((struct device *, int)); 86 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 87 void wdc_obio_dma_start __P((void *, int, int)); 88 int wdc_obio_dma_finish __P((void *, int, int, int)); 89 90 static void wdc_obio_select __P((struct ata_channel *, int)); 91 static void adjust_timing __P((struct ata_channel *)); 92 static void ata4_adjust_timing __P((struct ata_channel *)); 93 94 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 95 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 96 97 int 98 wdc_obio_probe(parent, match, aux) 99 struct device *parent; 100 struct cfdata *match; 101 void *aux; 102 { 103 struct confargs *ca = aux; 104 char compat[32]; 105 106 /* XXX should not use name */ 107 if (strcmp(ca->ca_name, "ATA") == 0 || 108 strcmp(ca->ca_name, "ata") == 0 || 109 strcmp(ca->ca_name, "ata0") == 0 || 110 strcmp(ca->ca_name, "ide") == 0) 111 return 1; 112 113 memset(compat, 0, sizeof(compat)); 114 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 115 if (strcmp(compat, "heathrow-ata") == 0 || 116 strcmp(compat, "keylargo-ata") == 0) 117 return 1; 118 119 return 0; 120 } 121 122 void 123 wdc_obio_attach(parent, self, aux) 124 struct device *parent, *self; 125 void *aux; 126 { 127 struct wdc_obio_softc *sc = (void *)self; 128 struct wdc_regs *wdr; 129 struct confargs *ca = aux; 130 struct ata_channel *chp = &sc->sc_channel; 131 int intr, i; 132 int use_dma = 0; 133 char path[80], compat[32]; 134 135 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 136 137 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 138 WDC_OPTIONS_DMA) { 139 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 140 use_dma = 1; /* XXX Don't work yet. */ 141 } 142 143 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 144 intr = ca->ca_intr[0]; 145 printf(" irq %d", intr); 146 } else if (ca->ca_nintr == -1) { 147 intr = WDC_DEFAULT_PIO_IRQ; 148 printf(" irq property not found; using %d", intr); 149 } else { 150 printf(": couldn't get irq property\n"); 151 return; 152 } 153 154 if (use_dma) 155 printf(": DMA transfer"); 156 157 printf("\n"); 158 159 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 160 161 wdr->cmd_iot = wdr->ctl_iot = 162 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 163 164 if (bus_space_map(wdr->cmd_iot, 0, WDC_REG_NPORTS, 0, 165 &wdr->cmd_baseioh) || 166 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 167 WDC_AUXREG_OFFSET, 1, &wdr->ctl_ioh)) { 168 printf("%s: couldn't map registers\n", 169 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 170 return; 171 } 172 for (i = 0; i < WDC_NREG; i++) { 173 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 174 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 175 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 176 WDC_REG_NPORTS); 177 printf("%s: couldn't subregion registers\n", 178 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 179 return; 180 } 181 } 182 #if 0 183 wdr->data32iot = wdr->cmd_iot; 184 wdr->data32ioh = wdr->cmd_ioh; 185 #endif 186 187 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 188 189 if (use_dma) { 190 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 191 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 192 ca->ca_reg[3]); 193 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 194 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 195 if (strcmp(ca->ca_name, "ata-4") == 0) { 196 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 197 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 198 sc->sc_wdcdev.sc_atac.atac_set_modes = 199 ata4_adjust_timing; 200 } else { 201 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 202 } 203 #ifdef notyet 204 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 205 if (ohare) { 206 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3; 207 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1; 208 } 209 #endif 210 } else { 211 /* all non-DMA controllers can use adjust_timing */ 212 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 213 } 214 215 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 216 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 217 sc->sc_chanptr = chp; 218 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 219 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 220 sc->sc_wdcdev.dma_arg = sc; 221 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 222 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 223 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 224 chp->ch_channel = 0; 225 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 226 chp->ch_queue = &sc->sc_chqueue; 227 chp->ch_ndrive = 2; 228 229 wdc_init_shadow_regs(chp); 230 231 #define OHARE_FEATURE_REG 0xf3000038 232 233 /* XXX Enable wdc1 by feature reg. */ 234 memset(path, 0, sizeof(path)); 235 OF_package_to_path(ca->ca_node, path, sizeof(path)); 236 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 237 u_int x; 238 239 x = in32rb(OHARE_FEATURE_REG); 240 x |= 8; 241 out32rb(OHARE_FEATURE_REG, x); 242 } 243 244 wdcattach(chp); 245 } 246 247 /* Multiword DMA transfer timings */ 248 struct ide_timings { 249 int cycle; /* minimum cycle time [ns] */ 250 int active; /* minimum command active time [ns] */ 251 }; 252 static struct ide_timings pio_timing[5] = { 253 { 600, 180 }, /* Mode 0 */ 254 { 390, 150 }, /* 1 */ 255 { 240, 105 }, /* 2 */ 256 { 180, 90 }, /* 3 */ 257 { 120, 75 } /* 4 */ 258 }; 259 static struct ide_timings dma_timing[3] = { 260 { 480, 240 }, /* Mode 0 */ 261 { 165, 90 }, /* Mode 1 */ 262 { 120, 75 } /* Mode 2 */ 263 }; 264 265 static struct ide_timings udma_timing[5] = { 266 {120, 180}, /* Mode 0 */ 267 { 90, 150}, /* Mode 1 */ 268 { 60, 120}, /* Mode 2 */ 269 { 45, 90}, /* Mode 3 */ 270 { 30, 90} /* Mode 4 */ 271 }; 272 273 #define TIME_TO_TICK(time) howmany((time), 30) 274 #define PIO_REC_OFFSET 4 275 #define PIO_REC_MIN 1 276 #define PIO_ACT_MIN 1 277 #define DMA_REC_OFFSET 1 278 #define DMA_REC_MIN 1 279 #define DMA_ACT_MIN 1 280 281 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 282 283 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 284 285 void 286 wdc_obio_select(chp, drive) 287 struct ata_channel *chp; 288 int drive; 289 { 290 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 291 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 292 293 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 294 CONFIG_REG, sc->sc_dmaconf[drive]); 295 } 296 297 void 298 adjust_timing(chp) 299 struct ata_channel *chp; 300 { 301 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 302 int drive; 303 int min_cycle = 0, min_active = 0; 304 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 305 306 for (drive = 0; drive < 2; drive++) { 307 u_int conf = 0; 308 struct ata_drive_datas *drvp; 309 310 drvp = &chp->ch_drive[drive]; 311 /* set up pio mode timings */ 312 if (drvp->drive_flags & DRIVE) { 313 int piomode = drvp->PIO_mode; 314 min_cycle = pio_timing[piomode].cycle; 315 min_active = pio_timing[piomode].active; 316 317 cycle_tick = TIME_TO_TICK(min_cycle); 318 act_tick = TIME_TO_TICK(min_active); 319 if (act_tick < PIO_ACT_MIN) 320 act_tick = PIO_ACT_MIN; 321 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 322 if (inact_tick < PIO_REC_MIN) 323 inact_tick = PIO_REC_MIN; 324 /* mask: 0x000007ff */ 325 conf |= (inact_tick << 5) | act_tick; 326 } 327 /* Set up DMA mode timings */ 328 if (drvp->drive_flags & DRIVE_DMA) { 329 int dmamode = drvp->DMA_mode; 330 min_cycle = dma_timing[dmamode].cycle; 331 min_active = dma_timing[dmamode].active; 332 cycle_tick = TIME_TO_TICK(min_cycle); 333 act_tick = TIME_TO_TICK(min_active); 334 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 335 if (inact_tick < DMA_REC_MIN) 336 inact_tick = DMA_REC_MIN; 337 half_tick = 0; /* XXX */ 338 /* mask: 0xfffff800 */ 339 conf |= 340 (half_tick << 21) | 341 (inact_tick << 16) | (act_tick << 11); 342 } 343 #ifdef DEBUG 344 if (conf) { 345 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 346 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 347 } 348 #endif 349 sc->sc_dmaconf[drive] = conf; 350 } 351 sc->sc_wdcdev.select = 0; 352 if (sc->sc_dmaconf[0]) { 353 wdc_obio_select(chp,0); 354 if (sc->sc_dmaconf[1] && 355 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 356 sc->sc_wdcdev.select = wdc_obio_select; 357 } 358 } else if (sc->sc_dmaconf[1]) { 359 wdc_obio_select(chp,1); 360 } 361 } 362 363 void 364 ata4_adjust_timing(chp) 365 struct ata_channel *chp; 366 { 367 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 368 int drive; 369 int min_cycle = 0, min_active = 0; 370 int cycle_tick = 0, act_tick = 0, inact_tick = 0; 371 372 for (drive = 0; drive < 2; drive++) { 373 u_int conf = 0; 374 struct ata_drive_datas *drvp; 375 376 drvp = &chp->ch_drive[drive]; 377 /* set up pio mode timings */ 378 379 if (drvp->drive_flags & DRIVE) { 380 int piomode = drvp->PIO_mode; 381 min_cycle = pio_timing[piomode].cycle; 382 min_active = pio_timing[piomode].active; 383 384 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 385 act_tick = ATA4_TIME_TO_TICK(min_active); 386 inact_tick = cycle_tick - act_tick; 387 /* mask: 0x000003ff */ 388 conf |= (inact_tick << 5) | act_tick; 389 } 390 /* set up dma mode timings */ 391 if (drvp->drive_flags & DRIVE_DMA) { 392 int dmamode = drvp->DMA_mode; 393 min_cycle = dma_timing[dmamode].cycle; 394 min_active = dma_timing[dmamode].active; 395 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 396 act_tick = ATA4_TIME_TO_TICK(min_active); 397 inact_tick = cycle_tick - act_tick; 398 /* mask: 0x001ffc00 */ 399 conf |= (act_tick << 10) | (inact_tick << 15); 400 } 401 /* set up udma mode timings */ 402 if (drvp->drive_flags & DRIVE_UDMA) { 403 int udmamode = drvp->UDMA_mode; 404 min_cycle = udma_timing[udmamode].cycle; 405 min_active = udma_timing[udmamode].active; 406 act_tick = ATA4_TIME_TO_TICK(min_active); 407 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 408 /* mask: 0x1ff00000 */ 409 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 410 } 411 #ifdef DEBUG 412 if (conf) { 413 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 414 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 415 } 416 #endif 417 sc->sc_dmaconf[drive] = conf; 418 } 419 sc->sc_wdcdev.select = 0; 420 if (sc->sc_dmaconf[0]) { 421 wdc_obio_select(chp,0); 422 if (sc->sc_dmaconf[1] && 423 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 424 sc->sc_wdcdev.select = wdc_obio_select; 425 } 426 } else if (sc->sc_dmaconf[1]) { 427 wdc_obio_select(chp,1); 428 } 429 } 430 431 int 432 wdc_obio_detach(self, flags) 433 struct device *self; 434 int flags; 435 { 436 struct wdc_obio_softc *sc = (void *)self; 437 int error; 438 439 if ((error = wdcdetach(self, flags)) != 0) 440 return error; 441 442 intr_disestablish(sc->sc_ih); 443 444 /* Unmap our i/o space. */ 445 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot, 446 sc->sc_wdcdev.regs->cmd_ioh, WDC_REG_NPORTS); 447 448 /* Unmap DMA registers. */ 449 /* XXX unmapiodev(sc->sc_dmareg); */ 450 /* XXX free(sc->sc_dmacmd); */ 451 452 return 0; 453 } 454 455 int 456 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 457 void *v; 458 void *databuf; 459 size_t datalen; 460 int flags; 461 { 462 struct wdc_obio_softc *sc = v; 463 vaddr_t va = (vaddr_t)databuf; 464 dbdma_command_t *cmdp; 465 u_int cmd, offset; 466 int read = flags & WDC_DMA_READ; 467 468 cmdp = sc->sc_dmacmd; 469 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 470 471 offset = va & PGOFSET; 472 473 /* if va is not page-aligned, setup the first page */ 474 if (offset != 0) { 475 int rest = PAGE_SIZE - offset; /* the rest of the page */ 476 477 if (datalen > rest) { /* if continues to next page */ 478 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 479 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 480 DBDMA_BRANCH_NEVER); 481 datalen -= rest; 482 va += rest; 483 cmdp++; 484 } 485 } 486 487 /* now va is page-aligned */ 488 while (datalen > PAGE_SIZE) { 489 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 490 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 491 datalen -= PAGE_SIZE; 492 va += PAGE_SIZE; 493 cmdp++; 494 } 495 496 /* the last page (datalen <= PAGE_SIZE here) */ 497 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 498 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 499 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 500 cmdp++; 501 502 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 503 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 504 505 return 0; 506 } 507 508 void 509 wdc_obio_dma_start(v, channel, drive) 510 void *v; 511 int channel, drive; 512 { 513 struct wdc_obio_softc *sc = v; 514 515 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 516 } 517 518 int 519 wdc_obio_dma_finish(v, channel, drive, read) 520 void *v; 521 int channel, drive; 522 int read; 523 { 524 struct wdc_obio_softc *sc = v; 525 526 dbdma_stop(sc->sc_dmareg); 527 return 0; 528 } 529
Indexes created Tue Oct 21 19:09:51 GMT 2025