wdc_obio.c revision 1.46.16.5
1 /* $NetBSD: wdc_obio.c,v 1.46.16.5 2007/08/02 22:14:12 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wdc_obio.c,v 1.46.16.5 2007/08/02 22:14:12 macallan Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/malloc.h> 46 #include <sys/extent.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <machine/bus.h> 51 #include <machine/autoconf.h> 52 #include <machine/pio.h> 53 54 #include <dev/ata/atareg.h> 55 #include <dev/ata/atavar.h> 56 #include <dev/ic/wdcvar.h> 57 58 #include <dev/ofw/openfirm.h> 59 60 #include <macppc/dev/dbdma.h> 61 62 #define WDC_REG_NPORTS 8 63 #define WDC_AUXREG_OFFSET 0x16 64 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 65 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 66 67 #define WDC_OPTIONS_DMA 0x01 68 69 /* 70 * XXX This code currently doesn't even try to allow 32-bit data port use. 71 */ 72 73 u_int8_t bsr1_s(bus_space_tag_t, bus_space_handle_t, bus_size_t); 74 75 76 struct wdc_obio_softc { 77 struct wdc_softc sc_wdcdev; 78 struct ata_channel *sc_chanptr; 79 struct ata_channel sc_channel; 80 struct ata_queue sc_chqueue; 81 struct wdc_regs sc_wdc_regs; 82 struct powerpc_bus_space sc_bus_space; 83 dbdma_regmap_t *sc_dmareg; 84 dbdma_command_t *sc_dmacmd; 85 u_int sc_dmaconf[2]; /* per target value of CONFIG_REG */ 86 void *sc_ih; 87 }; 88 89 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 90 void wdc_obio_attach __P((struct device *, struct device *, void *)); 91 int wdc_obio_detach __P((struct device *, int)); 92 int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 93 void wdc_obio_dma_start __P((void *, int, int)); 94 int wdc_obio_dma_finish __P((void *, int, int, int)); 95 96 static void wdc_obio_select __P((struct ata_channel *, int)); 97 static void adjust_timing __P((struct ata_channel *)); 98 static void ata4_adjust_timing __P((struct ata_channel *)); 99 100 CFATTACH_DECL(wdc_obio, sizeof(struct wdc_obio_softc), 101 wdc_obio_probe, wdc_obio_attach, wdc_obio_detach, wdcactivate); 102 103 int 104 wdc_obio_probe(parent, match, aux) 105 struct device *parent; 106 struct cfdata *match; 107 void *aux; 108 { 109 struct confargs *ca = aux; 110 char compat[32]; 111 112 /* XXX should not use name */ 113 if (strcmp(ca->ca_name, "ATA") == 0 || 114 strcmp(ca->ca_name, "ata") == 0 || 115 strcmp(ca->ca_name, "ata0") == 0 || 116 strcmp(ca->ca_name, "ide") == 0) 117 return 1; 118 119 memset(compat, 0, sizeof(compat)); 120 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 121 if (strcmp(compat, "heathrow-ata") == 0 || 122 strcmp(compat, "keylargo-ata") == 0) 123 return 1; 124 125 return 0; 126 } 127 128 void 129 wdc_obio_attach(parent, self, aux) 130 struct device *parent, *self; 131 void *aux; 132 { 133 struct wdc_obio_softc *sc = (void *)self; 134 struct wdc_regs *wdr; 135 struct confargs *ca = aux; 136 struct ata_channel *chp = &sc->sc_channel; 137 int intr, i; 138 int use_dma = 0; 139 char path[80], compat[32]; 140 141 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 142 143 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 144 WDC_OPTIONS_DMA) { 145 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 146 use_dma = 1; /* XXX Don't work yet. */ 147 } 148 149 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 150 intr = ca->ca_intr[0]; 151 printf(" irq %d", intr); 152 } else if (ca->ca_nintr == -1) { 153 intr = WDC_DEFAULT_PIO_IRQ; 154 printf(" irq property not found; using %d", intr); 155 } else { 156 printf(": couldn't get irq property\n"); 157 return; 158 } 159 160 if (use_dma) 161 printf(": DMA transfer"); 162 163 printf("\n"); 164 165 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs; 166 167 #if 0 168 wdr->cmd_iot = wdr->ctl_iot = 169 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 170 #endif 171 wdr->cmd_iot = wdr->ctl_iot = &sc->sc_bus_space; 172 sc->sc_bus_space.pbs_flags = 173 ca->ca_tag->pbs_flags & ~_BUS_SPACE_STRIDE_MASK; 174 sc->sc_bus_space.pbs_flags |= 4; 175 sc->sc_bus_space.pbs_offset = ca->ca_baseaddr + ca->ca_reg[0]; 176 sc->sc_bus_space.pbs_base = 0; 177 sc->sc_bus_space.pbs_limit = WDC_REG_NPORTS << 4; 178 sc->sc_bus_space.pbs_extent = extent_create("wdc_obio", 0, 0x100000, 179 M_DEVBUF, NULL, 0, EX_WAITOK); 180 181 if (bus_space_init(&sc->sc_bus_space, NULL, NULL, 0)) 182 panic("bus_space_init failed"); 183 184 if (bus_space_map(wdr->cmd_iot, 0, WDC_REG_NPORTS, 0, 185 &wdr->cmd_baseioh) || 186 bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 187 WDC_AUXREG_OFFSET, 1, &wdr->ctl_ioh)) { 188 printf("%s: couldn't map registers\n", 189 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 190 return; 191 } 192 193 for (i = 0; i < WDC_NREG; i++) { 194 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 195 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 196 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 197 WDC_REG_NPORTS); 198 printf("%s: couldn't subregion registers\n", 199 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 200 return; 201 } 202 } 203 #if 0 204 wdr->data32iot = wdr->cmd_iot; 205 wdr->data32ioh = wdr->cmd_ioh; 206 #endif 207 208 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 209 210 if (use_dma) { 211 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 212 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 213 ca->ca_reg[3]); 214 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 215 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 216 if (strcmp(ca->ca_name, "ata-4") == 0) { 217 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 218 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 219 sc->sc_wdcdev.sc_atac.atac_set_modes = 220 ata4_adjust_timing; 221 } else { 222 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 223 } 224 #ifdef notyet 225 /* Minimum cycle time is 150ns (DMA MODE 1) on ohare. */ 226 if (ohare) { 227 sc->sc_wdcdev.sc_atac.atac_pio_cap = 3; 228 sc->sc_wdcdev.sc_atac.atac_dma_cap = 1; 229 } 230 #endif 231 } else { 232 /* all non-DMA controllers can use adjust_timing */ 233 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing; 234 } 235 236 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 237 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 238 sc->sc_chanptr = chp; 239 sc->sc_wdcdev.sc_atac.atac_channels = &sc->sc_chanptr; 240 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 241 sc->sc_wdcdev.dma_arg = sc; 242 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 243 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 244 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 245 chp->ch_channel = 0; 246 chp->ch_atac = &sc->sc_wdcdev.sc_atac; 247 chp->ch_queue = &sc->sc_chqueue; 248 chp->ch_ndrive = 2; 249 250 wdc_init_shadow_regs(chp); 251 252 #define OHARE_FEATURE_REG 0xf3000038 253 254 /* XXX Enable wdc1 by feature reg. */ 255 memset(path, 0, sizeof(path)); 256 OF_package_to_path(ca->ca_node, path, sizeof(path)); 257 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 258 u_int x; 259 260 x = in32rb(OHARE_FEATURE_REG); 261 x |= 8; 262 out32rb(OHARE_FEATURE_REG, x); 263 } 264 265 wdcattach(chp); 266 } 267 268 /* Multiword DMA transfer timings */ 269 struct ide_timings { 270 int cycle; /* minimum cycle time [ns] */ 271 int active; /* minimum command active time [ns] */ 272 }; 273 static struct ide_timings pio_timing[5] = { 274 { 600, 180 }, /* Mode 0 */ 275 { 390, 150 }, /* 1 */ 276 { 240, 105 }, /* 2 */ 277 { 180, 90 }, /* 3 */ 278 { 120, 75 } /* 4 */ 279 }; 280 static struct ide_timings dma_timing[3] = { 281 { 480, 240 }, /* Mode 0 */ 282 { 165, 90 }, /* Mode 1 */ 283 { 120, 75 } /* Mode 2 */ 284 }; 285 286 static struct ide_timings udma_timing[5] = { 287 {120, 180}, /* Mode 0 */ 288 { 90, 150}, /* Mode 1 */ 289 { 60, 120}, /* Mode 2 */ 290 { 45, 90}, /* Mode 3 */ 291 { 30, 90} /* Mode 4 */ 292 }; 293 294 #define TIME_TO_TICK(time) howmany((time), 30) 295 #define PIO_REC_OFFSET 4 296 #define PIO_REC_MIN 1 297 #define PIO_ACT_MIN 1 298 #define DMA_REC_OFFSET 1 299 #define DMA_REC_MIN 1 300 #define DMA_ACT_MIN 1 301 302 #define ATA4_TIME_TO_TICK(time) howmany((time), 15) /* 15 ns clock */ 303 304 #define CONFIG_REG (0x200 >> 4) /* IDE access timing register */ 305 306 void 307 wdc_obio_select(chp, drive) 308 struct ata_channel *chp; 309 int drive; 310 { 311 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 312 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 313 314 bus_space_write_4(wdr->cmd_iot, wdr->cmd_baseioh, 315 CONFIG_REG, sc->sc_dmaconf[drive]); 316 } 317 318 void 319 adjust_timing(chp) 320 struct ata_channel *chp; 321 { 322 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 323 int drive; 324 int min_cycle = 0, min_active = 0; 325 int cycle_tick = 0, act_tick = 0, inact_tick = 0, half_tick; 326 327 for (drive = 0; drive < 2; drive++) { 328 u_int conf = 0; 329 struct ata_drive_datas *drvp; 330 331 drvp = &chp->ch_drive[drive]; 332 /* set up pio mode timings */ 333 if (drvp->drive_flags & DRIVE) { 334 int piomode = drvp->PIO_mode; 335 min_cycle = pio_timing[piomode].cycle; 336 min_active = pio_timing[piomode].active; 337 338 cycle_tick = TIME_TO_TICK(min_cycle); 339 act_tick = TIME_TO_TICK(min_active); 340 if (act_tick < PIO_ACT_MIN) 341 act_tick = PIO_ACT_MIN; 342 inact_tick = cycle_tick - act_tick - PIO_REC_OFFSET; 343 if (inact_tick < PIO_REC_MIN) 344 inact_tick = PIO_REC_MIN; 345 /* mask: 0x000007ff */ 346 conf |= (inact_tick << 5) | act_tick; 347 } 348 /* Set up DMA mode timings */ 349 if (drvp->drive_flags & DRIVE_DMA) { 350 int dmamode = drvp->DMA_mode; 351 min_cycle = dma_timing[dmamode].cycle; 352 min_active = dma_timing[dmamode].active; 353 cycle_tick = TIME_TO_TICK(min_cycle); 354 act_tick = TIME_TO_TICK(min_active); 355 inact_tick = cycle_tick - act_tick - DMA_REC_OFFSET; 356 if (inact_tick < DMA_REC_MIN) 357 inact_tick = DMA_REC_MIN; 358 half_tick = 0; /* XXX */ 359 /* mask: 0xfffff800 */ 360 conf |= 361 (half_tick << 21) | 362 (inact_tick << 16) | (act_tick << 11); 363 } 364 #ifdef DEBUG 365 if (conf) { 366 printf("conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 367 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 368 } 369 #endif 370 sc->sc_dmaconf[drive] = conf; 371 } 372 sc->sc_wdcdev.select = 0; 373 if (sc->sc_dmaconf[0]) { 374 wdc_obio_select(chp,0); 375 if (sc->sc_dmaconf[1] && 376 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 377 sc->sc_wdcdev.select = wdc_obio_select; 378 } 379 } else if (sc->sc_dmaconf[1]) { 380 wdc_obio_select(chp,1); 381 } 382 } 383 384 void 385 ata4_adjust_timing(chp) 386 struct ata_channel *chp; 387 { 388 struct wdc_obio_softc *sc = (struct wdc_obio_softc *)chp->ch_atac; 389 int drive; 390 int min_cycle = 0, min_active = 0; 391 int cycle_tick = 0, act_tick = 0, inact_tick = 0; 392 393 for (drive = 0; drive < 2; drive++) { 394 u_int conf = 0; 395 struct ata_drive_datas *drvp; 396 397 drvp = &chp->ch_drive[drive]; 398 /* set up pio mode timings */ 399 400 if (drvp->drive_flags & DRIVE) { 401 int piomode = drvp->PIO_mode; 402 min_cycle = pio_timing[piomode].cycle; 403 min_active = pio_timing[piomode].active; 404 405 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 406 act_tick = ATA4_TIME_TO_TICK(min_active); 407 inact_tick = cycle_tick - act_tick; 408 /* mask: 0x000003ff */ 409 conf |= (inact_tick << 5) | act_tick; 410 } 411 /* set up dma mode timings */ 412 if (drvp->drive_flags & DRIVE_DMA) { 413 int dmamode = drvp->DMA_mode; 414 min_cycle = dma_timing[dmamode].cycle; 415 min_active = dma_timing[dmamode].active; 416 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 417 act_tick = ATA4_TIME_TO_TICK(min_active); 418 inact_tick = cycle_tick - act_tick; 419 /* mask: 0x001ffc00 */ 420 conf |= (act_tick << 10) | (inact_tick << 15); 421 } 422 /* set up udma mode timings */ 423 if (drvp->drive_flags & DRIVE_UDMA) { 424 int udmamode = drvp->UDMA_mode; 425 min_cycle = udma_timing[udmamode].cycle; 426 min_active = udma_timing[udmamode].active; 427 act_tick = ATA4_TIME_TO_TICK(min_active); 428 cycle_tick = ATA4_TIME_TO_TICK(min_cycle); 429 /* mask: 0x1ff00000 */ 430 conf |= (cycle_tick << 21) | (act_tick << 25) | 0x100000; 431 } 432 #ifdef DEBUG 433 if (conf) { 434 printf("ata4 conf[%d] = 0x%x, cyc = %d (%d ns), act = %d (%d ns), inact = %d\n", 435 drive, conf, cycle_tick, min_cycle, act_tick, min_active, inact_tick); 436 } 437 #endif 438 sc->sc_dmaconf[drive] = conf; 439 } 440 sc->sc_wdcdev.select = 0; 441 if (sc->sc_dmaconf[0]) { 442 wdc_obio_select(chp,0); 443 if (sc->sc_dmaconf[1] && 444 (sc->sc_dmaconf[0] != sc->sc_dmaconf[1])) { 445 sc->sc_wdcdev.select = wdc_obio_select; 446 } 447 } else if (sc->sc_dmaconf[1]) { 448 wdc_obio_select(chp,1); 449 } 450 } 451 452 int 453 wdc_obio_detach(self, flags) 454 struct device *self; 455 int flags; 456 { 457 struct wdc_obio_softc *sc = (void *)self; 458 int error; 459 460 if ((error = wdcdetach(self, flags)) != 0) 461 return error; 462 463 intr_disestablish(sc->sc_ih); 464 465 /* Unmap our i/o space. */ 466 bus_space_unmap(sc->sc_wdcdev.regs->cmd_iot, 467 sc->sc_wdcdev.regs->cmd_baseioh, WDC_REG_NPORTS); 468 469 /* Unmap DMA registers. */ 470 /* XXX unmapiodev(sc->sc_dmareg); */ 471 /* XXX free(sc->sc_dmacmd); */ 472 473 return 0; 474 } 475 476 int 477 wdc_obio_dma_init(v, channel, drive, databuf, datalen, flags) 478 void *v; 479 void *databuf; 480 size_t datalen; 481 int flags; 482 { 483 struct wdc_obio_softc *sc = v; 484 vaddr_t va = (vaddr_t)databuf; 485 dbdma_command_t *cmdp; 486 u_int cmd, offset; 487 int read = flags & WDC_DMA_READ; 488 489 cmdp = sc->sc_dmacmd; 490 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 491 492 offset = va & PGOFSET; 493 494 /* if va is not page-aligned, setup the first page */ 495 if (offset != 0) { 496 int rest = PAGE_SIZE - offset; /* the rest of the page */ 497 498 if (datalen > rest) { /* if continues to next page */ 499 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 500 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 501 DBDMA_BRANCH_NEVER); 502 datalen -= rest; 503 va += rest; 504 cmdp++; 505 } 506 } 507 508 /* now va is page-aligned */ 509 while (datalen > PAGE_SIZE) { 510 DBDMA_BUILD(cmdp, cmd, 0, PAGE_SIZE, vtophys(va), 511 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 512 datalen -= PAGE_SIZE; 513 va += PAGE_SIZE; 514 cmdp++; 515 } 516 517 /* the last page (datalen <= PAGE_SIZE here) */ 518 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 519 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 520 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 521 cmdp++; 522 523 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 524 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 525 526 return 0; 527 } 528 529 void 530 wdc_obio_dma_start(v, channel, drive) 531 void *v; 532 int channel, drive; 533 { 534 struct wdc_obio_softc *sc = v; 535 536 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 537 } 538 539 int 540 wdc_obio_dma_finish(v, channel, drive, read) 541 void *v; 542 int channel, drive; 543 int read; 544 { 545 struct wdc_obio_softc *sc = v; 546 547 dbdma_stop(sc->sc_dmareg); 548 return 0; 549 } 550
Indexes created Wed Oct 22 13:09:56 GMT 2025