wdc_obio.c revision 1.7
1 /* $NetBSD: wdc_obio.c,v 1.7 2000/04/02 12:36:38 tsubai Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and by Onno van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <vm/vm.h> 45 46 #include <machine/bus.h> 47 #include <machine/autoconf.h> 48 49 #include <dev/ata/atavar.h> 50 #include <dev/ic/wdcvar.h> 51 52 #include <macppc/dev/dbdma.h> 53 54 #define WDC_REG_NPORTS 8 55 #define WDC_AUXREG_OFFSET 0x16 56 #define WDC_DEFAULT_PIO_IRQ 13 /* XXX */ 57 #define WDC_DEFAULT_DMA_IRQ 2 /* XXX */ 58 59 #define WDC_OPTIONS_DMA 0x01 60 61 /* 62 * XXX This code currently doesn't even try to allow 32-bit data port use. 63 */ 64 65 struct wdc_obio_softc { 66 struct wdc_softc sc_wdcdev; 67 struct channel_softc *wdc_chanptr; 68 struct channel_softc wdc_channel; 69 dbdma_regmap_t *sc_dmareg; 70 dbdma_command_t *sc_dmacmd; 71 void *sc_ih; 72 }; 73 74 int wdc_obio_probe __P((struct device *, struct cfdata *, void *)); 75 void wdc_obio_attach __P((struct device *, struct device *, void *)); 76 int wdc_obio_detach __P((struct device *, int)); 77 78 struct cfattach wdc_obio_ca = { 79 sizeof(struct wdc_obio_softc), wdc_obio_probe, wdc_obio_attach, 80 wdc_obio_detach, wdcactivate 81 }; 82 83 static int wdc_obio_dma_init __P((void *, int, int, void *, size_t, int)); 84 static void wdc_obio_dma_start __P((void *, int, int, int)); 85 static int wdc_obio_dma_finish __P((void *, int, int, int)); 86 87 int 88 wdc_obio_probe(parent, match, aux) 89 struct device *parent; 90 struct cfdata *match; 91 void *aux; 92 { 93 struct confargs *ca = aux; 94 char compat[32]; 95 96 /* XXX should not use name */ 97 if (strcmp(ca->ca_name, "ATA") == 0 || 98 strcmp(ca->ca_name, "ata") == 0 || 99 strcmp(ca->ca_name, "ata0") == 0 || 100 strcmp(ca->ca_name, "ide") == 0) 101 return 1; 102 103 bzero(compat, sizeof(compat)); 104 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 105 if (strcmp(compat, "heathrow-ata") == 0 || 106 strcmp(compat, "keylargo-ata") == 0) 107 return 1; 108 109 return 0; 110 } 111 112 void 113 wdc_obio_attach(parent, self, aux) 114 struct device *parent, *self; 115 void *aux; 116 { 117 struct wdc_obio_softc *sc = (void *)self; 118 struct confargs *ca = aux; 119 struct channel_softc *chp = &sc->wdc_channel; 120 int intr; 121 int use_dma = 0; 122 char path[80]; 123 124 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_DMA) { 125 if (ca->ca_nreg >= 16 || ca->ca_nintr == -1) 126 use_dma = 1; /* XXX Don't work yet. */ 127 } 128 129 if (ca->ca_nintr >= 4 && ca->ca_nreg >= 8) { 130 intr = ca->ca_intr[0]; 131 printf(" irq %d", intr); 132 } else if (ca->ca_nintr == -1) { 133 intr = WDC_DEFAULT_PIO_IRQ; 134 printf(" irq property not found; using %d", intr); 135 } else { 136 printf(": couldn't get irq property\n"); 137 return; 138 } 139 140 if (use_dma) 141 printf(": DMA transfer"); 142 143 printf("\n"); 144 145 chp->cmd_iot = chp->ctl_iot = 146 macppc_make_bus_space_tag(ca->ca_baseaddr + ca->ca_reg[0], 4); 147 148 if (bus_space_map(chp->cmd_iot, 0, WDC_REG_NPORTS, 0, &chp->cmd_ioh) || 149 bus_space_subregion(chp->cmd_iot, chp->cmd_ioh, 150 WDC_AUXREG_OFFSET, 1, &chp->ctl_ioh)) { 151 printf("%s: couldn't map registers\n", 152 sc->sc_wdcdev.sc_dev.dv_xname); 153 return; 154 } 155 #if 0 156 chp->data32iot = chp->cmd_iot; 157 chp->data32ioh = chp->cmd_ioh; 158 #endif 159 160 sc->sc_ih = intr_establish(intr, IST_LEVEL, IPL_BIO, wdcintr, chp); 161 162 if (use_dma) { 163 sc->sc_dmacmd = dbdma_alloc(sizeof(dbdma_command_t) * 20); 164 sc->sc_dmareg = mapiodev(ca->ca_baseaddr + ca->ca_reg[2], 165 ca->ca_reg[3]); 166 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 167 } 168 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 169 sc->sc_wdcdev.PIO_cap = 0; 170 sc->wdc_chanptr = chp; 171 sc->sc_wdcdev.channels = &sc->wdc_chanptr; 172 sc->sc_wdcdev.nchannels = 1; 173 sc->sc_wdcdev.dma_arg = sc; 174 sc->sc_wdcdev.dma_init = wdc_obio_dma_init; 175 sc->sc_wdcdev.dma_start = wdc_obio_dma_start; 176 sc->sc_wdcdev.dma_finish = wdc_obio_dma_finish; 177 chp->channel = 0; 178 chp->wdc = &sc->sc_wdcdev; 179 chp->ch_queue = malloc(sizeof(struct channel_queue), 180 M_DEVBUF, M_NOWAIT); 181 if (chp->ch_queue == NULL) { 182 printf("%s: can't allocate memory for command queue", 183 sc->sc_wdcdev.sc_dev.dv_xname); 184 return; 185 } 186 187 #define OHARE_FEATURE_REG 0xf3000038 188 189 /* XXX Enable wdc1 by feature reg. */ 190 bzero(path, sizeof(path)); 191 OF_package_to_path(ca->ca_node, path, sizeof(path)); 192 if (strcmp(path, "/bandit@F2000000/ohare@10/ata@21000") == 0) { 193 u_int x; 194 195 x = in32rb(OHARE_FEATURE_REG); 196 x |= 8; 197 out32rb(OHARE_FEATURE_REG, x); 198 } 199 200 wdcattach(chp); 201 } 202 203 int 204 wdc_obio_detach(self, flags) 205 struct device *self; 206 int flags; 207 { 208 struct wdc_obio_softc *sc = (void *)self; 209 struct channel_softc *chp = &sc->wdc_channel; 210 int error; 211 212 if ((error = wdcdetach(self, flags)) != 0) 213 return error; 214 215 intr_disestablish(sc->sc_ih); 216 217 free(sc->wdc_channel.ch_queue, M_DEVBUF); 218 219 /* Unmap our i/o space. */ 220 bus_space_unmap(chp->cmd_iot, chp->cmd_ioh, WDC_REG_NPORTS); 221 222 /* Unmap DMA registers. */ 223 /* XXX unmapiodev(sc->sc_dmareg); */ 224 /* XXX free(sc->sc_dmacmd); */ 225 226 return 0; 227 } 228 229 static int 230 wdc_obio_dma_init(v, channel, drive, databuf, datalen, read) 231 void *v; 232 void *databuf; 233 size_t datalen; 234 int read; 235 { 236 struct wdc_obio_softc *sc = v; 237 vaddr_t va = (vaddr_t)databuf; 238 dbdma_command_t *cmdp; 239 u_int cmd, offset; 240 241 cmdp = sc->sc_dmacmd; 242 cmd = read ? DBDMA_CMD_IN_MORE : DBDMA_CMD_OUT_MORE; 243 244 offset = va & PGOFSET; 245 246 /* if va is not page-aligned, setup the first page */ 247 if (offset != 0) { 248 int rest = NBPG - offset; /* the rest of the page */ 249 250 if (datalen > rest) { /* if continues to next page */ 251 DBDMA_BUILD(cmdp, cmd, 0, rest, vtophys(va), 252 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, 253 DBDMA_BRANCH_NEVER); 254 datalen -= rest; 255 va += rest; 256 cmdp++; 257 } 258 } 259 260 /* now va is page-aligned */ 261 while (datalen > NBPG) { 262 DBDMA_BUILD(cmdp, cmd, 0, NBPG, vtophys(va), 263 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 264 datalen -= NBPG; 265 va += NBPG; 266 cmdp++; 267 } 268 269 /* the last page (datalen <= NBPG here) */ 270 cmd = read ? DBDMA_CMD_IN_LAST : DBDMA_CMD_OUT_LAST; 271 DBDMA_BUILD(cmdp, cmd, 0, datalen, vtophys(va), 272 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 273 cmdp++; 274 275 DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0, 276 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 277 278 return 0; 279 } 280 281 static void 282 wdc_obio_dma_start(v, channel, drive, read) 283 void *v; 284 int channel, drive; 285 { 286 struct wdc_obio_softc *sc = v; 287 288 dbdma_start(sc->sc_dmareg, sc->sc_dmacmd); 289 } 290 291 static int 292 wdc_obio_dma_finish(v, channel, drive, read) 293 void *v; 294 int channel, drive; 295 int read; 296 { 297 struct wdc_obio_softc *sc = v; 298 299 dbdma_stop(sc->sc_dmareg); 300 return 0; 301 } 302
Indexes created Mon Sep 29 18:09:42 GMT 2025