zs.c revision 1.18.6.5 1 1.18.6.5 nathanw /* $NetBSD: zs.c,v 1.18.6.5 2002/09/17 21:15:38 nathanw Exp $ */
2 1.18.6.2 nathanw
3 1.18.6.2 nathanw /*
4 1.18.6.2 nathanw * Copyright (c) 1996, 1998 Bill Studenmund
5 1.18.6.2 nathanw * Copyright (c) 1995 Gordon W. Ross
6 1.18.6.2 nathanw * All rights reserved.
7 1.18.6.2 nathanw *
8 1.18.6.2 nathanw * Redistribution and use in source and binary forms, with or without
9 1.18.6.2 nathanw * modification, are permitted provided that the following conditions
10 1.18.6.2 nathanw * are met:
11 1.18.6.2 nathanw * 1. Redistributions of source code must retain the above copyright
12 1.18.6.2 nathanw * notice, this list of conditions and the following disclaimer.
13 1.18.6.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
14 1.18.6.2 nathanw * notice, this list of conditions and the following disclaimer in the
15 1.18.6.2 nathanw * documentation and/or other materials provided with the distribution.
16 1.18.6.2 nathanw * 3. The name of the author may not be used to endorse or promote products
17 1.18.6.2 nathanw * derived from this software without specific prior written permission.
18 1.18.6.2 nathanw * 4. All advertising materials mentioning features or use of this software
19 1.18.6.2 nathanw * must display the following acknowledgement:
20 1.18.6.2 nathanw * This product includes software developed by Gordon Ross
21 1.18.6.2 nathanw *
22 1.18.6.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.18.6.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.18.6.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.18.6.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.18.6.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.18.6.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.18.6.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.18.6.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.18.6.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.18.6.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.18.6.2 nathanw */
33 1.18.6.2 nathanw
34 1.18.6.2 nathanw /*
35 1.18.6.2 nathanw * Zilog Z8530 Dual UART driver (machine-dependent part)
36 1.18.6.2 nathanw *
37 1.18.6.2 nathanw * Runs two serial lines per chip using slave drivers.
38 1.18.6.2 nathanw * Plain tty/async lines use the zs_async slave.
39 1.18.6.2 nathanw * Sun keyboard/mouse uses the zs_kbd/zs_ms slaves.
40 1.18.6.2 nathanw * Other ports use their own mice & keyboard slaves.
41 1.18.6.2 nathanw *
42 1.18.6.2 nathanw * Credits & history:
43 1.18.6.2 nathanw *
44 1.18.6.2 nathanw * With NetBSD 1.1, port-mac68k started using a port of the port-sparc
45 1.18.6.2 nathanw * (port-sun3?) zs.c driver (which was in turn based on code in the
46 1.18.6.2 nathanw * Berkeley 4.4 Lite release). Bill Studenmund did the port, with
47 1.18.6.2 nathanw * help from Allen Briggs and Gordon Ross <gwr (at) netbsd.org>. Noud de
48 1.18.6.2 nathanw * Brouwer field-tested the driver at a local ISP.
49 1.18.6.2 nathanw *
50 1.18.6.2 nathanw * Bill Studenmund and Gordon Ross then ported the machine-independant
51 1.18.6.2 nathanw * z8530 driver to work with port-mac68k. NetBSD 1.2 contained an
52 1.18.6.2 nathanw * intermediate version (mac68k using a local, patched version of
53 1.18.6.2 nathanw * the m.i. drivers), with NetBSD 1.3 containing a full version.
54 1.18.6.2 nathanw */
55 1.18.6.2 nathanw
56 1.18.6.2 nathanw #include "opt_ddb.h"
57 1.18.6.2 nathanw #include "opt_kgdb.h"
58 1.18.6.2 nathanw
59 1.18.6.2 nathanw #include <sys/param.h>
60 1.18.6.2 nathanw #include <sys/systm.h>
61 1.18.6.2 nathanw #include <sys/proc.h>
62 1.18.6.2 nathanw #include <sys/device.h>
63 1.18.6.2 nathanw #include <sys/conf.h>
64 1.18.6.2 nathanw #include <sys/file.h>
65 1.18.6.2 nathanw #include <sys/ioctl.h>
66 1.18.6.2 nathanw #include <sys/tty.h>
67 1.18.6.2 nathanw #include <sys/time.h>
68 1.18.6.2 nathanw #include <sys/kernel.h>
69 1.18.6.2 nathanw #include <sys/syslog.h>
70 1.18.6.2 nathanw #ifdef KGDB
71 1.18.6.2 nathanw #include <sys/kgdb.h>
72 1.18.6.2 nathanw #endif
73 1.18.6.2 nathanw
74 1.18.6.2 nathanw #include <dev/cons.h>
75 1.18.6.2 nathanw #include <dev/ofw/openfirm.h>
76 1.18.6.2 nathanw #include <dev/ic/z8530reg.h>
77 1.18.6.2 nathanw
78 1.18.6.2 nathanw #include <machine/z8530var.h>
79 1.18.6.2 nathanw #include <machine/autoconf.h>
80 1.18.6.2 nathanw #include <machine/cpu.h>
81 1.18.6.2 nathanw #include <machine/pio.h>
82 1.18.6.2 nathanw
83 1.18.6.2 nathanw /* Are these in a header file anywhere? */
84 1.18.6.2 nathanw /* Booter flags interface */
85 1.18.6.2 nathanw #define ZSMAC_RAW 0x01
86 1.18.6.2 nathanw #define ZSMAC_LOCALTALK 0x02
87 1.18.6.2 nathanw
88 1.18.6.2 nathanw #include "zsc.h" /* get the # of zs chips defined */
89 1.18.6.2 nathanw
90 1.18.6.2 nathanw /*
91 1.18.6.2 nathanw * Some warts needed by z8530tty.c -
92 1.18.6.2 nathanw */
93 1.18.6.2 nathanw int zs_def_cflag = (CREAD | CS8 | HUPCL);
94 1.18.6.2 nathanw
95 1.18.6.2 nathanw /*
96 1.18.6.2 nathanw * abort detection on console will now timeout after iterating on a loop
97 1.18.6.2 nathanw * the following # of times. Cheep hack. Also, abort detection is turned
98 1.18.6.2 nathanw * off after a timeout (i.e. maybe there's not a terminal hooked up).
99 1.18.6.2 nathanw */
100 1.18.6.2 nathanw #define ZSABORT_DELAY 3000000
101 1.18.6.2 nathanw
102 1.18.6.2 nathanw struct zsdevice {
103 1.18.6.2 nathanw /* Yes, they are backwards. */
104 1.18.6.2 nathanw struct zschan zs_chan_b;
105 1.18.6.2 nathanw struct zschan zs_chan_a;
106 1.18.6.2 nathanw };
107 1.18.6.2 nathanw
108 1.18.6.2 nathanw /* Flags from cninit() */
109 1.18.6.2 nathanw static int zs_hwflags[NZSC][2];
110 1.18.6.2 nathanw /* Default speed for each channel */
111 1.18.6.2 nathanw static int zs_defspeed[NZSC][2] = {
112 1.18.6.2 nathanw { 38400, /* tty00 */
113 1.18.6.2 nathanw 38400 }, /* tty01 */
114 1.18.6.2 nathanw };
115 1.18.6.2 nathanw
116 1.18.6.2 nathanw /* console stuff */
117 1.18.6.2 nathanw void *zs_conschan = 0;
118 1.18.6.2 nathanw #ifdef ZS_CONSOLE_ABORT
119 1.18.6.2 nathanw int zs_cons_canabort = 1;
120 1.18.6.2 nathanw #else
121 1.18.6.2 nathanw int zs_cons_canabort = 0;
122 1.18.6.2 nathanw #endif /* ZS_CONSOLE_ABORT*/
123 1.18.6.2 nathanw
124 1.18.6.2 nathanw /* device to which the console is attached--if serial. */
125 1.18.6.2 nathanw /* Mac stuff */
126 1.18.6.2 nathanw
127 1.18.6.2 nathanw static int zs_get_speed __P((struct zs_chanstate *));
128 1.18.6.2 nathanw
129 1.18.6.2 nathanw /*
130 1.18.6.2 nathanw * Even though zsparam will set up the clock multiples, etc., we
131 1.18.6.2 nathanw * still set them here as: 1) mice & keyboards don't use zsparam,
132 1.18.6.2 nathanw * and 2) the console stuff uses these defaults before device
133 1.18.6.2 nathanw * attach.
134 1.18.6.2 nathanw */
135 1.18.6.2 nathanw
136 1.18.6.2 nathanw static u_char zs_init_reg[16] = {
137 1.18.6.2 nathanw 0, /* 0: CMD (reset, etc.) */
138 1.18.6.2 nathanw 0, /* 1: No interrupts yet. */
139 1.18.6.2 nathanw 0, /* IVECT */
140 1.18.6.2 nathanw ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
141 1.18.6.2 nathanw ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
142 1.18.6.2 nathanw ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
143 1.18.6.2 nathanw 0, /* 6: TXSYNC/SYNCLO */
144 1.18.6.2 nathanw 0, /* 7: RXSYNC/SYNCHI */
145 1.18.6.2 nathanw 0, /* 8: alias for data port */
146 1.18.6.2 nathanw ZSWR9_MASTER_IE,
147 1.18.6.2 nathanw 0, /*10: Misc. TX/RX control bits */
148 1.18.6.2 nathanw ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
149 1.18.6.2 nathanw ((PCLK/32)/38400)-2, /*12: BAUDLO (default=38400) */
150 1.18.6.2 nathanw 0, /*13: BAUDHI (default=38400) */
151 1.18.6.2 nathanw ZSWR14_BAUD_ENA,
152 1.18.6.2 nathanw ZSWR15_BREAK_IE,
153 1.18.6.2 nathanw };
154 1.18.6.2 nathanw
155 1.18.6.2 nathanw /****************************************************************
156 1.18.6.2 nathanw * Autoconfig
157 1.18.6.2 nathanw ****************************************************************/
158 1.18.6.2 nathanw
159 1.18.6.2 nathanw /* Definition of the driver for autoconfig. */
160 1.18.6.2 nathanw static int zsc_match __P((struct device *, struct cfdata *, void *));
161 1.18.6.2 nathanw static void zsc_attach __P((struct device *, struct device *, void *));
162 1.18.6.2 nathanw static int zsc_print __P((void *, const char *name));
163 1.18.6.2 nathanw
164 1.18.6.2 nathanw struct cfattach zsc_ca = {
165 1.18.6.2 nathanw sizeof(struct zsc_softc), zsc_match, zsc_attach
166 1.18.6.2 nathanw };
167 1.18.6.2 nathanw
168 1.18.6.2 nathanw extern struct cfdriver zsc_cd;
169 1.18.6.2 nathanw
170 1.18.6.2 nathanw int zshard __P((void *));
171 1.18.6.2 nathanw int zssoft __P((void *));
172 1.18.6.2 nathanw #ifdef ZS_TXDMA
173 1.18.6.2 nathanw static int zs_txdma_int __P((void *));
174 1.18.6.2 nathanw #endif
175 1.18.6.2 nathanw
176 1.18.6.2 nathanw void zscnprobe __P((struct consdev *));
177 1.18.6.2 nathanw void zscninit __P((struct consdev *));
178 1.18.6.2 nathanw int zscngetc __P((dev_t));
179 1.18.6.2 nathanw void zscnputc __P((dev_t, int));
180 1.18.6.2 nathanw void zscnpollc __P((dev_t, int));
181 1.18.6.2 nathanw
182 1.18.6.2 nathanw /*
183 1.18.6.2 nathanw * Is the zs chip present?
184 1.18.6.2 nathanw */
185 1.18.6.2 nathanw static int
186 1.18.6.2 nathanw zsc_match(parent, cf, aux)
187 1.18.6.2 nathanw struct device *parent;
188 1.18.6.2 nathanw struct cfdata *cf;
189 1.18.6.2 nathanw void *aux;
190 1.18.6.2 nathanw {
191 1.18.6.2 nathanw struct confargs *ca = aux;
192 1.18.6.2 nathanw int unit = cf->cf_unit;
193 1.18.6.2 nathanw
194 1.18.6.2 nathanw if (strcmp(ca->ca_name, "escc") != 0)
195 1.18.6.2 nathanw return 0;
196 1.18.6.2 nathanw
197 1.18.6.2 nathanw if (unit > 1)
198 1.18.6.2 nathanw return 0;
199 1.18.6.2 nathanw
200 1.18.6.2 nathanw return 1;
201 1.18.6.2 nathanw }
202 1.18.6.2 nathanw
203 1.18.6.2 nathanw /*
204 1.18.6.2 nathanw * Attach a found zs.
205 1.18.6.2 nathanw *
206 1.18.6.2 nathanw * Match slave number to zs unit number, so that misconfiguration will
207 1.18.6.2 nathanw * not set up the keyboard as ttya, etc.
208 1.18.6.2 nathanw */
209 1.18.6.2 nathanw static void
210 1.18.6.2 nathanw zsc_attach(parent, self, aux)
211 1.18.6.2 nathanw struct device *parent;
212 1.18.6.2 nathanw struct device *self;
213 1.18.6.2 nathanw void *aux;
214 1.18.6.2 nathanw {
215 1.18.6.2 nathanw struct zsc_softc *zsc = (void *)self;
216 1.18.6.2 nathanw struct confargs *ca = aux;
217 1.18.6.2 nathanw struct zsc_attach_args zsc_args;
218 1.18.6.2 nathanw volatile struct zschan *zc;
219 1.18.6.2 nathanw struct xzs_chanstate *xcs;
220 1.18.6.2 nathanw struct zs_chanstate *cs;
221 1.18.6.2 nathanw struct zsdevice *zsd;
222 1.18.6.2 nathanw int zsc_unit, channel;
223 1.18.6.2 nathanw int s, chip, theflags;
224 1.18.6.2 nathanw int node, intr[2][3];
225 1.18.6.2 nathanw u_int regs[6];
226 1.18.6.2 nathanw
227 1.18.6.2 nathanw chip = 0;
228 1.18.6.2 nathanw zsc_unit = zsc->zsc_dev.dv_unit;
229 1.18.6.2 nathanw
230 1.18.6.2 nathanw ca->ca_reg[0] += ca->ca_baseaddr;
231 1.18.6.2 nathanw zsd = mapiodev(ca->ca_reg[0], ca->ca_reg[1]);
232 1.18.6.2 nathanw
233 1.18.6.2 nathanw node = OF_child(ca->ca_node); /* ch-a */
234 1.18.6.2 nathanw
235 1.18.6.2 nathanw for (channel = 0; channel < 2; channel++) {
236 1.18.6.2 nathanw if (OF_getprop(node, "AAPL,interrupts",
237 1.18.6.2 nathanw intr[channel], sizeof(intr[0])) == -1 &&
238 1.18.6.2 nathanw OF_getprop(node, "interrupts",
239 1.18.6.2 nathanw intr[channel], sizeof(intr[0])) == -1) {
240 1.18.6.2 nathanw printf(": cannot find interrupt property\n");
241 1.18.6.2 nathanw return;
242 1.18.6.2 nathanw }
243 1.18.6.2 nathanw
244 1.18.6.2 nathanw if (OF_getprop(node, "reg", regs, sizeof(regs)) < 24) {
245 1.18.6.2 nathanw printf(": cannot find reg property\n");
246 1.18.6.2 nathanw return;
247 1.18.6.2 nathanw }
248 1.18.6.2 nathanw regs[2] += ca->ca_baseaddr;
249 1.18.6.2 nathanw regs[4] += ca->ca_baseaddr;
250 1.18.6.2 nathanw #ifdef ZS_TXDMA
251 1.18.6.2 nathanw zsc->zsc_txdmareg[channel] = mapiodev(regs[2], regs[3]);
252 1.18.6.2 nathanw zsc->zsc_txdmacmd[channel] =
253 1.18.6.2 nathanw dbdma_alloc(sizeof(dbdma_command_t) * 3);
254 1.18.6.2 nathanw memset(zsc->zsc_txdmacmd[channel], 0,
255 1.18.6.2 nathanw sizeof(dbdma_command_t) * 3);
256 1.18.6.2 nathanw dbdma_reset(zsc->zsc_txdmareg[channel]);
257 1.18.6.2 nathanw #endif
258 1.18.6.2 nathanw node = OF_peer(node); /* ch-b */
259 1.18.6.2 nathanw }
260 1.18.6.2 nathanw
261 1.18.6.2 nathanw printf(": irq %d,%d\n", intr[0][0], intr[1][0]);
262 1.18.6.2 nathanw
263 1.18.6.2 nathanw /*
264 1.18.6.2 nathanw * Initialize software state for each channel.
265 1.18.6.2 nathanw */
266 1.18.6.2 nathanw for (channel = 0; channel < 2; channel++) {
267 1.18.6.2 nathanw zsc_args.channel = channel;
268 1.18.6.2 nathanw zsc_args.hwflags = zs_hwflags[zsc_unit][channel];
269 1.18.6.2 nathanw xcs = &zsc->xzsc_xcs_store[channel];
270 1.18.6.2 nathanw cs = &xcs->xzs_cs;
271 1.18.6.2 nathanw zsc->zsc_cs[channel] = cs;
272 1.18.6.2 nathanw
273 1.18.6.2 nathanw cs->cs_channel = channel;
274 1.18.6.2 nathanw cs->cs_private = NULL;
275 1.18.6.2 nathanw cs->cs_ops = &zsops_null;
276 1.18.6.2 nathanw
277 1.18.6.2 nathanw zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b;
278 1.18.6.2 nathanw
279 1.18.6.2 nathanw cs->cs_reg_csr = &zc->zc_csr;
280 1.18.6.2 nathanw cs->cs_reg_data = &zc->zc_data;
281 1.18.6.2 nathanw
282 1.18.6.2 nathanw memcpy(cs->cs_creg, zs_init_reg, 16);
283 1.18.6.2 nathanw memcpy(cs->cs_preg, zs_init_reg, 16);
284 1.18.6.2 nathanw
285 1.18.6.2 nathanw /* Current BAUD rate generator clock. */
286 1.18.6.2 nathanw cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */
287 1.18.6.2 nathanw if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE)
288 1.18.6.2 nathanw cs->cs_defspeed = zs_get_speed(cs);
289 1.18.6.2 nathanw else
290 1.18.6.2 nathanw cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
291 1.18.6.2 nathanw cs->cs_defcflag = zs_def_cflag;
292 1.18.6.2 nathanw
293 1.18.6.2 nathanw /* Make these correspond to cs_defcflag (-crtscts) */
294 1.18.6.2 nathanw cs->cs_rr0_dcd = ZSRR0_DCD;
295 1.18.6.2 nathanw cs->cs_rr0_cts = 0;
296 1.18.6.2 nathanw cs->cs_wr5_dtr = ZSWR5_DTR;
297 1.18.6.2 nathanw cs->cs_wr5_rts = 0;
298 1.18.6.2 nathanw
299 1.18.6.2 nathanw #ifdef __notyet__
300 1.18.6.2 nathanw cs->cs_slave_type = ZS_SLAVE_NONE;
301 1.18.6.2 nathanw #endif
302 1.18.6.2 nathanw
303 1.18.6.2 nathanw /* Define BAUD rate stuff. */
304 1.18.6.2 nathanw xcs->cs_clocks[0].clk = PCLK;
305 1.18.6.2 nathanw xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV;
306 1.18.6.2 nathanw xcs->cs_clocks[1].flags =
307 1.18.6.2 nathanw ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN;
308 1.18.6.2 nathanw xcs->cs_clocks[2].flags = ZSC_TRXDIV | ZSC_VARIABLE;
309 1.18.6.2 nathanw xcs->cs_clock_count = 3;
310 1.18.6.2 nathanw if (channel == 0) {
311 1.18.6.2 nathanw theflags = 0; /*mac68k_machine.modem_flags;*/
312 1.18.6.2 nathanw /*xcs->cs_clocks[1].clk = mac68k_machine.modem_dcd_clk;*/
313 1.18.6.2 nathanw /*xcs->cs_clocks[2].clk = mac68k_machine.modem_cts_clk;*/
314 1.18.6.2 nathanw xcs->cs_clocks[1].clk = 0;
315 1.18.6.2 nathanw xcs->cs_clocks[2].clk = 0;
316 1.18.6.2 nathanw } else {
317 1.18.6.2 nathanw theflags = 0; /*mac68k_machine.print_flags;*/
318 1.18.6.2 nathanw xcs->cs_clocks[1].flags = ZSC_VARIABLE;
319 1.18.6.2 nathanw /*
320 1.18.6.2 nathanw * Yes, we aren't defining ANY clock source enables for the
321 1.18.6.2 nathanw * printer's DCD clock in. The hardware won't let us
322 1.18.6.2 nathanw * use it. But a clock will freak out the chip, so we
323 1.18.6.2 nathanw * let you set it, telling us to bar interrupts on the line.
324 1.18.6.2 nathanw */
325 1.18.6.2 nathanw /*xcs->cs_clocks[1].clk = mac68k_machine.print_dcd_clk;*/
326 1.18.6.2 nathanw /*xcs->cs_clocks[2].clk = mac68k_machine.print_cts_clk;*/
327 1.18.6.2 nathanw xcs->cs_clocks[1].clk = 0;
328 1.18.6.2 nathanw xcs->cs_clocks[2].clk = 0;
329 1.18.6.2 nathanw }
330 1.18.6.2 nathanw if (xcs->cs_clocks[1].clk)
331 1.18.6.2 nathanw zsc_args.hwflags |= ZS_HWFLAG_NO_DCD;
332 1.18.6.2 nathanw if (xcs->cs_clocks[2].clk)
333 1.18.6.2 nathanw zsc_args.hwflags |= ZS_HWFLAG_NO_CTS;
334 1.18.6.2 nathanw
335 1.18.6.2 nathanw /* Set defaults in our "extended" chanstate. */
336 1.18.6.2 nathanw xcs->cs_csource = 0;
337 1.18.6.2 nathanw xcs->cs_psource = 0;
338 1.18.6.2 nathanw xcs->cs_cclk_flag = 0; /* Nothing fancy by default */
339 1.18.6.2 nathanw xcs->cs_pclk_flag = 0;
340 1.18.6.2 nathanw
341 1.18.6.2 nathanw if (theflags & ZSMAC_RAW) {
342 1.18.6.2 nathanw zsc_args.hwflags |= ZS_HWFLAG_RAW;
343 1.18.6.2 nathanw printf(" (raw defaults)");
344 1.18.6.2 nathanw }
345 1.18.6.2 nathanw
346 1.18.6.2 nathanw /*
347 1.18.6.2 nathanw * XXX - This might be better done with a "stub" driver
348 1.18.6.2 nathanw * (to replace zstty) that ignores LocalTalk for now.
349 1.18.6.2 nathanw */
350 1.18.6.2 nathanw if (theflags & ZSMAC_LOCALTALK) {
351 1.18.6.2 nathanw printf(" shielding from LocalTalk");
352 1.18.6.2 nathanw cs->cs_defspeed = 1;
353 1.18.6.2 nathanw cs->cs_creg[ZSRR_BAUDLO] = cs->cs_preg[ZSRR_BAUDLO] = 0xff;
354 1.18.6.2 nathanw cs->cs_creg[ZSRR_BAUDHI] = cs->cs_preg[ZSRR_BAUDHI] = 0xff;
355 1.18.6.2 nathanw zs_write_reg(cs, ZSRR_BAUDLO, 0xff);
356 1.18.6.2 nathanw zs_write_reg(cs, ZSRR_BAUDHI, 0xff);
357 1.18.6.2 nathanw /*
358 1.18.6.2 nathanw * If we might have LocalTalk, then make sure we have the
359 1.18.6.2 nathanw * Baud rate low-enough to not do any damage.
360 1.18.6.2 nathanw */
361 1.18.6.2 nathanw }
362 1.18.6.2 nathanw
363 1.18.6.2 nathanw /*
364 1.18.6.2 nathanw * We used to disable chip interrupts here, but we now
365 1.18.6.2 nathanw * do that in zscnprobe, just in case MacOS left the chip on.
366 1.18.6.2 nathanw */
367 1.18.6.2 nathanw
368 1.18.6.2 nathanw xcs->cs_chip = chip;
369 1.18.6.2 nathanw
370 1.18.6.2 nathanw /* Stash away a copy of the final H/W flags. */
371 1.18.6.2 nathanw xcs->cs_hwflags = zsc_args.hwflags;
372 1.18.6.2 nathanw
373 1.18.6.2 nathanw /*
374 1.18.6.2 nathanw * Look for a child driver for this channel.
375 1.18.6.2 nathanw * The child attach will setup the hardware.
376 1.18.6.2 nathanw */
377 1.18.6.2 nathanw if (!config_found(self, (void *)&zsc_args, zsc_print)) {
378 1.18.6.2 nathanw /* No sub-driver. Just reset it. */
379 1.18.6.2 nathanw u_char reset = (channel == 0) ?
380 1.18.6.2 nathanw ZSWR9_A_RESET : ZSWR9_B_RESET;
381 1.18.6.2 nathanw s = splzs();
382 1.18.6.2 nathanw zs_write_reg(cs, 9, reset);
383 1.18.6.2 nathanw splx(s);
384 1.18.6.2 nathanw }
385 1.18.6.2 nathanw }
386 1.18.6.2 nathanw
387 1.18.6.2 nathanw /* XXX - Now safe to install interrupt handlers. */
388 1.18.6.2 nathanw intr_establish(intr[0][0], IST_LEVEL, IPL_TTY, zshard, NULL);
389 1.18.6.2 nathanw intr_establish(intr[1][0], IST_LEVEL, IPL_TTY, zshard, NULL);
390 1.18.6.2 nathanw #ifdef ZS_TXDMA
391 1.18.6.2 nathanw intr_establish(intr[0][1], IST_LEVEL, IPL_TTY, zs_txdma_int, (void *)0);
392 1.18.6.2 nathanw intr_establish(intr[1][1], IST_LEVEL, IPL_TTY, zs_txdma_int, (void *)1);
393 1.18.6.2 nathanw #endif
394 1.18.6.2 nathanw
395 1.18.6.2 nathanw /*
396 1.18.6.2 nathanw * Set the master interrupt enable and interrupt vector.
397 1.18.6.2 nathanw * (common to both channels, do it on A)
398 1.18.6.2 nathanw */
399 1.18.6.2 nathanw cs = zsc->zsc_cs[0];
400 1.18.6.2 nathanw s = splzs();
401 1.18.6.2 nathanw /* interrupt vector */
402 1.18.6.2 nathanw zs_write_reg(cs, 2, zs_init_reg[2]);
403 1.18.6.2 nathanw /* master interrupt control (enable) */
404 1.18.6.2 nathanw zs_write_reg(cs, 9, zs_init_reg[9]);
405 1.18.6.2 nathanw splx(s);
406 1.18.6.2 nathanw }
407 1.18.6.2 nathanw
408 1.18.6.2 nathanw static int
409 1.18.6.2 nathanw zsc_print(aux, name)
410 1.18.6.2 nathanw void *aux;
411 1.18.6.2 nathanw const char *name;
412 1.18.6.2 nathanw {
413 1.18.6.2 nathanw struct zsc_attach_args *args = aux;
414 1.18.6.2 nathanw
415 1.18.6.2 nathanw if (name != NULL)
416 1.18.6.2 nathanw printf("%s: ", name);
417 1.18.6.2 nathanw
418 1.18.6.2 nathanw if (args->channel != -1)
419 1.18.6.2 nathanw printf(" channel %d", args->channel);
420 1.18.6.2 nathanw
421 1.18.6.2 nathanw return UNCONF;
422 1.18.6.2 nathanw }
423 1.18.6.2 nathanw
424 1.18.6.2 nathanw int
425 1.18.6.2 nathanw zsmdioctl(cs, cmd, data)
426 1.18.6.2 nathanw struct zs_chanstate *cs;
427 1.18.6.2 nathanw u_long cmd;
428 1.18.6.2 nathanw caddr_t data;
429 1.18.6.2 nathanw {
430 1.18.6.2 nathanw switch (cmd) {
431 1.18.6.2 nathanw default:
432 1.18.6.4 nathanw return (EPASSTHROUGH);
433 1.18.6.2 nathanw }
434 1.18.6.2 nathanw return (0);
435 1.18.6.2 nathanw }
436 1.18.6.2 nathanw
437 1.18.6.2 nathanw void
438 1.18.6.2 nathanw zsmd_setclock(cs)
439 1.18.6.2 nathanw struct zs_chanstate *cs;
440 1.18.6.2 nathanw {
441 1.18.6.2 nathanw #ifdef NOTYET
442 1.18.6.2 nathanw struct xzs_chanstate *xcs = (void *)cs;
443 1.18.6.2 nathanw
444 1.18.6.2 nathanw if (cs->cs_channel != 0)
445 1.18.6.2 nathanw return;
446 1.18.6.2 nathanw
447 1.18.6.2 nathanw /*
448 1.18.6.2 nathanw * If the new clock has the external bit set, then select the
449 1.18.6.2 nathanw * external source.
450 1.18.6.2 nathanw */
451 1.18.6.2 nathanw via_set_modem((xcs->cs_pclk_flag & ZSC_EXTERN) ? 1 : 0);
452 1.18.6.2 nathanw #endif
453 1.18.6.2 nathanw }
454 1.18.6.2 nathanw
455 1.18.6.2 nathanw static int zssoftpending;
456 1.18.6.2 nathanw
457 1.18.6.2 nathanw /*
458 1.18.6.2 nathanw * Our ZS chips all share a common, autovectored interrupt,
459 1.18.6.2 nathanw * so we have to look at all of them on each interrupt.
460 1.18.6.2 nathanw */
461 1.18.6.2 nathanw int
462 1.18.6.2 nathanw zshard(arg)
463 1.18.6.2 nathanw void *arg;
464 1.18.6.2 nathanw {
465 1.18.6.2 nathanw register struct zsc_softc *zsc;
466 1.18.6.2 nathanw register int unit, rval;
467 1.18.6.2 nathanw
468 1.18.6.2 nathanw rval = 0;
469 1.18.6.2 nathanw for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
470 1.18.6.2 nathanw zsc = zsc_cd.cd_devs[unit];
471 1.18.6.2 nathanw if (zsc == NULL)
472 1.18.6.2 nathanw continue;
473 1.18.6.2 nathanw rval |= zsc_intr_hard(zsc);
474 1.18.6.2 nathanw if ((zsc->zsc_cs[0]->cs_softreq) ||
475 1.18.6.2 nathanw (zsc->zsc_cs[1]->cs_softreq))
476 1.18.6.2 nathanw {
477 1.18.6.2 nathanw /* zsc_req_softint(zsc); */
478 1.18.6.2 nathanw /* We are at splzs here, so no need to lock. */
479 1.18.6.2 nathanw if (zssoftpending == 0) {
480 1.18.6.2 nathanw zssoftpending = 1;
481 1.18.6.2 nathanw setsoftserial();
482 1.18.6.2 nathanw }
483 1.18.6.2 nathanw }
484 1.18.6.2 nathanw }
485 1.18.6.2 nathanw return (rval);
486 1.18.6.2 nathanw }
487 1.18.6.2 nathanw
488 1.18.6.2 nathanw /*
489 1.18.6.2 nathanw * Similar scheme as for zshard (look at all of them)
490 1.18.6.2 nathanw */
491 1.18.6.2 nathanw int
492 1.18.6.2 nathanw zssoft(arg)
493 1.18.6.2 nathanw void *arg;
494 1.18.6.2 nathanw {
495 1.18.6.2 nathanw register struct zsc_softc *zsc;
496 1.18.6.2 nathanw register int unit;
497 1.18.6.2 nathanw
498 1.18.6.2 nathanw /* This is not the only ISR on this IPL. */
499 1.18.6.2 nathanw if (zssoftpending == 0)
500 1.18.6.2 nathanw return (0);
501 1.18.6.2 nathanw
502 1.18.6.2 nathanw /*
503 1.18.6.2 nathanw * The soft intr. bit will be set by zshard only if
504 1.18.6.2 nathanw * the variable zssoftpending is zero.
505 1.18.6.2 nathanw */
506 1.18.6.2 nathanw zssoftpending = 0;
507 1.18.6.2 nathanw
508 1.18.6.2 nathanw for (unit = 0; unit < zsc_cd.cd_ndevs; ++unit) {
509 1.18.6.2 nathanw zsc = zsc_cd.cd_devs[unit];
510 1.18.6.2 nathanw if (zsc == NULL)
511 1.18.6.2 nathanw continue;
512 1.18.6.2 nathanw (void) zsc_intr_soft(zsc);
513 1.18.6.2 nathanw }
514 1.18.6.2 nathanw return (1);
515 1.18.6.2 nathanw }
516 1.18.6.2 nathanw
517 1.18.6.2 nathanw #ifdef ZS_TXDMA
518 1.18.6.2 nathanw int
519 1.18.6.2 nathanw zs_txdma_int(arg)
520 1.18.6.2 nathanw void *arg;
521 1.18.6.2 nathanw {
522 1.18.6.2 nathanw int ch = (int)arg;
523 1.18.6.2 nathanw struct zsc_softc *zsc;
524 1.18.6.2 nathanw struct zs_chanstate *cs;
525 1.18.6.2 nathanw int unit = 0; /* XXX */
526 1.18.6.2 nathanw extern int zstty_txdma_int();
527 1.18.6.2 nathanw
528 1.18.6.2 nathanw zsc = zsc_cd.cd_devs[unit];
529 1.18.6.2 nathanw if (zsc == NULL)
530 1.18.6.2 nathanw panic("zs_txdma_int");
531 1.18.6.2 nathanw
532 1.18.6.2 nathanw cs = zsc->zsc_cs[ch];
533 1.18.6.2 nathanw zstty_txdma_int(cs);
534 1.18.6.2 nathanw
535 1.18.6.2 nathanw if (cs->cs_softreq) {
536 1.18.6.2 nathanw if (zssoftpending == 0) {
537 1.18.6.2 nathanw zssoftpending = 1;
538 1.18.6.2 nathanw setsoftserial();
539 1.18.6.2 nathanw }
540 1.18.6.2 nathanw }
541 1.18.6.2 nathanw return 1;
542 1.18.6.2 nathanw }
543 1.18.6.2 nathanw
544 1.18.6.2 nathanw void
545 1.18.6.2 nathanw zs_dma_setup(cs, pa, len)
546 1.18.6.2 nathanw struct zs_chanstate *cs;
547 1.18.6.2 nathanw caddr_t pa;
548 1.18.6.2 nathanw int len;
549 1.18.6.2 nathanw {
550 1.18.6.2 nathanw struct zsc_softc *zsc;
551 1.18.6.2 nathanw dbdma_command_t *cmdp;
552 1.18.6.2 nathanw int ch = cs->cs_channel;
553 1.18.6.2 nathanw
554 1.18.6.2 nathanw zsc = zsc_cd.cd_devs[ch];
555 1.18.6.2 nathanw cmdp = zsc->zsc_txdmacmd[ch];
556 1.18.6.2 nathanw
557 1.18.6.2 nathanw DBDMA_BUILD(cmdp, DBDMA_CMD_OUT_LAST, 0, len, kvtop(pa),
558 1.18.6.2 nathanw DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
559 1.18.6.2 nathanw cmdp++;
560 1.18.6.2 nathanw DBDMA_BUILD(cmdp, DBDMA_CMD_STOP, 0, 0, 0,
561 1.18.6.2 nathanw DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER);
562 1.18.6.2 nathanw
563 1.18.6.2 nathanw __asm __volatile("eieio");
564 1.18.6.2 nathanw
565 1.18.6.2 nathanw dbdma_start(zsc->zsc_txdmareg[ch], zsc->zsc_txdmacmd[ch]);
566 1.18.6.2 nathanw }
567 1.18.6.2 nathanw #endif
568 1.18.6.2 nathanw
569 1.18.6.2 nathanw /*
570 1.18.6.2 nathanw * Compute the current baud rate given a ZS channel.
571 1.18.6.2 nathanw * XXX Assume internal BRG.
572 1.18.6.2 nathanw */
573 1.18.6.2 nathanw int
574 1.18.6.2 nathanw zs_get_speed(cs)
575 1.18.6.2 nathanw struct zs_chanstate *cs;
576 1.18.6.2 nathanw {
577 1.18.6.2 nathanw int tconst;
578 1.18.6.2 nathanw
579 1.18.6.2 nathanw tconst = zs_read_reg(cs, 12);
580 1.18.6.2 nathanw tconst |= zs_read_reg(cs, 13) << 8;
581 1.18.6.2 nathanw return TCONST_TO_BPS(cs->cs_brg_clk, tconst);
582 1.18.6.2 nathanw }
583 1.18.6.2 nathanw
584 1.18.6.2 nathanw #ifndef ZS_TOLERANCE
585 1.18.6.2 nathanw #define ZS_TOLERANCE 51
586 1.18.6.2 nathanw /* 5% in tenths of a %, plus 1 so that exactly 5% will be ok. */
587 1.18.6.2 nathanw #endif
588 1.18.6.2 nathanw
589 1.18.6.2 nathanw /*
590 1.18.6.2 nathanw * Search through the signal sources in the channel, and
591 1.18.6.2 nathanw * pick the best one for the baud rate requested. Return
592 1.18.6.2 nathanw * a -1 if not achievable in tolerance. Otherwise return 0
593 1.18.6.2 nathanw * and fill in the values.
594 1.18.6.2 nathanw *
595 1.18.6.2 nathanw * This routine draws inspiration from the Atari port's zs.c
596 1.18.6.2 nathanw * driver in NetBSD 1.1 which did the same type of source switching.
597 1.18.6.2 nathanw * Tolerance code inspired by comspeed routine in isa/com.c.
598 1.18.6.2 nathanw *
599 1.18.6.2 nathanw * By Bill Studenmund, 1996-05-12
600 1.18.6.2 nathanw */
601 1.18.6.2 nathanw int
602 1.18.6.2 nathanw zs_set_speed(cs, bps)
603 1.18.6.2 nathanw struct zs_chanstate *cs;
604 1.18.6.2 nathanw int bps; /* bits per second */
605 1.18.6.2 nathanw {
606 1.18.6.2 nathanw struct xzs_chanstate *xcs = (void *) cs;
607 1.18.6.2 nathanw int i, tc, tc0 = 0, tc1, s, sf = 0;
608 1.18.6.2 nathanw int src, rate0, rate1, err, tol;
609 1.18.6.2 nathanw
610 1.18.6.2 nathanw if (bps == 0)
611 1.18.6.2 nathanw return (0);
612 1.18.6.2 nathanw
613 1.18.6.2 nathanw src = -1; /* no valid source yet */
614 1.18.6.2 nathanw tol = ZS_TOLERANCE;
615 1.18.6.2 nathanw
616 1.18.6.2 nathanw /*
617 1.18.6.2 nathanw * Step through all the sources and see which one matches
618 1.18.6.2 nathanw * the best. A source has to match BETTER than tol to be chosen.
619 1.18.6.2 nathanw * Thus if two sources give the same error, the first one will be
620 1.18.6.2 nathanw * chosen. Also, allow for the possability that one source might run
621 1.18.6.2 nathanw * both the BRG and the direct divider (i.e. RTxC).
622 1.18.6.2 nathanw */
623 1.18.6.2 nathanw for (i = 0; i < xcs->cs_clock_count; i++) {
624 1.18.6.2 nathanw if (xcs->cs_clocks[i].clk <= 0)
625 1.18.6.2 nathanw continue; /* skip non-existent or bad clocks */
626 1.18.6.2 nathanw if (xcs->cs_clocks[i].flags & ZSC_BRG) {
627 1.18.6.2 nathanw /* check out BRG at /16 */
628 1.18.6.2 nathanw tc1 = BPS_TO_TCONST(xcs->cs_clocks[i].clk >> 4, bps);
629 1.18.6.2 nathanw if (tc1 >= 0) {
630 1.18.6.2 nathanw rate1 = TCONST_TO_BPS(xcs->cs_clocks[i].clk >> 4, tc1);
631 1.18.6.2 nathanw err = abs(((rate1 - bps)*1000)/bps);
632 1.18.6.2 nathanw if (err < tol) {
633 1.18.6.2 nathanw tol = err;
634 1.18.6.2 nathanw src = i;
635 1.18.6.2 nathanw sf = xcs->cs_clocks[i].flags & ~ZSC_DIV;
636 1.18.6.2 nathanw tc0 = tc1;
637 1.18.6.2 nathanw rate0 = rate1;
638 1.18.6.2 nathanw }
639 1.18.6.2 nathanw }
640 1.18.6.2 nathanw }
641 1.18.6.2 nathanw if (xcs->cs_clocks[i].flags & ZSC_DIV) {
642 1.18.6.2 nathanw /*
643 1.18.6.2 nathanw * Check out either /1, /16, /32, or /64
644 1.18.6.2 nathanw * Note: for /1, you'd better be using a synchronized
645 1.18.6.2 nathanw * clock!
646 1.18.6.2 nathanw */
647 1.18.6.2 nathanw int b0 = xcs->cs_clocks[i].clk, e0 = abs(b0-bps);
648 1.18.6.2 nathanw int b1 = b0 >> 4, e1 = abs(b1-bps);
649 1.18.6.2 nathanw int b2 = b1 >> 1, e2 = abs(b2-bps);
650 1.18.6.2 nathanw int b3 = b2 >> 1, e3 = abs(b3-bps);
651 1.18.6.2 nathanw
652 1.18.6.2 nathanw if (e0 < e1 && e0 < e2 && e0 < e3) {
653 1.18.6.2 nathanw err = e0;
654 1.18.6.2 nathanw rate1 = b0;
655 1.18.6.2 nathanw tc1 = ZSWR4_CLK_X1;
656 1.18.6.2 nathanw } else if (e0 > e1 && e1 < e2 && e1 < e3) {
657 1.18.6.2 nathanw err = e1;
658 1.18.6.2 nathanw rate1 = b1;
659 1.18.6.2 nathanw tc1 = ZSWR4_CLK_X16;
660 1.18.6.2 nathanw } else if (e0 > e2 && e1 > e2 && e2 < e3) {
661 1.18.6.2 nathanw err = e2;
662 1.18.6.2 nathanw rate1 = b2;
663 1.18.6.2 nathanw tc1 = ZSWR4_CLK_X32;
664 1.18.6.2 nathanw } else {
665 1.18.6.2 nathanw err = e3;
666 1.18.6.2 nathanw rate1 = b3;
667 1.18.6.2 nathanw tc1 = ZSWR4_CLK_X64;
668 1.18.6.2 nathanw }
669 1.18.6.2 nathanw
670 1.18.6.2 nathanw err = (err * 1000)/bps;
671 1.18.6.2 nathanw if (err < tol) {
672 1.18.6.2 nathanw tol = err;
673 1.18.6.2 nathanw src = i;
674 1.18.6.2 nathanw sf = xcs->cs_clocks[i].flags & ~ZSC_BRG;
675 1.18.6.2 nathanw tc0 = tc1;
676 1.18.6.2 nathanw rate0 = rate1;
677 1.18.6.2 nathanw }
678 1.18.6.2 nathanw }
679 1.18.6.2 nathanw }
680 1.18.6.2 nathanw #ifdef ZSMACDEBUG
681 1.18.6.2 nathanw zsprintf("Checking for rate %d. Found source #%d.\n",bps, src);
682 1.18.6.2 nathanw #endif
683 1.18.6.2 nathanw if (src == -1)
684 1.18.6.2 nathanw return (EINVAL); /* no can do */
685 1.18.6.2 nathanw
686 1.18.6.2 nathanw /*
687 1.18.6.2 nathanw * The M.I. layer likes to keep cs_brg_clk current, even though
688 1.18.6.2 nathanw * we are the only ones who should be touching the BRG's rate.
689 1.18.6.2 nathanw *
690 1.18.6.2 nathanw * Note: we are assuming that any ZSC_EXTERN signal source comes in
691 1.18.6.2 nathanw * on the RTxC pin. Correct for the mac68k obio zsc.
692 1.18.6.2 nathanw */
693 1.18.6.2 nathanw if (sf & ZSC_EXTERN)
694 1.18.6.2 nathanw cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;
695 1.18.6.2 nathanw else
696 1.18.6.2 nathanw cs->cs_brg_clk = PCLK / 16;
697 1.18.6.2 nathanw
698 1.18.6.2 nathanw /*
699 1.18.6.2 nathanw * Now we have a source, so set it up.
700 1.18.6.2 nathanw */
701 1.18.6.2 nathanw s = splzs();
702 1.18.6.2 nathanw xcs->cs_psource = src;
703 1.18.6.2 nathanw xcs->cs_pclk_flag = sf;
704 1.18.6.2 nathanw bps = rate0;
705 1.18.6.2 nathanw if (sf & ZSC_BRG) {
706 1.18.6.2 nathanw cs->cs_preg[4] = ZSWR4_CLK_X16;
707 1.18.6.2 nathanw cs->cs_preg[11]= ZSWR11_RXCLK_BAUD | ZSWR11_TXCLK_BAUD;
708 1.18.6.2 nathanw if (sf & ZSC_PCLK) {
709 1.18.6.2 nathanw cs->cs_preg[14] = ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK;
710 1.18.6.2 nathanw } else {
711 1.18.6.2 nathanw cs->cs_preg[14] = ZSWR14_BAUD_ENA;
712 1.18.6.2 nathanw }
713 1.18.6.2 nathanw tc = tc0;
714 1.18.6.2 nathanw } else {
715 1.18.6.2 nathanw cs->cs_preg[4] = tc0;
716 1.18.6.2 nathanw if (sf & ZSC_RTXDIV) {
717 1.18.6.2 nathanw cs->cs_preg[11] = ZSWR11_RXCLK_RTXC | ZSWR11_TXCLK_RTXC;
718 1.18.6.2 nathanw } else {
719 1.18.6.2 nathanw cs->cs_preg[11] = ZSWR11_RXCLK_TRXC | ZSWR11_TXCLK_TRXC;
720 1.18.6.2 nathanw }
721 1.18.6.2 nathanw cs->cs_preg[14]= 0;
722 1.18.6.2 nathanw tc = 0xffff;
723 1.18.6.2 nathanw }
724 1.18.6.2 nathanw /* Set the BAUD rate divisor. */
725 1.18.6.2 nathanw cs->cs_preg[12] = tc;
726 1.18.6.2 nathanw cs->cs_preg[13] = tc >> 8;
727 1.18.6.2 nathanw splx(s);
728 1.18.6.2 nathanw
729 1.18.6.2 nathanw #ifdef ZSMACDEBUG
730 1.18.6.2 nathanw zsprintf("Rate is %7d, tc is %7d, source no. %2d, flags %4x\n", \
731 1.18.6.2 nathanw bps, tc, src, sf);
732 1.18.6.2 nathanw zsprintf("Registers are: 4 %x, 11 %x, 14 %x\n\n",
733 1.18.6.2 nathanw cs->cs_preg[4], cs->cs_preg[11], cs->cs_preg[14]);
734 1.18.6.2 nathanw #endif
735 1.18.6.2 nathanw
736 1.18.6.2 nathanw cs->cs_preg[5] |= ZSWR5_RTS; /* Make sure the drivers are on! */
737 1.18.6.2 nathanw
738 1.18.6.2 nathanw /* Caller will stuff the pending registers. */
739 1.18.6.2 nathanw return (0);
740 1.18.6.2 nathanw }
741 1.18.6.2 nathanw
742 1.18.6.2 nathanw int
743 1.18.6.2 nathanw zs_set_modes(cs, cflag)
744 1.18.6.2 nathanw struct zs_chanstate *cs;
745 1.18.6.2 nathanw int cflag; /* bits per second */
746 1.18.6.2 nathanw {
747 1.18.6.2 nathanw struct xzs_chanstate *xcs = (void*)cs;
748 1.18.6.2 nathanw int s;
749 1.18.6.2 nathanw
750 1.18.6.2 nathanw /*
751 1.18.6.2 nathanw * Make sure we don't enable hfc on a signal line we're ignoring.
752 1.18.6.2 nathanw * As we enable CTS interrupts only if we have CRTSCTS or CDTRCTS,
753 1.18.6.2 nathanw * this code also effectivly turns off ZSWR15_CTS_IE.
754 1.18.6.2 nathanw *
755 1.18.6.2 nathanw * Also, disable DCD interrupts if we've been told to ignore
756 1.18.6.2 nathanw * the DCD pin. Happens on mac68k because the input line for
757 1.18.6.2 nathanw * DCD can also be used as a clock input. (Just set CLOCAL.)
758 1.18.6.2 nathanw *
759 1.18.6.2 nathanw * If someone tries to turn an invalid flow mode on, Just Say No
760 1.18.6.2 nathanw * (Suggested by gwr)
761 1.18.6.2 nathanw */
762 1.18.6.2 nathanw if ((cflag & CDTRCTS) && (cflag & (CRTSCTS | MDMBUF)))
763 1.18.6.2 nathanw return (EINVAL);
764 1.18.6.2 nathanw if (xcs->cs_hwflags & ZS_HWFLAG_NO_DCD) {
765 1.18.6.2 nathanw if (cflag & MDMBUF)
766 1.18.6.2 nathanw return (EINVAL);
767 1.18.6.2 nathanw cflag |= CLOCAL;
768 1.18.6.2 nathanw }
769 1.18.6.2 nathanw if ((xcs->cs_hwflags & ZS_HWFLAG_NO_CTS) && (cflag & (CRTSCTS | CDTRCTS)))
770 1.18.6.2 nathanw return (EINVAL);
771 1.18.6.2 nathanw
772 1.18.6.2 nathanw /*
773 1.18.6.2 nathanw * Output hardware flow control on the chip is horrendous:
774 1.18.6.2 nathanw * if carrier detect drops, the receiver is disabled, and if
775 1.18.6.2 nathanw * CTS drops, the transmitter is stoped IN MID CHARACTER!
776 1.18.6.2 nathanw * Therefore, NEVER set the HFC bit, and instead use the
777 1.18.6.2 nathanw * status interrupt to detect CTS changes.
778 1.18.6.2 nathanw */
779 1.18.6.2 nathanw s = splzs();
780 1.18.6.2 nathanw if ((cflag & (CLOCAL | MDMBUF)) != 0)
781 1.18.6.2 nathanw cs->cs_rr0_dcd = 0;
782 1.18.6.2 nathanw else
783 1.18.6.2 nathanw cs->cs_rr0_dcd = ZSRR0_DCD;
784 1.18.6.2 nathanw /*
785 1.18.6.2 nathanw * The mac hardware only has one output, DTR (HSKo in Mac
786 1.18.6.2 nathanw * parlance). In HFC mode, we use it for the functions
787 1.18.6.2 nathanw * typically served by RTS and DTR on other ports, so we
788 1.18.6.2 nathanw * have to fake the upper layer out some.
789 1.18.6.2 nathanw *
790 1.18.6.2 nathanw * CRTSCTS we use CTS as an input which tells us when to shut up.
791 1.18.6.2 nathanw * We make no effort to shut up the other side of the connection.
792 1.18.6.2 nathanw * DTR is used to hang up the modem.
793 1.18.6.2 nathanw *
794 1.18.6.2 nathanw * In CDTRCTS, we use CTS to tell us to stop, but we use DTR to
795 1.18.6.2 nathanw * shut up the other side.
796 1.18.6.2 nathanw */
797 1.18.6.2 nathanw if ((cflag & CRTSCTS) != 0) {
798 1.18.6.2 nathanw cs->cs_wr5_dtr = ZSWR5_DTR;
799 1.18.6.2 nathanw cs->cs_wr5_rts = 0;
800 1.18.6.2 nathanw cs->cs_rr0_cts = ZSRR0_CTS;
801 1.18.6.2 nathanw } else if ((cflag & CDTRCTS) != 0) {
802 1.18.6.2 nathanw cs->cs_wr5_dtr = 0;
803 1.18.6.2 nathanw cs->cs_wr5_rts = ZSWR5_DTR;
804 1.18.6.2 nathanw cs->cs_rr0_cts = ZSRR0_CTS;
805 1.18.6.2 nathanw } else if ((cflag & MDMBUF) != 0) {
806 1.18.6.2 nathanw cs->cs_wr5_dtr = 0;
807 1.18.6.2 nathanw cs->cs_wr5_rts = ZSWR5_DTR;
808 1.18.6.2 nathanw cs->cs_rr0_cts = ZSRR0_DCD;
809 1.18.6.2 nathanw } else {
810 1.18.6.2 nathanw cs->cs_wr5_dtr = ZSWR5_DTR;
811 1.18.6.2 nathanw cs->cs_wr5_rts = 0;
812 1.18.6.2 nathanw cs->cs_rr0_cts = 0;
813 1.18.6.2 nathanw }
814 1.18.6.2 nathanw splx(s);
815 1.18.6.2 nathanw
816 1.18.6.2 nathanw /* Caller will stuff the pending registers. */
817 1.18.6.2 nathanw return (0);
818 1.18.6.2 nathanw }
819 1.18.6.2 nathanw
820 1.18.6.2 nathanw
821 1.18.6.2 nathanw /*
822 1.18.6.2 nathanw * Read or write the chip with suitable delays.
823 1.18.6.2 nathanw * MacII hardware has the delay built in.
824 1.18.6.2 nathanw * No need for extra delay. :-) However, some clock-chirped
825 1.18.6.2 nathanw * macs, or zsc's on serial add-on boards might need it.
826 1.18.6.2 nathanw */
827 1.18.6.2 nathanw #define ZS_DELAY()
828 1.18.6.2 nathanw
829 1.18.6.2 nathanw u_char
830 1.18.6.2 nathanw zs_read_reg(cs, reg)
831 1.18.6.2 nathanw struct zs_chanstate *cs;
832 1.18.6.2 nathanw u_char reg;
833 1.18.6.2 nathanw {
834 1.18.6.2 nathanw u_char val;
835 1.18.6.2 nathanw
836 1.18.6.2 nathanw out8(cs->cs_reg_csr, reg);
837 1.18.6.2 nathanw ZS_DELAY();
838 1.18.6.2 nathanw val = in8(cs->cs_reg_csr);
839 1.18.6.2 nathanw ZS_DELAY();
840 1.18.6.2 nathanw return val;
841 1.18.6.2 nathanw }
842 1.18.6.2 nathanw
843 1.18.6.2 nathanw void
844 1.18.6.2 nathanw zs_write_reg(cs, reg, val)
845 1.18.6.2 nathanw struct zs_chanstate *cs;
846 1.18.6.2 nathanw u_char reg, val;
847 1.18.6.2 nathanw {
848 1.18.6.2 nathanw out8(cs->cs_reg_csr, reg);
849 1.18.6.2 nathanw ZS_DELAY();
850 1.18.6.2 nathanw out8(cs->cs_reg_csr, val);
851 1.18.6.2 nathanw ZS_DELAY();
852 1.18.6.2 nathanw }
853 1.18.6.2 nathanw
854 1.18.6.2 nathanw u_char zs_read_csr(cs)
855 1.18.6.2 nathanw struct zs_chanstate *cs;
856 1.18.6.2 nathanw {
857 1.18.6.2 nathanw register u_char val;
858 1.18.6.2 nathanw
859 1.18.6.2 nathanw val = in8(cs->cs_reg_csr);
860 1.18.6.2 nathanw ZS_DELAY();
861 1.18.6.2 nathanw /* make up for the fact CTS is wired backwards */
862 1.18.6.2 nathanw val ^= ZSRR0_CTS;
863 1.18.6.2 nathanw return val;
864 1.18.6.2 nathanw }
865 1.18.6.2 nathanw
866 1.18.6.2 nathanw void zs_write_csr(cs, val)
867 1.18.6.2 nathanw struct zs_chanstate *cs;
868 1.18.6.2 nathanw u_char val;
869 1.18.6.2 nathanw {
870 1.18.6.2 nathanw /* Note, the csr does not write CTS... */
871 1.18.6.2 nathanw out8(cs->cs_reg_csr, val);
872 1.18.6.2 nathanw ZS_DELAY();
873 1.18.6.2 nathanw }
874 1.18.6.2 nathanw
875 1.18.6.2 nathanw u_char zs_read_data(cs)
876 1.18.6.2 nathanw struct zs_chanstate *cs;
877 1.18.6.2 nathanw {
878 1.18.6.2 nathanw register u_char val;
879 1.18.6.2 nathanw
880 1.18.6.2 nathanw val = in8(cs->cs_reg_data);
881 1.18.6.2 nathanw ZS_DELAY();
882 1.18.6.2 nathanw return val;
883 1.18.6.2 nathanw }
884 1.18.6.2 nathanw
885 1.18.6.2 nathanw void zs_write_data(cs, val)
886 1.18.6.2 nathanw struct zs_chanstate *cs;
887 1.18.6.2 nathanw u_char val;
888 1.18.6.2 nathanw {
889 1.18.6.2 nathanw out8(cs->cs_reg_data, val);
890 1.18.6.2 nathanw ZS_DELAY();
891 1.18.6.2 nathanw }
892 1.18.6.2 nathanw
893 1.18.6.2 nathanw /****************************************************************
894 1.18.6.2 nathanw * Console support functions (powermac specific!)
895 1.18.6.2 nathanw * Note: this code is allowed to know about the layout of
896 1.18.6.2 nathanw * the chip registers, and uses that to keep things simple.
897 1.18.6.2 nathanw * XXX - I think I like the mvme167 code better. -gwr
898 1.18.6.2 nathanw * XXX - Well :-P :-) -wrs
899 1.18.6.2 nathanw ****************************************************************/
900 1.18.6.2 nathanw
901 1.18.6.2 nathanw #define zscnpollc nullcnpollc
902 1.18.6.2 nathanw cons_decl(zs);
903 1.18.6.2 nathanw
904 1.18.6.2 nathanw static int stdin, stdout;
905 1.18.6.2 nathanw
906 1.18.6.2 nathanw /*
907 1.18.6.2 nathanw * Console functions.
908 1.18.6.2 nathanw */
909 1.18.6.2 nathanw
910 1.18.6.2 nathanw /*
911 1.18.6.2 nathanw * zscnprobe is the routine which gets called as the kernel is trying to
912 1.18.6.2 nathanw * figure out where the console should be. Each io driver which might
913 1.18.6.2 nathanw * be the console (as defined in mac68k/conf.c) gets probed. The probe
914 1.18.6.2 nathanw * fills in the consdev structure. Important parts are the device #,
915 1.18.6.2 nathanw * and the console priority. Values are CN_DEAD (don't touch me),
916 1.18.6.2 nathanw * CN_NORMAL (I'm here, but elsewhere might be better), CN_INTERNAL
917 1.18.6.2 nathanw * (the video, better than CN_NORMAL), and CN_REMOTE (pick me!)
918 1.18.6.2 nathanw *
919 1.18.6.2 nathanw * As the mac's a bit different, we do extra work here. We mainly check
920 1.18.6.2 nathanw * to see if we have serial echo going on. Also chould check for default
921 1.18.6.2 nathanw * speeds.
922 1.18.6.2 nathanw */
923 1.18.6.2 nathanw
924 1.18.6.2 nathanw /*
925 1.18.6.2 nathanw * Polled input char.
926 1.18.6.2 nathanw */
927 1.18.6.2 nathanw int
928 1.18.6.2 nathanw zs_getc(v)
929 1.18.6.2 nathanw void *v;
930 1.18.6.2 nathanw {
931 1.18.6.2 nathanw register volatile struct zschan *zc = v;
932 1.18.6.2 nathanw register int s, c, rr0;
933 1.18.6.2 nathanw
934 1.18.6.2 nathanw s = splhigh();
935 1.18.6.2 nathanw /* Wait for a character to arrive. */
936 1.18.6.2 nathanw do {
937 1.18.6.2 nathanw rr0 = in8(&zc->zc_csr);
938 1.18.6.2 nathanw ZS_DELAY();
939 1.18.6.2 nathanw } while ((rr0 & ZSRR0_RX_READY) == 0);
940 1.18.6.2 nathanw
941 1.18.6.2 nathanw c = in8(&zc->zc_data);
942 1.18.6.2 nathanw ZS_DELAY();
943 1.18.6.2 nathanw splx(s);
944 1.18.6.2 nathanw
945 1.18.6.2 nathanw /*
946 1.18.6.2 nathanw * This is used by the kd driver to read scan codes,
947 1.18.6.2 nathanw * so don't translate '\r' ==> '\n' here...
948 1.18.6.2 nathanw */
949 1.18.6.2 nathanw return (c);
950 1.18.6.2 nathanw }
951 1.18.6.2 nathanw
952 1.18.6.2 nathanw /*
953 1.18.6.2 nathanw * Polled output char.
954 1.18.6.2 nathanw */
955 1.18.6.2 nathanw void
956 1.18.6.2 nathanw zs_putc(v, c)
957 1.18.6.2 nathanw void *v;
958 1.18.6.2 nathanw int c;
959 1.18.6.2 nathanw {
960 1.18.6.2 nathanw register volatile struct zschan *zc = v;
961 1.18.6.2 nathanw register int s, rr0;
962 1.18.6.2 nathanw register long wait = 0;
963 1.18.6.2 nathanw
964 1.18.6.2 nathanw s = splhigh();
965 1.18.6.2 nathanw /* Wait for transmitter to become ready. */
966 1.18.6.2 nathanw do {
967 1.18.6.2 nathanw rr0 = in8(&zc->zc_csr);
968 1.18.6.2 nathanw ZS_DELAY();
969 1.18.6.2 nathanw } while (((rr0 & ZSRR0_TX_READY) == 0) && (wait++ < 1000000));
970 1.18.6.2 nathanw
971 1.18.6.2 nathanw if ((rr0 & ZSRR0_TX_READY) != 0) {
972 1.18.6.2 nathanw out8(&zc->zc_data, c);
973 1.18.6.2 nathanw ZS_DELAY();
974 1.18.6.2 nathanw }
975 1.18.6.2 nathanw splx(s);
976 1.18.6.2 nathanw }
977 1.18.6.2 nathanw
978 1.18.6.2 nathanw
979 1.18.6.2 nathanw /*
980 1.18.6.2 nathanw * Polled console input putchar.
981 1.18.6.2 nathanw */
982 1.18.6.2 nathanw int
983 1.18.6.2 nathanw zscngetc(dev)
984 1.18.6.2 nathanw dev_t dev;
985 1.18.6.2 nathanw {
986 1.18.6.2 nathanw register volatile struct zschan *zc = zs_conschan;
987 1.18.6.2 nathanw register int c;
988 1.18.6.2 nathanw
989 1.18.6.2 nathanw if (zc) {
990 1.18.6.2 nathanw c = zs_getc((void *)zc);
991 1.18.6.2 nathanw } else {
992 1.18.6.2 nathanw char ch = 0;
993 1.18.6.2 nathanw OF_read(stdin, &ch, 1);
994 1.18.6.2 nathanw c = ch;
995 1.18.6.2 nathanw }
996 1.18.6.2 nathanw return c;
997 1.18.6.2 nathanw }
998 1.18.6.2 nathanw
999 1.18.6.2 nathanw /*
1000 1.18.6.2 nathanw * Polled console output putchar.
1001 1.18.6.2 nathanw */
1002 1.18.6.2 nathanw void
1003 1.18.6.2 nathanw zscnputc(dev, c)
1004 1.18.6.2 nathanw dev_t dev;
1005 1.18.6.2 nathanw int c;
1006 1.18.6.2 nathanw {
1007 1.18.6.2 nathanw register volatile struct zschan *zc = zs_conschan;
1008 1.18.6.2 nathanw
1009 1.18.6.2 nathanw if (zc) {
1010 1.18.6.2 nathanw zs_putc((void *)zc, c);
1011 1.18.6.2 nathanw } else {
1012 1.18.6.2 nathanw char ch = c;
1013 1.18.6.2 nathanw OF_write(stdout, &ch, 1);
1014 1.18.6.2 nathanw }
1015 1.18.6.2 nathanw }
1016 1.18.6.2 nathanw
1017 1.18.6.2 nathanw /*
1018 1.18.6.2 nathanw * Handle user request to enter kernel debugger.
1019 1.18.6.2 nathanw */
1020 1.18.6.2 nathanw void
1021 1.18.6.2 nathanw zs_abort(cs)
1022 1.18.6.2 nathanw struct zs_chanstate *cs;
1023 1.18.6.2 nathanw {
1024 1.18.6.2 nathanw volatile struct zschan *zc = zs_conschan;
1025 1.18.6.2 nathanw int rr0;
1026 1.18.6.2 nathanw register long wait = 0;
1027 1.18.6.2 nathanw
1028 1.18.6.2 nathanw if (zs_cons_canabort == 0)
1029 1.18.6.2 nathanw return;
1030 1.18.6.2 nathanw
1031 1.18.6.2 nathanw /* Wait for end of break to avoid PROM abort. */
1032 1.18.6.2 nathanw do {
1033 1.18.6.2 nathanw rr0 = in8(&zc->zc_csr);
1034 1.18.6.2 nathanw ZS_DELAY();
1035 1.18.6.2 nathanw } while ((rr0 & ZSRR0_BREAK) && (wait++ < ZSABORT_DELAY));
1036 1.18.6.2 nathanw
1037 1.18.6.2 nathanw if (wait > ZSABORT_DELAY) {
1038 1.18.6.2 nathanw zs_cons_canabort = 0;
1039 1.18.6.2 nathanw /* If we time out, turn off the abort ability! */
1040 1.18.6.2 nathanw }
1041 1.18.6.2 nathanw
1042 1.18.6.2 nathanw #if defined(KGDB)
1043 1.18.6.2 nathanw kgdb_connect(1);
1044 1.18.6.2 nathanw #elif defined(DDB)
1045 1.18.6.2 nathanw Debugger();
1046 1.18.6.2 nathanw #endif
1047 1.18.6.2 nathanw }
1048 1.18.6.2 nathanw
1049 1.18.6.2 nathanw extern int ofccngetc __P((dev_t));
1050 1.18.6.2 nathanw extern void ofccnputc __P((dev_t, int));
1051 1.18.6.2 nathanw
1052 1.18.6.2 nathanw struct consdev consdev_zs = {
1053 1.18.6.2 nathanw zscnprobe,
1054 1.18.6.2 nathanw zscninit,
1055 1.18.6.2 nathanw zscngetc,
1056 1.18.6.2 nathanw zscnputc,
1057 1.18.6.2 nathanw zscnpollc,
1058 1.18.6.2 nathanw NULL,
1059 1.18.6.2 nathanw };
1060 1.18.6.2 nathanw
1061 1.18.6.2 nathanw void
1062 1.18.6.2 nathanw zscnprobe(cp)
1063 1.18.6.2 nathanw struct consdev *cp;
1064 1.18.6.2 nathanw {
1065 1.18.6.2 nathanw int chosen, pkg;
1066 1.18.6.2 nathanw int unit = 0;
1067 1.18.6.2 nathanw char name[16];
1068 1.18.6.5 nathanw extern const struct cdevsw zstty_cdevsw;
1069 1.18.6.2 nathanw
1070 1.18.6.2 nathanw if ((chosen = OF_finddevice("/chosen")) == -1)
1071 1.18.6.2 nathanw return;
1072 1.18.6.2 nathanw
1073 1.18.6.2 nathanw if (OF_getprop(chosen, "stdin", &stdin, sizeof(stdin)) == -1)
1074 1.18.6.2 nathanw return;
1075 1.18.6.2 nathanw if (OF_getprop(chosen, "stdout", &stdout, sizeof(stdout)) == -1)
1076 1.18.6.2 nathanw return;
1077 1.18.6.2 nathanw
1078 1.18.6.2 nathanw if ((pkg = OF_instance_to_package(stdin)) == -1)
1079 1.18.6.2 nathanw return;
1080 1.18.6.2 nathanw
1081 1.18.6.2 nathanw memset(name, 0, sizeof(name));
1082 1.18.6.2 nathanw if (OF_getprop(pkg, "device_type", name, sizeof(name)) == -1)
1083 1.18.6.2 nathanw return;
1084 1.18.6.2 nathanw
1085 1.18.6.2 nathanw if (strcmp(name, "serial") != 0)
1086 1.18.6.2 nathanw return;
1087 1.18.6.2 nathanw
1088 1.18.6.2 nathanw memset(name, 0, sizeof(name));
1089 1.18.6.2 nathanw if (OF_getprop(pkg, "name", name, sizeof(name)) == -1)
1090 1.18.6.2 nathanw return;
1091 1.18.6.2 nathanw
1092 1.18.6.2 nathanw if (strcmp(name, "ch-b") == 0)
1093 1.18.6.2 nathanw unit = 1;
1094 1.18.6.2 nathanw
1095 1.18.6.5 nathanw cp->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), unit);
1096 1.18.6.2 nathanw cp->cn_pri = CN_REMOTE;
1097 1.18.6.2 nathanw }
1098 1.18.6.2 nathanw
1099 1.18.6.2 nathanw void
1100 1.18.6.2 nathanw zscninit(cp)
1101 1.18.6.2 nathanw struct consdev *cp;
1102 1.18.6.2 nathanw {
1103 1.18.6.2 nathanw int escc, escc_ch, obio, zs_offset;
1104 1.18.6.2 nathanw int ch = 0;
1105 1.18.6.2 nathanw u_int32_t reg[5];
1106 1.18.6.2 nathanw char name[16];
1107 1.18.6.2 nathanw
1108 1.18.6.2 nathanw if ((escc_ch = OF_instance_to_package(stdin)) == -1)
1109 1.18.6.2 nathanw return;
1110 1.18.6.2 nathanw
1111 1.18.6.2 nathanw memset(name, 0, sizeof(name));
1112 1.18.6.2 nathanw if (OF_getprop(escc_ch, "name", name, sizeof(name)) == -1)
1113 1.18.6.2 nathanw return;
1114 1.18.6.2 nathanw
1115 1.18.6.2 nathanw if (strcmp(name, "ch-b") == 0)
1116 1.18.6.2 nathanw ch = 1;
1117 1.18.6.2 nathanw
1118 1.18.6.2 nathanw if (OF_getprop(escc_ch, "reg", reg, sizeof(reg)) < 4)
1119 1.18.6.2 nathanw return;
1120 1.18.6.2 nathanw zs_offset = reg[0];
1121 1.18.6.2 nathanw
1122 1.18.6.2 nathanw escc = OF_parent(escc_ch);
1123 1.18.6.2 nathanw obio = OF_parent(escc);
1124 1.18.6.2 nathanw
1125 1.18.6.2 nathanw if (OF_getprop(obio, "assigned-addresses", reg, sizeof(reg)) < 12)
1126 1.18.6.2 nathanw return;
1127 1.18.6.2 nathanw zs_conschan = (void *)(reg[2] + zs_offset);
1128 1.18.6.2 nathanw
1129 1.18.6.2 nathanw zs_hwflags[0][ch] = ZS_HWFLAG_CONSOLE;
1130 1.18.6.2 nathanw }
1131