intr.h revision 1.2
1/* $NetBSD: intr.h,v 1.2 1998/07/18 21:27:27 is Exp $ */ 2/* $OpenBSD: intr.h,v 1.1 1997/10/13 10:53:45 pefo Exp $ */ 3 4/* 5 * Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#ifndef _POWERMAC_INTR_H_ 34#define _POWERMAC_INTR_H_ 35 36/* Interrupt priority `levels'. */ 37#define IPL_NONE 9 /* nothing */ 38#define IPL_SOFTCLOCK 8 /* timeouts */ 39#define IPL_SOFTNET 7 /* protocol stacks */ 40#define IPL_BIO 6 /* block I/O */ 41#define IPL_NET 5 /* network */ 42#define IPL_SOFTSERIAL 4 /* serial */ 43#define IPL_TTY 3 /* terminal */ 44#define IPL_IMP 3 /* memory allocation */ 45#define IPL_AUDIO 2 /* audio */ 46#define IPL_CLOCK 1 /* clock */ 47#define IPL_HIGH 1 /* everything */ 48#define IPL_SERIAL 0 /* serial */ 49#define NIPL 10 50 51/* Interrupt sharing types. */ 52#define IST_NONE 0 /* none */ 53#define IST_PULSE 1 /* pulsed */ 54#define IST_EDGE 2 /* edge-triggered */ 55#define IST_LEVEL 3 /* level-triggered */ 56 57#ifndef _LOCORE 58 59/* 60 * Interrupt handler chains. intr_establish() inserts a handler into 61 * the list. The handler is called with its (single) argument. 62 */ 63struct intrhand { 64 int (*ih_fun) __P((void *)); 65 void *ih_arg; 66 u_long ih_count; 67 struct intrhand *ih_next; 68 int ih_level; 69 int ih_irq; 70}; 71 72void setsoftclock __P((void)); 73void clearsoftclock __P((void)); 74int splsoftclock __P((void)); 75void setsoftnet __P((void)); 76void clearsoftnet __P((void)); 77int splsoftnet __P((void)); 78 79void do_pending_int __P((void)); 80 81static __inline int splraise __P((int)); 82static __inline int spllower __P((int)); 83static __inline void splx __P((int)); 84static __inline void softintr __P((int)); 85 86extern volatile int cpl, ipending, astpending, tickspending; 87extern int imask[]; 88 89/* 90 * Reorder protection in the following inline functions is 91 * achived with the "eieio" instruction which the assembler 92 * seems to detect and then doen't move instructions past.... 93 */ 94static __inline int 95splraise(ncpl) 96 int ncpl; 97{ 98 int ocpl; 99 100 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 101 ocpl = cpl; 102 cpl = ocpl | ncpl; 103 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 104 return (ocpl); 105} 106 107static __inline void 108splx(ncpl) 109 int ncpl; 110{ 111 112 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 113 cpl = ncpl; 114 if (ipending & ~ncpl) 115 do_pending_int(); 116 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 117} 118 119static __inline int 120spllower(ncpl) 121 int ncpl; 122{ 123 int ocpl; 124 125 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 126 ocpl = cpl; 127 cpl = ncpl; 128 if (ipending & ~ncpl) 129 do_pending_int(); 130 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 131 return (ocpl); 132} 133 134/* Following code should be implemented with lwarx/stwcx to avoid 135 * the disable/enable. i need to read the manual once more.... */ 136static __inline void 137softintr(ipl) 138 int ipl; 139{ 140 int msrsave; 141 142 __asm__ volatile("mfmsr %0" : "=r"(msrsave)); 143 __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 144 ipending |= 1 << ipl; 145 __asm__ volatile("mtmsr %0" :: "r"(msrsave)); 146} 147 148#define ICU_LEN 32 149 150/* Soft interrupt masks. */ 151#define SIR_CLOCK 28 152#define SIR_NET 29 153#define SIR_SERIAL 30 154#define SPL_CLOCK 31 155 156/* 157 * Hardware interrupt masks 158 */ 159#define splbio() splraise(imask[IPL_BIO]) 160#define splnet() splraise(imask[IPL_NET]) 161#define spltty() splraise(imask[IPL_TTY]) 162#define splaudio() splraise(imask[IPL_AUDIO]) 163#define splclock() splraise(imask[IPL_CLOCK]) 164#define splstatclock() splclock() 165#define splserial() splraise(imask[IPL_SERIAL]) 166 167#define spllpt() spltty() 168 169/* 170 * Software interrupt masks 171 * 172 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 173 * clock to softclock before it calls softclock(). 174 */ 175#define splsoftclock() spllower(imask[IPL_SOFTCLOCK]) 176#define splsoftnet() splraise(imask[IPL_SOFTNET]) 177#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 178 179/* 180 * Miscellaneous 181 */ 182#define splimp() splraise(imask[IPL_IMP]) 183#define splhigh() splraise(imask[IPL_HIGH]) 184#define spl0() spllower(0) 185 186#define setsoftclock() softintr(SIR_CLOCK) 187#define setsoftnet() softintr(SIR_NET) 188#define setsoftserial() softintr(SIR_SERIAL) 189 190#endif /* !_LOCORE */ 191 192#endif /* !_POWERMAC_INTR_H_ */ 193