pio.h revision 1.1
1 /* $NetBSD: pio.h,v 1.1 1998/05/15 10:15:54 tsubai Exp $ */ 2 /* $OpenBSD: pio.h,v 1.1 1997/10/13 10:53:47 pefo Exp $ */ 3 4 /* 5 * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed under OpenBSD by 18 * Per Fogelstrom Opsycon AB for RTMX Inc, North Carolina, USA. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 */ 35 36 #ifndef _MACHINE_PIO_H_ 37 #define _MACHINE_PIO_H_ 38 /* 39 * I/O macros. 40 */ 41 42 static __inline void 43 __outb(a,v) 44 volatile u_int8_t *a; 45 u_int8_t v; 46 { 47 *a = v; 48 __asm__ volatile("eieio; sync"); 49 } 50 51 static __inline void 52 __outw(a,v) 53 volatile u_int16_t *a; 54 u_int16_t v; 55 { 56 *a = v; 57 __asm__ volatile("eieio; sync"); 58 } 59 60 static __inline void 61 __outl(a,v) 62 volatile u_int32_t *a; 63 u_int32_t v; 64 { 65 *a = v; 66 __asm__ volatile("eieio; sync"); 67 } 68 69 static __inline void 70 __outwrb(a,v) 71 volatile u_int16_t *a; 72 u_int16_t v; 73 { 74 __asm__ volatile("sthbrx %0, 0, %1" :: "r"(v), "r"(a)); 75 __asm__ volatile("eieio; sync"); 76 } 77 78 static __inline void 79 __outlrb(a,v) 80 volatile u_int32_t *a; 81 u_int32_t v; 82 { 83 __asm__ volatile("stwbrx %0, 0, %1" :: "r"(v), "r"(a)); 84 __asm__ volatile("eieio; sync"); 85 } 86 87 static __inline u_int8_t 88 __inb(a) 89 volatile u_int8_t *a; 90 { 91 u_int8_t _v_; 92 93 _v_ = *a; 94 __asm__ volatile("eieio; sync"); 95 return _v_; 96 } 97 98 static __inline u_int16_t 99 __inw(a) 100 volatile u_int16_t *a; 101 { 102 u_int16_t _v_; 103 104 _v_ = *a; 105 __asm__ volatile("eieio; sync"); 106 return _v_; 107 } 108 109 static __inline u_int32_t 110 __inl(a) 111 volatile u_int32_t *a; 112 { 113 u_int32_t _v_; 114 115 _v_ = *a; 116 __asm__ volatile("eieio; sync"); 117 return _v_; 118 } 119 120 static __inline u_int16_t 121 __inwrb(a) 122 volatile u_int16_t *a; 123 { 124 u_int16_t _v_; 125 126 __asm__ volatile("lhbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 127 __asm__ volatile("eieio; sync"); 128 return _v_; 129 } 130 131 static __inline u_int32_t 132 __inlrb(a) 133 volatile u_int32_t *a; 134 { 135 u_int32_t _v_; 136 137 __asm__ volatile("lwbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); 138 __asm__ volatile("eieio; sync"); 139 return _v_; 140 } 141 142 #define outb(a,v) (__outb((volatile u_int8_t *)(a), v)) 143 #define out8(a,v) outb(a,v) 144 #define outw(a,v) (__outw((volatile u_int16_t *)(a), v)) 145 #define out16(a,v) outw(a,v) 146 #define outl(a,v) (__outl((volatile u_int32_t *)(a), v)) 147 #define out32(a,v) outl(a,v) 148 #define inb(a) (__inb((volatile u_int8_t *)(a))) 149 #define in8(a) inb(a) 150 #define inw(a) (__inw((volatile u_int16_t *)(a))) 151 #define in16(a) inw(a) 152 #define inl(a) (__inl((volatile u_int32_t *)(a))) 153 #define in32(a) inl(a) 154 155 #define out8rb(a,v) outb(a,v) 156 #define outwrb(a,v) (__outwrb((volatile u_int16_t *)(a), v)) 157 #define out16rb(a,v) outwrb(a,v) 158 #define outlrb(a,v) (__outlrb((volatile u_int32_t *)(a), v)) 159 #define out32rb(a,v) outlrb(a,v) 160 #define in8rb(a) inb(a) 161 #define inwrb(a) (__inwrb((volatile u_int16_t *)(a))) 162 #define in16rb(a) inwrb(a) 163 #define inlrb(a) (__inlrb((volatile u_int32_t *)(a))) 164 #define in32rb(a) inlrb(a) 165 166 167 static __inline void 168 __outsb(a,s,c) 169 volatile u_int8_t *a; 170 const u_int8_t *s; 171 size_t c; 172 { 173 while (c--) 174 *a = *s++; 175 __asm__ volatile("eieio; sync"); 176 } 177 178 static __inline void 179 __outsw(a,s,c) 180 volatile u_int16_t *a; 181 const u_int16_t *s; 182 size_t c; 183 { 184 while (c--) 185 *a = *s++; 186 __asm__ volatile("eieio; sync"); 187 } 188 189 static __inline void 190 __outsl(a,s,c) 191 volatile u_int32_t *a; 192 const u_int32_t *s; 193 size_t c; 194 { 195 while (c--) 196 *a = *s++; 197 __asm__ volatile("eieio; sync"); 198 } 199 200 static __inline void 201 __outswrb(a,s,c) 202 volatile u_int16_t *a; 203 const u_int16_t *s; 204 size_t c; 205 { 206 while (c--) 207 __asm__ volatile("sthbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 208 __asm__ volatile("eieio; sync"); 209 } 210 211 static __inline void 212 __outslrb(a,s,c) 213 volatile u_int32_t *a; 214 const u_int32_t *s; 215 size_t c; 216 { 217 while (c--) 218 __asm__ volatile("stwbrx %0, 0, %1" :: "r"(*s++), "r"(a)); 219 __asm__ volatile("eieio; sync"); 220 } 221 222 static __inline void 223 __insb(a,d,c) 224 volatile u_int8_t *a; 225 u_int8_t *d; 226 size_t c; 227 { 228 while (c--) 229 *d++ = *a; 230 __asm__ volatile("eieio; sync"); 231 } 232 233 static __inline void 234 __insw(a,d,c) 235 volatile u_int16_t *a; 236 u_int16_t *d; 237 size_t c; 238 { 239 while (c--) 240 *d++ = *a; 241 __asm__ volatile("eieio; sync"); 242 } 243 244 static __inline void 245 __insl(a,d,c) 246 volatile u_int32_t *a; 247 u_int32_t *d; 248 size_t c; 249 { 250 while (c--) 251 *d++ = *a; 252 __asm__ volatile("eieio; sync"); 253 } 254 255 static __inline void 256 __inswrb(a,d,c) 257 volatile u_int16_t *a; 258 u_int16_t *d; 259 size_t c; 260 { 261 while (c--) 262 __asm__ volatile("lhbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 263 __asm__ volatile("eieio; sync"); 264 } 265 266 static __inline void 267 __inslrb(a,d,c) 268 volatile u_int32_t *a; 269 u_int32_t *d; 270 size_t c; 271 { 272 while (c--) 273 __asm__ volatile("lwbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); 274 __asm__ volatile("eieio; sync"); 275 } 276 277 #define outsb(a,s,c) (__outsb((volatile u_int8_t *)(a), s, c)) 278 #define outs8(a,s,c) outsb(a,s,c) 279 #define outsw(a,s,c) (__outsw((volatile u_int16_t *)(a), s, c)) 280 #define outs16(a,s,c) outsw(a,s,c) 281 #define outsl(a,s,c) (__outsl((volatile u_int32_t *)(a), s, c)) 282 #define outs32(a,s,c) outsl(a,s,c) 283 #define insb(a,d,c) (__insb((volatile u_int8_t *)(a), d, c)) 284 #define ins8(a,d,c) insb(a,d,c) 285 #define insw(a,d,c) (__insw((volatile u_int16_t *)(a), d, c)) 286 #define ins16(a,d,c) insw(a,d,c) 287 #define insl(a,d,c) (__insl((volatile u_int32_t *)(a), d, c)) 288 #define ins32(a,d,c) insl(a,d,c) 289 290 #define outs8rb(a,s,c) outsb(a,s,c) 291 #define outswrb(a,s,c) (__outswrb((volatile u_int16_t *)(a), s, c)) 292 #define outs16rb(a,s,c) outswrb(a,s,c) 293 #define outslrb(a,s,c) (__outslrb((volatile u_int32_t *)(a), s, c)) 294 #define outs32rb(a,s,c) outslrb(a,s,c) 295 #define ins8rb(a,d,c) insb(a,d,c) 296 #define inswrb(a,d,c) (__inswrb((volatile u_int16_t *)(a), d, c)) 297 #define ins16rb(a,d,c) inswrb(a,d,c) 298 #define inslrb(a,d,c) (__inslrb((volatile u_int32_t *)(a), d, c)) 299 #define ins32rb(a,d,c) inslrb(a,d,c) 300 301 #endif /*_MACHINE_PIO_H_*/ 302
Indexes created Tue Oct 21 12:09:54 GMT 2025