pci_machdep.c revision 1.18.6.2 1 1.18.6.2 nathanw /* $NetBSD: pci_machdep.c,v 1.18.6.2 2002/08/27 23:44:47 nathanw Exp $ */
2 1.18.6.2 nathanw
3 1.18.6.2 nathanw /*
4 1.18.6.2 nathanw * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 1.18.6.2 nathanw * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 1.18.6.2 nathanw *
7 1.18.6.2 nathanw * Redistribution and use in source and binary forms, with or without
8 1.18.6.2 nathanw * modification, are permitted provided that the following conditions
9 1.18.6.2 nathanw * are met:
10 1.18.6.2 nathanw * 1. Redistributions of source code must retain the above copyright
11 1.18.6.2 nathanw * notice, this list of conditions and the following disclaimer.
12 1.18.6.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
13 1.18.6.2 nathanw * notice, this list of conditions and the following disclaimer in the
14 1.18.6.2 nathanw * documentation and/or other materials provided with the distribution.
15 1.18.6.2 nathanw * 3. All advertising materials mentioning features or use of this software
16 1.18.6.2 nathanw * must display the following acknowledgement:
17 1.18.6.2 nathanw * This product includes software developed by Charles M. Hannum.
18 1.18.6.2 nathanw * 4. The name of the author may not be used to endorse or promote products
19 1.18.6.2 nathanw * derived from this software without specific prior written permission.
20 1.18.6.2 nathanw *
21 1.18.6.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 1.18.6.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 1.18.6.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 1.18.6.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 1.18.6.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 1.18.6.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 1.18.6.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 1.18.6.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 1.18.6.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 1.18.6.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 1.18.6.2 nathanw */
32 1.18.6.2 nathanw
33 1.18.6.2 nathanw /*
34 1.18.6.2 nathanw * Machine-specific functions for PCI autoconfiguration.
35 1.18.6.2 nathanw *
36 1.18.6.2 nathanw * On PCs, there are two methods of generating PCI configuration cycles.
37 1.18.6.2 nathanw * We try to detect the appropriate mechanism for this machine and set
38 1.18.6.2 nathanw * up a few function pointers to access the correct method directly.
39 1.18.6.2 nathanw *
40 1.18.6.2 nathanw * The configuration method can be hard-coded in the config file by
41 1.18.6.2 nathanw * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42 1.18.6.2 nathanw * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43 1.18.6.2 nathanw */
44 1.18.6.2 nathanw
45 1.18.6.2 nathanw #include <sys/types.h>
46 1.18.6.2 nathanw #include <sys/param.h>
47 1.18.6.2 nathanw #include <sys/time.h>
48 1.18.6.2 nathanw #include <sys/systm.h>
49 1.18.6.2 nathanw #include <sys/errno.h>
50 1.18.6.2 nathanw #include <sys/device.h>
51 1.18.6.2 nathanw
52 1.18.6.2 nathanw #include <uvm/uvm_extern.h>
53 1.18.6.2 nathanw
54 1.18.6.2 nathanw #define _MACPPC_BUS_DMA_PRIVATE
55 1.18.6.2 nathanw #include <machine/bus.h>
56 1.18.6.2 nathanw
57 1.18.6.2 nathanw #include <machine/bus.h>
58 1.18.6.2 nathanw #include <machine/pio.h>
59 1.18.6.2 nathanw #include <machine/intr.h>
60 1.18.6.2 nathanw
61 1.18.6.2 nathanw #include <dev/pci/pcivar.h>
62 1.18.6.2 nathanw #include <dev/pci/pcireg.h>
63 1.18.6.2 nathanw
64 1.18.6.2 nathanw #include <dev/ofw/openfirm.h>
65 1.18.6.2 nathanw #include <dev/ofw/ofw_pci.h>
66 1.18.6.2 nathanw
67 1.18.6.2 nathanw static void fixpci __P((int, pci_chipset_tag_t));
68 1.18.6.2 nathanw static int find_node_intr __P((int, u_int32_t *, u_int32_t *));
69 1.18.6.2 nathanw
70 1.18.6.2 nathanw /*
71 1.18.6.2 nathanw * PCI doesn't have any special needs; just use the generic versions
72 1.18.6.2 nathanw * of these functions.
73 1.18.6.2 nathanw */
74 1.18.6.2 nathanw struct macppc_bus_dma_tag pci_bus_dma_tag = {
75 1.18.6.2 nathanw 0, /* _bounce_thresh */
76 1.18.6.2 nathanw _bus_dmamap_create,
77 1.18.6.2 nathanw _bus_dmamap_destroy,
78 1.18.6.2 nathanw _bus_dmamap_load,
79 1.18.6.2 nathanw _bus_dmamap_load_mbuf,
80 1.18.6.2 nathanw _bus_dmamap_load_uio,
81 1.18.6.2 nathanw _bus_dmamap_load_raw,
82 1.18.6.2 nathanw _bus_dmamap_unload,
83 1.18.6.2 nathanw NULL, /* _dmamap_sync */
84 1.18.6.2 nathanw _bus_dmamem_alloc,
85 1.18.6.2 nathanw _bus_dmamem_free,
86 1.18.6.2 nathanw _bus_dmamem_map,
87 1.18.6.2 nathanw _bus_dmamem_unmap,
88 1.18.6.2 nathanw _bus_dmamem_mmap,
89 1.18.6.2 nathanw };
90 1.18.6.2 nathanw
91 1.18.6.2 nathanw void
92 1.18.6.2 nathanw pci_attach_hook(parent, self, pba)
93 1.18.6.2 nathanw struct device *parent, *self;
94 1.18.6.2 nathanw struct pcibus_attach_args *pba;
95 1.18.6.2 nathanw {
96 1.18.6.2 nathanw pci_chipset_tag_t pc = pba->pba_pc;
97 1.18.6.2 nathanw int bus = pba->pba_bus;
98 1.18.6.2 nathanw int node, nn, sz;
99 1.18.6.2 nathanw int32_t busrange[2];
100 1.18.6.2 nathanw
101 1.18.6.2 nathanw for (node = pc->node; node; node = nn) {
102 1.18.6.2 nathanw sz = OF_getprop(node, "bus-range", busrange, 8);
103 1.18.6.2 nathanw if (sz == 8 && busrange[0] == bus) {
104 1.18.6.2 nathanw fixpci(node, pc);
105 1.18.6.2 nathanw return;
106 1.18.6.2 nathanw }
107 1.18.6.2 nathanw if ((nn = OF_child(node)) != 0)
108 1.18.6.2 nathanw continue;
109 1.18.6.2 nathanw while ((nn = OF_peer(node)) == 0) {
110 1.18.6.2 nathanw node = OF_parent(node);
111 1.18.6.2 nathanw if (node == pc->node)
112 1.18.6.2 nathanw return; /* not found */
113 1.18.6.2 nathanw }
114 1.18.6.2 nathanw }
115 1.18.6.2 nathanw }
116 1.18.6.2 nathanw
117 1.18.6.2 nathanw int
118 1.18.6.2 nathanw pci_bus_maxdevs(pc, busno)
119 1.18.6.2 nathanw pci_chipset_tag_t pc;
120 1.18.6.2 nathanw int busno;
121 1.18.6.2 nathanw {
122 1.18.6.2 nathanw
123 1.18.6.2 nathanw /*
124 1.18.6.2 nathanw * Bus number is irrelevant. Configuration Mechanism 1 is in
125 1.18.6.2 nathanw * use, can have devices 0-32 (i.e. the `normal' range).
126 1.18.6.2 nathanw */
127 1.18.6.2 nathanw return 32;
128 1.18.6.2 nathanw }
129 1.18.6.2 nathanw
130 1.18.6.2 nathanw pcitag_t
131 1.18.6.2 nathanw pci_make_tag(pc, bus, device, function)
132 1.18.6.2 nathanw pci_chipset_tag_t pc;
133 1.18.6.2 nathanw int bus, device, function;
134 1.18.6.2 nathanw {
135 1.18.6.2 nathanw pcitag_t tag;
136 1.18.6.2 nathanw
137 1.18.6.2 nathanw if (bus >= 256 || device >= 32 || function >= 8)
138 1.18.6.2 nathanw panic("pci_make_tag: bad request");
139 1.18.6.2 nathanw
140 1.18.6.2 nathanw /* XXX magic number */
141 1.18.6.2 nathanw tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8);
142 1.18.6.2 nathanw
143 1.18.6.2 nathanw return tag;
144 1.18.6.2 nathanw }
145 1.18.6.2 nathanw
146 1.18.6.2 nathanw void
147 1.18.6.2 nathanw pci_decompose_tag(pc, tag, bp, dp, fp)
148 1.18.6.2 nathanw pci_chipset_tag_t pc;
149 1.18.6.2 nathanw pcitag_t tag;
150 1.18.6.2 nathanw int *bp, *dp, *fp;
151 1.18.6.2 nathanw {
152 1.18.6.2 nathanw
153 1.18.6.2 nathanw if (bp != NULL)
154 1.18.6.2 nathanw *bp = (tag >> 16) & 0xff;
155 1.18.6.2 nathanw if (dp != NULL)
156 1.18.6.2 nathanw *dp = (tag >> 11) & 0x1f;
157 1.18.6.2 nathanw if (fp != NULL)
158 1.18.6.2 nathanw *fp = (tag >> 8) & 0x07;
159 1.18.6.2 nathanw }
160 1.18.6.2 nathanw
161 1.18.6.2 nathanw pcireg_t
162 1.18.6.2 nathanw pci_conf_read(pc, tag, reg)
163 1.18.6.2 nathanw pci_chipset_tag_t pc;
164 1.18.6.2 nathanw pcitag_t tag;
165 1.18.6.2 nathanw int reg;
166 1.18.6.2 nathanw {
167 1.18.6.2 nathanw
168 1.18.6.2 nathanw return (*pc->conf_read)(pc, tag, reg);
169 1.18.6.2 nathanw }
170 1.18.6.2 nathanw
171 1.18.6.2 nathanw void
172 1.18.6.2 nathanw pci_conf_write(pc, tag, reg, data)
173 1.18.6.2 nathanw pci_chipset_tag_t pc;
174 1.18.6.2 nathanw pcitag_t tag;
175 1.18.6.2 nathanw int reg;
176 1.18.6.2 nathanw pcireg_t data;
177 1.18.6.2 nathanw {
178 1.18.6.2 nathanw
179 1.18.6.2 nathanw (*pc->conf_write)(pc, tag, reg, data);
180 1.18.6.2 nathanw }
181 1.18.6.2 nathanw
182 1.18.6.2 nathanw int
183 1.18.6.2 nathanw pci_intr_map(pa, ihp)
184 1.18.6.2 nathanw struct pci_attach_args *pa;
185 1.18.6.2 nathanw pci_intr_handle_t *ihp;
186 1.18.6.2 nathanw {
187 1.18.6.2 nathanw int pin = pa->pa_intrpin;
188 1.18.6.2 nathanw int line = pa->pa_intrline;
189 1.18.6.2 nathanw
190 1.18.6.2 nathanw if (pin == 0) {
191 1.18.6.2 nathanw /* No IRQ used. */
192 1.18.6.2 nathanw goto bad;
193 1.18.6.2 nathanw }
194 1.18.6.2 nathanw
195 1.18.6.2 nathanw if (pin > 4) {
196 1.18.6.2 nathanw printf("pci_intr_map: bad interrupt pin %d\n", pin);
197 1.18.6.2 nathanw goto bad;
198 1.18.6.2 nathanw }
199 1.18.6.2 nathanw
200 1.18.6.2 nathanw /*
201 1.18.6.2 nathanw * Section 6.2.4, `Miscellaneous Functions', says that 255 means
202 1.18.6.2 nathanw * `unknown' or `no connection' on a PC. We assume that a device with
203 1.18.6.2 nathanw * `no connection' either doesn't have an interrupt (in which case the
204 1.18.6.2 nathanw * pin number should be 0, and would have been noticed above), or
205 1.18.6.2 nathanw * wasn't configured by the BIOS (in which case we punt, since there's
206 1.18.6.2 nathanw * no real way we can know how the interrupt lines are mapped in the
207 1.18.6.2 nathanw * hardware).
208 1.18.6.2 nathanw *
209 1.18.6.2 nathanw * XXX
210 1.18.6.2 nathanw * Since IRQ 0 is only used by the clock, and we can't actually be sure
211 1.18.6.2 nathanw * that the BIOS did its job, we also recognize that as meaning that
212 1.18.6.2 nathanw * the BIOS has not configured the device.
213 1.18.6.2 nathanw */
214 1.18.6.2 nathanw if (line == 0 || line == 255) {
215 1.18.6.2 nathanw printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
216 1.18.6.2 nathanw goto bad;
217 1.18.6.2 nathanw } else {
218 1.18.6.2 nathanw if (line >= ICU_LEN) {
219 1.18.6.2 nathanw printf("pci_intr_map: bad interrupt line %d\n", line);
220 1.18.6.2 nathanw goto bad;
221 1.18.6.2 nathanw }
222 1.18.6.2 nathanw }
223 1.18.6.2 nathanw
224 1.18.6.2 nathanw *ihp = line;
225 1.18.6.2 nathanw return 0;
226 1.18.6.2 nathanw
227 1.18.6.2 nathanw bad:
228 1.18.6.2 nathanw *ihp = -1;
229 1.18.6.2 nathanw return 1;
230 1.18.6.2 nathanw }
231 1.18.6.2 nathanw
232 1.18.6.2 nathanw const char *
233 1.18.6.2 nathanw pci_intr_string(pc, ih)
234 1.18.6.2 nathanw pci_chipset_tag_t pc;
235 1.18.6.2 nathanw pci_intr_handle_t ih;
236 1.18.6.2 nathanw {
237 1.18.6.2 nathanw static char irqstr[8]; /* 4 + 2 + NULL + sanity */
238 1.18.6.2 nathanw
239 1.18.6.2 nathanw if (ih == 0 || ih >= ICU_LEN)
240 1.18.6.2 nathanw panic("pci_intr_string: bogus handle 0x%x\n", ih);
241 1.18.6.2 nathanw
242 1.18.6.2 nathanw sprintf(irqstr, "irq %d", ih);
243 1.18.6.2 nathanw return (irqstr);
244 1.18.6.2 nathanw
245 1.18.6.2 nathanw }
246 1.18.6.2 nathanw
247 1.18.6.2 nathanw const struct evcnt *
248 1.18.6.2 nathanw pci_intr_evcnt(pc, ih)
249 1.18.6.2 nathanw pci_chipset_tag_t pc;
250 1.18.6.2 nathanw pci_intr_handle_t ih;
251 1.18.6.2 nathanw {
252 1.18.6.2 nathanw
253 1.18.6.2 nathanw /* XXX for now, no evcnt parent reported */
254 1.18.6.2 nathanw return NULL;
255 1.18.6.2 nathanw }
256 1.18.6.2 nathanw
257 1.18.6.2 nathanw void *
258 1.18.6.2 nathanw pci_intr_establish(pc, ih, level, func, arg)
259 1.18.6.2 nathanw pci_chipset_tag_t pc;
260 1.18.6.2 nathanw pci_intr_handle_t ih;
261 1.18.6.2 nathanw int level, (*func) __P((void *));
262 1.18.6.2 nathanw void *arg;
263 1.18.6.2 nathanw {
264 1.18.6.2 nathanw
265 1.18.6.2 nathanw if (ih == 0 || ih >= ICU_LEN)
266 1.18.6.2 nathanw panic("pci_intr_establish: bogus handle 0x%x\n", ih);
267 1.18.6.2 nathanw
268 1.18.6.2 nathanw return intr_establish(ih, IST_LEVEL, level, func, arg);
269 1.18.6.2 nathanw }
270 1.18.6.2 nathanw
271 1.18.6.2 nathanw void
272 1.18.6.2 nathanw pci_intr_disestablish(pc, cookie)
273 1.18.6.2 nathanw pci_chipset_tag_t pc;
274 1.18.6.2 nathanw void *cookie;
275 1.18.6.2 nathanw {
276 1.18.6.2 nathanw
277 1.18.6.2 nathanw intr_disestablish(cookie);
278 1.18.6.2 nathanw }
279 1.18.6.2 nathanw
280 1.18.6.2 nathanw #define pcibus(x) \
281 1.18.6.2 nathanw (((x) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT)
282 1.18.6.2 nathanw #define pcidev(x) \
283 1.18.6.2 nathanw (((x) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT)
284 1.18.6.2 nathanw #define pcifunc(x) \
285 1.18.6.2 nathanw (((x) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT)
286 1.18.6.2 nathanw
287 1.18.6.2 nathanw void
288 1.18.6.2 nathanw fixpci(parent, pc)
289 1.18.6.2 nathanw int parent;
290 1.18.6.2 nathanw pci_chipset_tag_t pc;
291 1.18.6.2 nathanw {
292 1.18.6.2 nathanw int node;
293 1.18.6.2 nathanw pcitag_t tag;
294 1.18.6.2 nathanw pcireg_t csr, intr;
295 1.18.6.2 nathanw int len, i;
296 1.18.6.2 nathanw int32_t irqs[4];
297 1.18.6.2 nathanw struct {
298 1.18.6.2 nathanw u_int32_t phys_hi, phys_mid, phys_lo;
299 1.18.6.2 nathanw u_int32_t size_hi, size_lo;
300 1.18.6.2 nathanw } addr[8];
301 1.18.6.2 nathanw
302 1.18.6.2 nathanw for (node = OF_child(parent); node; node = OF_peer(node)) {
303 1.18.6.2 nathanw len = OF_getprop(node, "assigned-addresses", addr,
304 1.18.6.2 nathanw sizeof(addr));
305 1.18.6.2 nathanw if (len < (int)sizeof(addr[0]))
306 1.18.6.2 nathanw continue;
307 1.18.6.2 nathanw
308 1.18.6.2 nathanw tag = pci_make_tag(pc, pcibus(addr[0].phys_hi),
309 1.18.6.2 nathanw pcidev(addr[0].phys_hi),
310 1.18.6.2 nathanw pcifunc(addr[0].phys_hi));
311 1.18.6.2 nathanw
312 1.18.6.2 nathanw /*
313 1.18.6.2 nathanw * Make sure the IO and MEM enable bits are set in the CSR.
314 1.18.6.2 nathanw */
315 1.18.6.2 nathanw csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
316 1.18.6.2 nathanw csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
317 1.18.6.2 nathanw
318 1.18.6.2 nathanw for (i = 0; i < len / sizeof(addr[0]); i++) {
319 1.18.6.2 nathanw switch (addr[i].phys_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
320 1.18.6.2 nathanw case OFW_PCI_PHYS_HI_SPACE_IO:
321 1.18.6.2 nathanw csr |= PCI_COMMAND_IO_ENABLE;
322 1.18.6.2 nathanw break;
323 1.18.6.2 nathanw
324 1.18.6.2 nathanw case OFW_PCI_PHYS_HI_SPACE_MEM32:
325 1.18.6.2 nathanw case OFW_PCI_PHYS_HI_SPACE_MEM64:
326 1.18.6.2 nathanw csr |= PCI_COMMAND_MEM_ENABLE;
327 1.18.6.2 nathanw break;
328 1.18.6.2 nathanw }
329 1.18.6.2 nathanw }
330 1.18.6.2 nathanw
331 1.18.6.2 nathanw pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
332 1.18.6.2 nathanw
333 1.18.6.2 nathanw /*
334 1.18.6.2 nathanw * Make sure the line register is programmed with the
335 1.18.6.2 nathanw * interrupt mapping.
336 1.18.6.2 nathanw */
337 1.18.6.2 nathanw if (find_node_intr(node, &addr[0].phys_hi, irqs) == -1)
338 1.18.6.2 nathanw continue;
339 1.18.6.2 nathanw
340 1.18.6.2 nathanw intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
341 1.18.6.2 nathanw intr &= ~PCI_INTERRUPT_LINE_MASK;
342 1.18.6.2 nathanw intr |= irqs[0] & PCI_INTERRUPT_LINE_MASK;
343 1.18.6.2 nathanw pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
344 1.18.6.2 nathanw }
345 1.18.6.2 nathanw }
346 1.18.6.2 nathanw
347 1.18.6.2 nathanw /*
348 1.18.6.2 nathanw * Find PCI IRQ of the node from OF tree.
349 1.18.6.2 nathanw */
350 1.18.6.2 nathanw int
351 1.18.6.2 nathanw find_node_intr(node, addr, intr)
352 1.18.6.2 nathanw int node;
353 1.18.6.2 nathanw u_int32_t *addr, *intr;
354 1.18.6.2 nathanw {
355 1.18.6.2 nathanw int parent, len, mlen, iparent;
356 1.18.6.2 nathanw int match, i;
357 1.18.6.2 nathanw u_int32_t map[160], *mp;
358 1.18.6.2 nathanw u_int32_t imask[8], maskedaddr[8];
359 1.18.6.2 nathanw u_int32_t icells;
360 1.18.6.2 nathanw char name[32];
361 1.18.6.2 nathanw
362 1.18.6.2 nathanw len = OF_getprop(node, "AAPL,interrupts", intr, 4) ;
363 1.18.6.2 nathanw if (len == 4)
364 1.18.6.2 nathanw return len;
365 1.18.6.2 nathanw
366 1.18.6.2 nathanw parent = OF_parent(node);
367 1.18.6.2 nathanw len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
368 1.18.6.2 nathanw mlen = OF_getprop(parent, "interrupt-map-mask", imask, sizeof(imask));
369 1.18.6.2 nathanw
370 1.18.6.2 nathanw if (len == -1 || mlen == -1)
371 1.18.6.2 nathanw goto nomap;
372 1.18.6.2 nathanw
373 1.18.6.2 nathanw #ifdef DIAGNOSTIC
374 1.18.6.2 nathanw if (mlen == sizeof(imask)) {
375 1.18.6.2 nathanw printf("interrupt-map too long\n");
376 1.18.6.2 nathanw return -1;
377 1.18.6.2 nathanw }
378 1.18.6.2 nathanw #endif
379 1.18.6.2 nathanw
380 1.18.6.2 nathanw /* mask addr by "interrupt-map-mask" */
381 1.18.6.2 nathanw memcpy(maskedaddr, addr, mlen);
382 1.18.6.2 nathanw for (i = 0; i < mlen / 4; i++)
383 1.18.6.2 nathanw maskedaddr[i] &= imask[i];
384 1.18.6.2 nathanw
385 1.18.6.2 nathanw mp = map;
386 1.18.6.2 nathanw while (len > mlen) {
387 1.18.6.2 nathanw match = memcmp(maskedaddr, mp, mlen);
388 1.18.6.2 nathanw mp += mlen / 4;
389 1.18.6.2 nathanw len -= mlen;
390 1.18.6.2 nathanw
391 1.18.6.2 nathanw /*
392 1.18.6.2 nathanw * We must read "#interrupt-cells" for each time because
393 1.18.6.2 nathanw * interrupt-parent may be different.
394 1.18.6.2 nathanw */
395 1.18.6.2 nathanw iparent = *mp++;
396 1.18.6.2 nathanw len -= 4;
397 1.18.6.2 nathanw if (OF_getprop(iparent, "#interrupt-cells", &icells, 4) != 4)
398 1.18.6.2 nathanw goto nomap;
399 1.18.6.2 nathanw
400 1.18.6.2 nathanw /* Found. */
401 1.18.6.2 nathanw if (match == 0) {
402 1.18.6.2 nathanw memcpy(intr, mp, icells * 4);
403 1.18.6.2 nathanw return icells * 4;
404 1.18.6.2 nathanw }
405 1.18.6.2 nathanw
406 1.18.6.2 nathanw mp += icells;
407 1.18.6.2 nathanw len -= icells * 4;
408 1.18.6.2 nathanw }
409 1.18.6.2 nathanw
410 1.18.6.2 nathanw nomap:
411 1.18.6.2 nathanw /*
412 1.18.6.2 nathanw * If the node has no interrupt property and the parent is a
413 1.18.6.2 nathanw * pci-bridge, use parent's interrupt. This occurs on a PCI
414 1.18.6.2 nathanw * slot. (e.g. AHA-3940)
415 1.18.6.2 nathanw */
416 1.18.6.2 nathanw memset(name, 0, sizeof(name));
417 1.18.6.2 nathanw OF_getprop(parent, "name", name, sizeof(name));
418 1.18.6.2 nathanw if (strcmp(name, "pci-bridge") == 0) {
419 1.18.6.2 nathanw len = OF_getprop(parent, "AAPL,interrupts", intr, 4) ;
420 1.18.6.2 nathanw if (len == 4)
421 1.18.6.2 nathanw return len;
422 1.18.6.2 nathanw /*
423 1.18.6.2 nathanw * XXX I don't know what is the correct local address.
424 1.18.6.2 nathanw * XXX Use the first entry for now.
425 1.18.6.2 nathanw */
426 1.18.6.2 nathanw len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
427 1.18.6.2 nathanw if (len >= 36) {
428 1.18.6.2 nathanw addr = &map[5];
429 1.18.6.2 nathanw return find_node_intr(parent, addr, intr);
430 1.18.6.2 nathanw }
431 1.18.6.2 nathanw }
432 1.18.6.2 nathanw
433 1.18.6.2 nathanw /* XXX This may be wrong... */
434 1.18.6.2 nathanw len = OF_getprop(node, "interrupts", intr, 4) ;
435 1.18.6.2 nathanw if (len == 4)
436 1.18.6.2 nathanw return len;
437 1.18.6.2 nathanw
438 1.18.6.2 nathanw return -1;
439 1.18.6.2 nathanw }
440