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pci_machdep.c revision 1.2
      1 /*	$NetBSD: pci_machdep.c,v 1.2 1998/07/13 19:27:13 tsubai Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
      5  * Copyright (c) 1994 Charles Hannum.  All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. All advertising materials mentioning features or use of this software
     16  *    must display the following acknowledgement:
     17  *	This product includes software developed by Charles Hannum.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 /*
     34  * Machine-specific functions for PCI autoconfiguration.
     35  *
     36  * On PCs, there are two methods of generating PCI configuration cycles.
     37  * We try to detect the appropriate mechanism for this machine and set
     38  * up a few function pointers to access the correct method directly.
     39  *
     40  * The configuration method can be hard-coded in the config file by
     41  * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
     42  * as defined section 3.6.4.1, `Generating Configuration Cycles'.
     43  */
     44 
     45 #include <sys/types.h>
     46 #include <sys/param.h>
     47 #include <sys/time.h>
     48 #include <sys/systm.h>
     49 #include <sys/errno.h>
     50 #include <sys/device.h>
     51 
     52 #include <vm/vm.h>
     53 #include <vm/vm_kern.h>
     54 
     55 #include <machine/bus.h>
     56 #include <machine/pio.h>
     57 #include <machine/intr.h>
     58 
     59 #include <dev/pci/pcivar.h>
     60 #include <dev/pci/pcireg.h>
     61 
     62 #if 0
     63 #define	PCI_MODE1_ADDRESS_REG	0xf2800000
     64 #define	PCI_MODE1_DATA_REG	0xf2c00000
     65 #endif
     66 
     67 void
     68 pci_attach_hook(parent, self, pba)
     69 	struct device *parent, *self;
     70 	struct pcibus_attach_args *pba;
     71 {
     72 }
     73 
     74 int
     75 pci_bus_maxdevs(pc, busno)
     76 	pci_chipset_tag_t pc;
     77 	int busno;
     78 {
     79 
     80 	/*
     81 	 * Bus number is irrelevant.  Configuration Mechanism 1 is in
     82 	 * use, can have devices 0-32 (i.e. the `normal' range).
     83 	 */
     84 	return (32);
     85 }
     86 
     87 pcitag_t
     88 pci_make_tag(pc, bus, device, function)
     89 	pci_chipset_tag_t pc;
     90 	int bus, device, function;
     91 {
     92 	pcitag_t tag;
     93 
     94 	if (bus >= 256 || device >= 32 || function >= 8)
     95 		panic("pci_make_tag: bad request");
     96 
     97 	if (pc == PCI_CHIPSET_MPC106) {
     98 		tag = 0x80000000 |
     99 			(bus << 16) | (device << 11) | (function << 8);
    100 	} else {
    101 		if (device < 11)
    102 			return 0;
    103 		tag = (1 << device);
    104 	}
    105 
    106 	return tag;
    107 }
    108 
    109 void
    110 pci_decompose_tag(pc, tag, bp, dp, fp)
    111 	pci_chipset_tag_t pc;
    112 	pcitag_t tag;
    113 	int *bp, *dp, *fp;
    114 {
    115 	if (pc == PCI_CHIPSET_MPC106) {
    116 		if (bp != NULL)
    117 			*bp = (tag >> 16) & 0xff;
    118 		if (dp != NULL)
    119 			*dp = (tag >> 11) & 0x1f;
    120 		if (fp != NULL)
    121 			*fp = (tag >> 8) & 0x7;
    122 	} else {
    123 		if (bp != NULL)
    124 			*bp = 0;
    125 		if (dp != NULL)
    126 			*dp = ffs(tag) - 1;
    127 		if (fp != NULL)
    128 			*fp = 0;
    129 	}
    130 	return;
    131 }
    132 
    133 pcireg_t
    134 pci_conf_read(pc, tag, reg)
    135 	pci_chipset_tag_t pc;
    136 	pcitag_t tag;
    137 	int reg;
    138 {
    139 	pcireg_t data;
    140 	struct pci_bridge *r;
    141 
    142 	if (pc == PCI_CHIPSET_MPC106) {
    143 		r = &pci_bridges[0];
    144 
    145 		out32rb(r->addr, tag | reg);
    146 		data = in32rb(r->data);
    147 		out32rb(r->addr, 0);
    148 	} else {
    149 		r = &pci_bridges[pc];
    150 
    151 		if (tag == 0)
    152 			return 0xffffffff;
    153 
    154 		out32rb(r->addr, tag | reg);
    155 		DELAY(10);
    156 		data = in32rb(r->data);
    157 		DELAY(10);
    158 		out32rb(r->addr, 0);
    159 		DELAY(10);
    160 	}
    161 
    162 	return data;
    163 }
    164 
    165 void
    166 pci_conf_write(pc, tag, reg, data)
    167 	pci_chipset_tag_t pc;
    168 	pcitag_t tag;
    169 	int reg;
    170 	pcireg_t data;
    171 {
    172 	struct pci_bridge *r = &pci_bridges[pc];
    173 
    174 	if (pc == PCI_CHIPSET_MPC106) {
    175 		r = &pci_bridges[0];
    176 
    177 		out32rb(r->addr, tag | reg);
    178 		out32rb(r->data, data);
    179 		out32rb(r->addr, 0);
    180 	} else {
    181 		r = &pci_bridges[pc];
    182 
    183 		out32rb(r->addr, tag | reg);
    184 		DELAY(10);
    185 		out32rb(r->data, data);
    186 		DELAY(10);
    187 		out32rb(r->addr, 0);
    188 		DELAY(10);
    189 	}
    190 }
    191 
    192 int
    193 pci_intr_map(pc, intrtag, pin, line, ihp)
    194 	pci_chipset_tag_t pc;
    195 	pcitag_t intrtag;
    196 	int pin, line;
    197 	pci_intr_handle_t *ihp;
    198 {
    199 
    200 	if (pin == 0) {
    201 		/* No IRQ used. */
    202 		goto bad;
    203 	}
    204 
    205 	if (pin > 4) {
    206 		printf("pci_intr_map: bad interrupt pin %d\n", pin);
    207 		goto bad;
    208 	}
    209 
    210 	/*
    211 	 * Section 6.2.4, `Miscellaneous Functions', says that 255 means
    212 	 * `unknown' or `no connection' on a PC.  We assume that a device with
    213 	 * `no connection' either doesn't have an interrupt (in which case the
    214 	 * pin number should be 0, and would have been noticed above), or
    215 	 * wasn't configured by the BIOS (in which case we punt, since there's
    216 	 * no real way we can know how the interrupt lines are mapped in the
    217 	 * hardware).
    218 	 *
    219 	 * XXX
    220 	 * Since IRQ 0 is only used by the clock, and we can't actually be sure
    221 	 * that the BIOS did its job, we also recognize that as meaning that
    222 	 * the BIOS has not configured the device.
    223 	 */
    224 	if (line == 0 || line == 255) {
    225 		printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
    226 		goto bad;
    227 	} else {
    228 		if (line >= ICU_LEN) {
    229 			printf("pci_intr_map: bad interrupt line %d\n", line);
    230 			goto bad;
    231 		}
    232 	}
    233 
    234 	*ihp = line;
    235 	return 0;
    236 
    237 bad:
    238 	*ihp = -1;
    239 	return 1;
    240 }
    241 
    242 const char *
    243 pci_intr_string(pc, ih)
    244 	pci_chipset_tag_t pc;
    245 	pci_intr_handle_t ih;
    246 {
    247 	static char irqstr[8];		/* 4 + 2 + NULL + sanity */
    248 
    249 	if (ih == 0 || ih >= ICU_LEN)
    250 		panic("pci_intr_string: bogus handle 0x%x\n", ih);
    251 
    252 	sprintf(irqstr, "irq %d", ih);
    253 	return (irqstr);
    254 
    255 }
    256 
    257 extern void * intr_establish();
    258 extern void intr_disestablish();
    259 
    260 void *
    261 pci_intr_establish(pc, ih, level, func, arg)
    262 	pci_chipset_tag_t pc;
    263 	pci_intr_handle_t ih;
    264 	int level, (*func) __P((void *));
    265 	void *arg;
    266 {
    267 
    268 	if (ih == 0 || ih >= ICU_LEN)
    269 		panic("pci_intr_establish: bogus handle 0x%x\n", ih);
    270 
    271 	return intr_establish(ih, IST_LEVEL, level, func, arg);
    272 }
    273 
    274 void
    275 pci_intr_disestablish(pc, cookie)
    276 	pci_chipset_tag_t pc;
    277 	void *cookie;
    278 {
    279 
    280 	intr_disestablish(cookie);
    281 }
    282