pci_machdep.c revision 1.34.14.1 1 /* $NetBSD: pci_machdep.c,v 1.34.14.1 2007/05/06 05:11:41 macallan Exp $ */
2
3 /*
4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Machine-specific functions for PCI autoconfiguration.
35 *
36 * On PCs, there are two methods of generating PCI configuration cycles.
37 * We try to detect the appropriate mechanism for this machine and set
38 * up a few function pointers to access the correct method directly.
39 *
40 * The configuration method can be hard-coded in the config file by
41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.34.14.1 2007/05/06 05:11:41 macallan Exp $");
47
48 #include <sys/types.h>
49 #include <sys/param.h>
50 #include <sys/time.h>
51 #include <sys/systm.h>
52 #include <sys/errno.h>
53 #include <sys/device.h>
54
55 #include <uvm/uvm_extern.h>
56
57 #define _MACPPC_BUS_DMA_PRIVATE
58 #include <machine/bus.h>
59
60 #include <machine/autoconf.h>
61 #include <machine/pio.h>
62 #include <machine/intr.h>
63
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/ppbreg.h>
67 #include <dev/pci/pcidevs.h>
68
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_pci.h>
71
72 #include "opt_macppc.h"
73
74 static void fixpci __P((int, pci_chipset_tag_t));
75 static int find_node_intr __P((int, u_int32_t *, u_int32_t *));
76 static void fix_cardbus_bridge(int, pci_chipset_tag_t, pcitag_t);
77
78 #ifdef PB3400_CARDBUS_HACK
79 int cardbus_number = 2;
80 const char *pb3400_compat[] = {"AAPL,3400/2400", NULL};
81 #endif
82
83 pcitag_t genppc_pci_indirect_make_tag(void *, int, int, int);
84 void genppc_pci_indirect_decompose_tag(void *, pcitag_t, int *, int *, int *);
85
86 /*
87 * PCI doesn't have any special needs; just use the generic versions
88 * of these functions.
89 */
90 struct macppc_bus_dma_tag pci_bus_dma_tag = {
91 0, /* _bounce_thresh */
92 _bus_dmamap_create,
93 _bus_dmamap_destroy,
94 _bus_dmamap_load,
95 _bus_dmamap_load_mbuf,
96 _bus_dmamap_load_uio,
97 _bus_dmamap_load_raw,
98 _bus_dmamap_unload,
99 NULL, /* _dmamap_sync */
100 _bus_dmamem_alloc,
101 _bus_dmamem_free,
102 _bus_dmamem_map,
103 _bus_dmamem_unmap,
104 _bus_dmamem_mmap,
105 };
106
107 void
108 macppc_pci_attach_hook(parent, self, pba)
109 struct device *parent, *self;
110 struct pcibus_attach_args *pba;
111 {
112 pci_chipset_tag_t pc = pba->pba_pc;
113 int bus = pba->pba_bus;
114 int node, nn, sz;
115 int32_t busrange[2];
116
117 for (node = pc->pc_node; node; node = nn) {
118 sz = OF_getprop(node, "bus-range", busrange, 8);
119 if (sz == 8 && busrange[0] == bus) {
120 fixpci(node, pc);
121 return;
122 }
123 if ((nn = OF_child(node)) != 0)
124 continue;
125 while ((nn = OF_peer(node)) == 0) {
126 node = OF_parent(node);
127 if (node == pc->pc_node)
128 return; /* not found */
129 }
130 }
131 }
132
133 void
134 macppc_pci_get_chipset_tag(pci_chipset_tag_t pc)
135 {
136
137 pc->pc_conf_v = (void *)pc;
138
139 pc->pc_attach_hook = macppc_pci_attach_hook;
140 pc->pc_bus_maxdevs = genppc_pci_bus_maxdevs;
141
142 pc->pc_make_tag = genppc_pci_indirect_make_tag;
143 pc->pc_decompose_tag = genppc_pci_indirect_decompose_tag;
144
145 pc->pc_intr_v = (void *)pc;
146
147 pc->pc_intr_map = genppc_pci_intr_map;
148 pc->pc_intr_string = genppc_pci_intr_string;
149 pc->pc_intr_evcnt = genppc_pci_intr_evcnt;
150 pc->pc_intr_establish = genppc_pci_intr_establish;
151 pc->pc_intr_disestablish = genppc_pci_intr_disestablish;
152
153 pc->pc_conf_interrupt = genppc_pci_conf_interrupt;
154 pc->pc_conf_hook = genppc_pci_conf_hook;
155
156 pc->pc_bus = 0;
157 pc->pc_node = 0;
158 pc->pc_memt = 0;
159 pc->pc_iot = 0;
160 }
161
162 #define pcibus(x) \
163 (((x) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT)
164 #define pcidev(x) \
165 (((x) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT)
166 #define pcifunc(x) \
167 (((x) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT)
168
169 void
170 fixpci(parent, pc)
171 int parent;
172 pci_chipset_tag_t pc;
173 {
174 int node;
175 pcitag_t tag;
176 pcireg_t csr, intr, id, cr;
177 int len, i, ilen;
178 int32_t irqs[4];
179 struct {
180 u_int32_t phys_hi, phys_mid, phys_lo;
181 u_int32_t size_hi, size_lo;
182 } addr[8];
183 struct {
184 u_int32_t phys_hi, phys_mid, phys_lo;
185 u_int32_t icells[5];
186 } iaddr;
187
188 /*
189 * first hack - here we make the Ethernet portion of a
190 * UMAX E100 card work
191 */
192 #ifdef UMAX_E100_HACK
193 tag = pci_make_tag(pc, 0, 17, 0);
194 id = pci_conf_read(pc, tag, PCI_ID_REG);
195 if ((PCI_VENDOR(id) == PCI_VENDOR_DEC) &&
196 (PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21140)) {
197 /* this could be one */
198 pcireg_t isp, reg;
199 pcitag_t tag_isp = pci_make_tag(pc, 0, 13, 0);
200 /*
201 * here we go. We shouldn't encounter this anywhere else
202 * than on a UMAX S900 with an E100 board
203 * look at 00:0d:00 for a Qlogic ISP 1020 to
204 * make sure we really have an E100 here
205 */
206 aprint_debug("\nfound E100 candidate tlp");
207 isp = pci_conf_read(pc, tag_isp, PCI_ID_REG);
208 if ((PCI_VENDOR(isp) == PCI_VENDOR_QLOGIC) &&
209 (PCI_PRODUCT(isp) == PCI_PRODUCT_QLOGIC_ISP1020)) {
210
211 aprint_verbose("\nenabling UMAX E100 ethernet");
212
213 pci_conf_write(pc, tag, 0x14, 0x80000000);
214
215 /* now enable MMIO and busmastering */
216 reg = pci_conf_read(pc, tag,
217 PCI_COMMAND_STATUS_REG);
218 reg |= PCI_COMMAND_MEM_ENABLE |
219 PCI_COMMAND_MASTER_ENABLE;
220 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
221 reg);
222
223 /* and finally the interrupt */
224 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
225 reg &= ~PCI_INTERRUPT_LINE_MASK;
226 reg |= 23;
227 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
228 }
229 }
230 #endif
231
232 len = OF_getprop(parent, "#interrupt-cells", &ilen, sizeof(ilen));
233 if (len < 0)
234 ilen = 0;
235 for (node = OF_child(parent); node; node = OF_peer(node)) {
236 len = OF_getprop(node, "assigned-addresses", addr,
237 sizeof(addr));
238 if (len < (int)sizeof(addr[0]))
239 continue;
240
241 tag = pci_make_tag(pc, pcibus(addr[0].phys_hi),
242 pcidev(addr[0].phys_hi),
243 pcifunc(addr[0].phys_hi));
244
245 /*
246 * Make sure the IO and MEM enable bits are set in the CSR.
247 */
248 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
249 csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
250
251 for (i = 0; i < len / sizeof(addr[0]); i++) {
252 switch (addr[i].phys_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
253 case OFW_PCI_PHYS_HI_SPACE_IO:
254 csr |= PCI_COMMAND_IO_ENABLE;
255 break;
256
257 case OFW_PCI_PHYS_HI_SPACE_MEM32:
258 case OFW_PCI_PHYS_HI_SPACE_MEM64:
259 csr |= PCI_COMMAND_MEM_ENABLE;
260 break;
261 }
262 }
263
264 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
265
266 /*
267 * Make sure the line register is programmed with the
268 * interrupt mapping.
269 */
270 if (ilen == 0) {
271 /*
272 * Early Apple OFW implementation don't handle
273 * interrupts as defined by the OFW PCI bindings.
274 */
275 len = OF_getprop(node, "AAPL,interrupts", irqs, 4);
276 } else {
277 iaddr.phys_hi = addr[0].phys_hi;
278 iaddr.phys_mid = addr[0].phys_mid;
279 iaddr.phys_lo = addr[0].phys_lo;
280 /*
281 * Thankfully, PCI can only have one entry in its
282 * "interrupts" property.
283 */
284 len = OF_getprop(node, "interrupts", &iaddr.icells[0],
285 4*ilen);
286 if (len != 4*ilen)
287 continue;
288 len = find_node_intr(node, &iaddr.phys_hi, irqs);
289 }
290 if (len <= 0) {
291 /*
292 * If we still don't have an interrupt, try one
293 * more time. This case covers devices behind the
294 * PCI-PCI bridge in a UMAX S900 or similar (9500?)
295 * system. These slots all share the bridge's
296 * interrupt.
297 */
298 len = find_node_intr(node, &addr[0].phys_hi, irqs);
299 if (len <= 0)
300 continue;
301 }
302
303 /*
304 * For PowerBook 2400, 3400 and original G3:
305 * check if we have a 2nd ohare PIC - if so frob the built-in
306 * tlp's IRQ to 60
307 * first see if we have something on bus 0 device 13 and if
308 * it's a DEC 21041
309 */
310 id = pci_conf_read(pc, tag, PCI_ID_REG);
311 if ((tag == pci_make_tag(pc, 0, 13, 0)) &&
312 (PCI_VENDOR(id) == PCI_VENDOR_DEC) &&
313 (PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21041)) {
314
315 /* now look for the 2nd ohare */
316 if (OF_finddevice("/bandit/pci106b,7") != -1) {
317
318 irqs[0] = 60;
319 aprint_verbose("\nohare: frobbing tlp IRQ to 60");
320 }
321 }
322
323 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
324 intr &= ~PCI_INTERRUPT_LINE_MASK;
325 intr |= irqs[0] & PCI_INTERRUPT_LINE_MASK;
326 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
327
328 /* fix secondary bus numbers on CardBus bridges */
329 cr = pci_conf_read(pc, tag, PCI_CLASS_REG);
330 if ((PCI_CLASS(cr) == PCI_CLASS_BRIDGE) &&
331 (PCI_SUBCLASS(cr) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
332 uint32_t bi, busid;
333
334 /*
335 * we found a CardBus bridge. Check if the bus number
336 * is sane
337 */
338 bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
339 busid = bi & 0xff;
340 if (busid == 0) {
341 fix_cardbus_bridge(node, pc, tag);
342 }
343 }
344 }
345 }
346
347 static void
348 fix_cardbus_bridge(int node, pci_chipset_tag_t pc, pcitag_t tag)
349 {
350 uint32_t bus_number = 0xffffffff;
351 pcireg_t bi;
352 int bus, dev, fn, ih, len;
353 char path[256];
354
355 #if PB3400_CARDBUS_HACK
356 int root_node;
357
358 root_node = OF_finddevice("/");
359 if (of_compatible(root_node, pb3400_compat) != -1) {
360
361 bus_number = cardbus_number;
362 cardbus_number++;
363 } else {
364 #endif
365 ih = OF_open(path);
366 OF_call_method("load-ata", ih, 0, 0);
367 OF_close(ih);
368
369 OF_getprop(node, "AAPL,bus-id", &bus_number,
370 sizeof(bus_number));
371 #if PB3400_CARDBUS_HACK
372 }
373 #endif
374 if (bus_number != 0xffffffff) {
375
376 len = OF_package_to_path(node, path, sizeof(path));
377 path[len] = 0;
378 aprint_verbose("\n%s: fixing bus number to %d", path, bus_number);
379 pci_decompose_tag(pc, tag, &bus, &dev, &fn);
380 bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
381 bi &= 0xff000000;
382 /* XXX subordinate is always 32 here */
383 bi |= (bus & 0xff) | (bus_number << 8) | 0x200000;
384 pci_conf_write(pc, tag, PPB_REG_BUSINFO, bi);
385 }
386 }
387
388 /*
389 * Find PCI IRQ of the node from OF tree.
390 */
391 int
392 find_node_intr(node, addr, intr)
393 int node;
394 u_int32_t *addr, *intr;
395 {
396 int parent, len, mlen, iparent;
397 int match, i;
398 u_int32_t map[160];
399 const u_int32_t *mp;
400 u_int32_t imapmask[8], maskedaddr[8];
401 u_int32_t acells, icells;
402 char name[32];
403
404 /* XXXSL: 1st check for a interrupt-parent property */
405 if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) == sizeof(iparent))
406 {
407 /* How many cells to specify an interrupt ?? */
408 if (OF_getprop(iparent, "#interrupt-cells", &icells, 4) != 4)
409 return -1;
410
411 if (OF_getprop(node, "interrupts", &map, sizeof(map)) != (icells * 4))
412 return -1;
413
414 memcpy(intr, map, icells * 4);
415 return (icells * 4);
416 }
417
418 parent = OF_parent(node);
419 len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
420 mlen = OF_getprop(parent, "interrupt-map-mask", imapmask,
421 sizeof(imapmask));
422
423 if (mlen != -1)
424 memcpy(maskedaddr, addr, mlen);
425 again:
426 if (len == -1 || mlen == -1)
427 goto nomap;
428
429 #ifdef DIAGNOSTIC
430 if (mlen == sizeof(imapmask)) {
431 aprint_error("interrupt-map too long\n");
432 return -1;
433 }
434 #endif
435
436 /* mask addr by "interrupt-map-mask" */
437 for (i = 0; i < mlen / 4; i++)
438 maskedaddr[i] &= imapmask[i];
439
440 mp = map;
441 i = 0;
442 while (len > mlen) {
443 match = memcmp(maskedaddr, mp, mlen);
444 mp += mlen / 4;
445 len -= mlen;
446
447 /*
448 * We must read "#address-cells" and "#interrupt-cells" each
449 * time because each interrupt-parent may be different.
450 */
451 iparent = *mp++;
452 len -= 4;
453 i = OF_getprop(iparent, "#address-cells", &acells, 4);
454 if (i <= 0)
455 acells = 0;
456 else if (i != 4)
457 return -1;
458 if (OF_getprop(iparent, "#interrupt-cells", &icells, 4) != 4)
459 return -1;
460
461 /* Found. */
462 if (match == 0) {
463 /*
464 * We matched on address/interrupt, but are we done?
465 */
466 if (acells == 0) { /* XXX */
467 /*
468 * If we are at the interrupt controller,
469 * we are finally done. Save the result and
470 * return.
471 */
472 memcpy(intr, mp, icells * 4);
473 return icells * 4;
474 }
475 /*
476 * We are now at an intermedia interrupt node. We
477 * need to use its interrupt mask and map the
478 * supplied address/interrupt via its map.
479 */
480 mlen = OF_getprop(iparent, "interrupt-map-mask",
481 imapmask, sizeof(imapmask));
482 #ifdef DIAGNOSTIC
483 if (mlen != (acells + icells)*4) {
484 aprint_error("interrupt-map inconsistent (%d, %d)\n",
485 mlen, (acells + icells)*4);
486 return -1;
487 }
488 #endif
489 memcpy(maskedaddr, mp, mlen);
490 len = OF_getprop(iparent, "interrupt-map", map,
491 sizeof(map));
492 goto again;
493 }
494
495 mp += (acells + icells);
496 len -= (acells + icells) * 4;
497 }
498
499 nomap:
500 /*
501 * If the node has no interrupt property and the parent is a
502 * pci-bridge, use parent's interrupt. This occurs on a PCI
503 * slot. (e.g. AHA-3940)
504 */
505 memset(name, 0, sizeof(name));
506 OF_getprop(parent, "name", name, sizeof(name));
507 if (strcmp(name, "pci-bridge") == 0) {
508 len = OF_getprop(parent, "AAPL,interrupts", intr, 4) ;
509 if (len == 4)
510 return len;
511 #if 0
512 /*
513 * XXX I don't know what is the correct local address.
514 * XXX Use the first entry for now.
515 */
516 len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
517 if (len >= 36) {
518 addr = &map[5];
519 return find_node_intr(parent, addr, intr);
520 }
521 #endif
522 }
523
524 /*
525 * If all else fails, attempt to get AAPL, interrupts property.
526 * Grackle, at least, uses this instead of above in some cases.
527 */
528 len = OF_getprop(node, "AAPL,interrupts", intr, 4) ;
529 if (len == 4)
530 return len;
531
532 return -1;
533 }
534