pci_machdep.c revision 1.34.14.3 1 /* $NetBSD: pci_machdep.c,v 1.34.14.3 2007/06/05 20:25:43 matt Exp $ */
2
3 /*
4 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
5 * Copyright (c) 1994 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Machine-specific functions for PCI autoconfiguration.
35 *
36 * On PCs, there are two methods of generating PCI configuration cycles.
37 * We try to detect the appropriate mechanism for this machine and set
38 * up a few function pointers to access the correct method directly.
39 *
40 * The configuration method can be hard-coded in the config file by
41 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode
42 * as defined section 3.6.4.1, `Generating Configuration Cycles'.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.34.14.3 2007/06/05 20:25:43 matt Exp $");
47
48 #include <sys/types.h>
49 #include <sys/param.h>
50 #include <sys/time.h>
51 #include <sys/systm.h>
52 #include <sys/errno.h>
53 #include <sys/device.h>
54
55 #include <uvm/uvm_extern.h>
56
57 #define _POWERPC_BUS_DMA_PRIVATE
58 #include <machine/bus.h>
59
60 #include <machine/autoconf.h>
61 #include <machine/pio.h>
62 #include <machine/intr.h>
63
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/ppbreg.h>
67 #include <dev/pci/pcidevs.h>
68
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_pci.h>
71
72 #include "opt_macppc.h"
73
74 static void fixpci(int, pci_chipset_tag_t);
75 static int find_node_intr(int, u_int32_t *, u_int32_t *);
76 static void fix_cardbus_bridge(int, pci_chipset_tag_t, pcitag_t);
77
78 #ifdef PB3400_CARDBUS_HACK
79 int cardbus_number = 2;
80 const char *pb3400_compat[] = {"AAPL,3400/2400", NULL};
81 #endif
82
83 pcitag_t genppc_pci_indirect_make_tag(void *, int, int, int);
84 void genppc_pci_indirect_decompose_tag(void *, pcitag_t, int *, int *, int *);
85
86 /*
87 * PCI doesn't have any special needs; just use the generic versions
88 * of these functions.
89 */
90 struct powerpc_bus_dma_tag pci_bus_dma_tag = {
91 ._dmamap_create = _bus_dmamap_create,
92 ._dmamap_destroy = _bus_dmamap_destroy,
93 ._dmamap_load = _bus_dmamap_load,
94 ._dmamap_load_mbuf = _bus_dmamap_load_mbuf,
95 ._dmamap_load_uio = _bus_dmamap_load_uio,
96 ._dmamap_load_raw = _bus_dmamap_load_raw,
97 ._dmamap_unload = _bus_dmamap_unload,
98 ._dmamap_sync = NULL,
99 ._dmamem_alloc = _bus_dmamem_alloc,
100 ._dmamem_free = _bus_dmamem_free,
101 ._dmamem_map = _bus_dmamem_map,
102 ._dmamem_unmap = _bus_dmamem_unmap,
103 ._dmamem_mmap = _bus_dmamem_mmap,
104 };
105
106 void
107 macppc_pci_attach_hook(parent, self, pba)
108 struct device *parent, *self;
109 struct pcibus_attach_args *pba;
110 {
111 pci_chipset_tag_t pc = pba->pba_pc;
112 int bus = pba->pba_bus;
113 int node, nn, sz;
114 int32_t busrange[2];
115
116 for (node = pc->pc_node; node; node = nn) {
117 sz = OF_getprop(node, "bus-range", busrange, 8);
118 if (sz == 8 && busrange[0] == bus) {
119 fixpci(node, pc);
120 return;
121 }
122 if ((nn = OF_child(node)) != 0)
123 continue;
124 while ((nn = OF_peer(node)) == 0) {
125 node = OF_parent(node);
126 if (node == pc->pc_node)
127 return; /* not found */
128 }
129 }
130 }
131
132 void
133 macppc_pci_get_chipset_tag(pci_chipset_tag_t pc)
134 {
135
136 pc->pc_conf_v = (void *)pc;
137
138 pc->pc_attach_hook = macppc_pci_attach_hook;
139 pc->pc_bus_maxdevs = genppc_pci_bus_maxdevs;
140
141 pc->pc_make_tag = genppc_pci_indirect_make_tag;
142 pc->pc_decompose_tag = genppc_pci_indirect_decompose_tag;
143
144 pc->pc_intr_v = (void *)pc;
145
146 pc->pc_intr_map = genppc_pci_intr_map;
147 pc->pc_intr_string = genppc_pci_intr_string;
148 pc->pc_intr_evcnt = genppc_pci_intr_evcnt;
149 pc->pc_intr_establish = genppc_pci_intr_establish;
150 pc->pc_intr_disestablish = genppc_pci_intr_disestablish;
151
152 pc->pc_conf_interrupt = genppc_pci_conf_interrupt;
153 pc->pc_conf_hook = genppc_pci_conf_hook;
154
155 pc->pc_bus = 0;
156 pc->pc_node = 0;
157 pc->pc_memt = 0;
158 pc->pc_iot = 0;
159 }
160
161 #define pcibus(x) \
162 (((x) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT)
163 #define pcidev(x) \
164 (((x) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT)
165 #define pcifunc(x) \
166 (((x) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT)
167
168 static void
169 fixpci(int parent, pci_chipset_tag_t pc)
170 {
171 int node;
172 pcitag_t tag;
173 pcireg_t csr, intr, id, cr;
174 int len, i, ilen;
175 int32_t irqs[4];
176 struct {
177 u_int32_t phys_hi, phys_mid, phys_lo;
178 u_int32_t size_hi, size_lo;
179 } addr[8];
180 struct {
181 u_int32_t phys_hi, phys_mid, phys_lo;
182 u_int32_t icells[5];
183 } iaddr;
184
185 /*
186 * first hack - here we make the Ethernet portion of a
187 * UMAX E100 card work
188 */
189 #ifdef UMAX_E100_HACK
190 tag = pci_make_tag(pc, 0, 17, 0);
191 id = pci_conf_read(pc, tag, PCI_ID_REG);
192 if ((PCI_VENDOR(id) == PCI_VENDOR_DEC) &&
193 (PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21140)) {
194 /* this could be one */
195 pcireg_t isp, reg;
196 pcitag_t tag_isp = pci_make_tag(pc, 0, 13, 0);
197 /*
198 * here we go. We shouldn't encounter this anywhere else
199 * than on a UMAX S900 with an E100 board
200 * look at 00:0d:00 for a Qlogic ISP 1020 to
201 * make sure we really have an E100 here
202 */
203 aprint_debug("\nfound E100 candidate tlp");
204 isp = pci_conf_read(pc, tag_isp, PCI_ID_REG);
205 if ((PCI_VENDOR(isp) == PCI_VENDOR_QLOGIC) &&
206 (PCI_PRODUCT(isp) == PCI_PRODUCT_QLOGIC_ISP1020)) {
207
208 aprint_verbose("\nenabling UMAX E100 ethernet");
209
210 pci_conf_write(pc, tag, 0x14, 0x80000000);
211
212 /* now enable MMIO and busmastering */
213 reg = pci_conf_read(pc, tag,
214 PCI_COMMAND_STATUS_REG);
215 reg |= PCI_COMMAND_MEM_ENABLE |
216 PCI_COMMAND_MASTER_ENABLE;
217 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
218 reg);
219
220 /* and finally the interrupt */
221 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
222 reg &= ~PCI_INTERRUPT_LINE_MASK;
223 reg |= 23;
224 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
225 }
226 }
227 #endif
228
229 len = OF_getprop(parent, "#interrupt-cells", &ilen, sizeof(ilen));
230 if (len < 0)
231 ilen = 0;
232 for (node = OF_child(parent); node; node = OF_peer(node)) {
233 len = OF_getprop(node, "assigned-addresses", addr,
234 sizeof(addr));
235 if (len < (int)sizeof(addr[0]))
236 continue;
237
238 tag = pci_make_tag(pc, pcibus(addr[0].phys_hi),
239 pcidev(addr[0].phys_hi),
240 pcifunc(addr[0].phys_hi));
241
242 /*
243 * Make sure the IO and MEM enable bits are set in the CSR.
244 */
245 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
246 csr &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE);
247
248 for (i = 0; i < len / sizeof(addr[0]); i++) {
249 switch (addr[i].phys_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
250 case OFW_PCI_PHYS_HI_SPACE_IO:
251 csr |= PCI_COMMAND_IO_ENABLE;
252 break;
253
254 case OFW_PCI_PHYS_HI_SPACE_MEM32:
255 case OFW_PCI_PHYS_HI_SPACE_MEM64:
256 csr |= PCI_COMMAND_MEM_ENABLE;
257 break;
258 }
259 }
260
261 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
262
263 /*
264 * Make sure the line register is programmed with the
265 * interrupt mapping.
266 */
267 if (ilen == 0) {
268 /*
269 * Early Apple OFW implementation don't handle
270 * interrupts as defined by the OFW PCI bindings.
271 */
272 len = OF_getprop(node, "AAPL,interrupts", irqs, 4);
273 } else {
274 iaddr.phys_hi = addr[0].phys_hi;
275 iaddr.phys_mid = addr[0].phys_mid;
276 iaddr.phys_lo = addr[0].phys_lo;
277 /*
278 * Thankfully, PCI can only have one entry in its
279 * "interrupts" property.
280 */
281 len = OF_getprop(node, "interrupts", &iaddr.icells[0],
282 4*ilen);
283 if (len != 4*ilen)
284 continue;
285 len = find_node_intr(node, &iaddr.phys_hi, irqs);
286 }
287 if (len <= 0) {
288 /*
289 * If we still don't have an interrupt, try one
290 * more time. This case covers devices behind the
291 * PCI-PCI bridge in a UMAX S900 or similar (9500?)
292 * system. These slots all share the bridge's
293 * interrupt.
294 */
295 len = find_node_intr(node, &addr[0].phys_hi, irqs);
296 if (len <= 0)
297 continue;
298 }
299
300 /*
301 * For PowerBook 2400, 3400 and original G3:
302 * check if we have a 2nd ohare PIC - if so frob the built-in
303 * tlp's IRQ to 60
304 * first see if we have something on bus 0 device 13 and if
305 * it's a DEC 21041
306 */
307 id = pci_conf_read(pc, tag, PCI_ID_REG);
308 if ((tag == pci_make_tag(pc, 0, 13, 0)) &&
309 (PCI_VENDOR(id) == PCI_VENDOR_DEC) &&
310 (PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21041)) {
311
312 /* now look for the 2nd ohare */
313 if (OF_finddevice("/bandit/pci106b,7") != -1) {
314
315 irqs[0] = 60;
316 aprint_verbose("\nohare: frobbing tlp IRQ to 60");
317 }
318 }
319
320 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
321 intr &= ~PCI_INTERRUPT_LINE_MASK;
322 intr |= irqs[0] & PCI_INTERRUPT_LINE_MASK;
323 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr);
324
325 /* fix secondary bus numbers on CardBus bridges */
326 cr = pci_conf_read(pc, tag, PCI_CLASS_REG);
327 if ((PCI_CLASS(cr) == PCI_CLASS_BRIDGE) &&
328 (PCI_SUBCLASS(cr) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
329 uint32_t bi, busid;
330
331 /*
332 * we found a CardBus bridge. Check if the bus number
333 * is sane
334 */
335 bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
336 busid = bi & 0xff;
337 if (busid == 0) {
338 fix_cardbus_bridge(node, pc, tag);
339 }
340 }
341 }
342 }
343
344 static void
345 fix_cardbus_bridge(int node, pci_chipset_tag_t pc, pcitag_t tag)
346 {
347 uint32_t bus_number = 0xffffffff;
348 pcireg_t bi;
349 int bus, dev, fn, ih, len;
350 char path[256];
351
352 #if PB3400_CARDBUS_HACK
353 int root_node;
354
355 root_node = OF_finddevice("/");
356 if (of_compatible(root_node, pb3400_compat) != -1) {
357
358 bus_number = cardbus_number;
359 cardbus_number++;
360 } else {
361 #endif
362 ih = OF_open(path);
363 OF_call_method("load-ata", ih, 0, 0);
364 OF_close(ih);
365
366 OF_getprop(node, "AAPL,bus-id", &bus_number,
367 sizeof(bus_number));
368 #if PB3400_CARDBUS_HACK
369 }
370 #endif
371 if (bus_number != 0xffffffff) {
372
373 len = OF_package_to_path(node, path, sizeof(path));
374 path[len] = 0;
375 aprint_verbose("\n%s: fixing bus number to %d", path, bus_number);
376 pci_decompose_tag(pc, tag, &bus, &dev, &fn);
377 bi = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
378 bi &= 0xff000000;
379 /* XXX subordinate is always 32 here */
380 bi |= (bus & 0xff) | (bus_number << 8) | 0x200000;
381 pci_conf_write(pc, tag, PPB_REG_BUSINFO, bi);
382 }
383 }
384
385 /*
386 * Find PCI IRQ of the node from OF tree.
387 */
388 static int
389 find_node_intr(int node, u_int32_t *addr, uint32_t *intr)
390 {
391 int parent, len, mlen, iparent;
392 int match, i;
393 u_int32_t map[160];
394 const u_int32_t *mp;
395 u_int32_t imapmask[8], maskedaddr[8];
396 u_int32_t acells, icells;
397 char name[32];
398
399 /* XXXSL: 1st check for a interrupt-parent property */
400 if (OF_getprop(node, "interrupt-parent", &iparent, sizeof(iparent)) == sizeof(iparent))
401 {
402 /* How many cells to specify an interrupt ?? */
403 if (OF_getprop(iparent, "#interrupt-cells", &icells, 4) != 4)
404 return -1;
405
406 if (OF_getprop(node, "interrupts", &map, sizeof(map)) != (icells * 4))
407 return -1;
408
409 memcpy(intr, map, icells * 4);
410 return (icells * 4);
411 }
412
413 parent = OF_parent(node);
414 len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
415 mlen = OF_getprop(parent, "interrupt-map-mask", imapmask,
416 sizeof(imapmask));
417
418 if (mlen != -1)
419 memcpy(maskedaddr, addr, mlen);
420 again:
421 if (len == -1 || mlen == -1)
422 goto nomap;
423
424 #ifdef DIAGNOSTIC
425 if (mlen == sizeof(imapmask)) {
426 aprint_error("interrupt-map too long\n");
427 return -1;
428 }
429 #endif
430
431 /* mask addr by "interrupt-map-mask" */
432 for (i = 0; i < mlen / 4; i++)
433 maskedaddr[i] &= imapmask[i];
434
435 mp = map;
436 i = 0;
437 while (len > mlen) {
438 match = memcmp(maskedaddr, mp, mlen);
439 mp += mlen / 4;
440 len -= mlen;
441
442 /*
443 * We must read "#address-cells" and "#interrupt-cells" each
444 * time because each interrupt-parent may be different.
445 */
446 iparent = *mp++;
447 len -= 4;
448 i = OF_getprop(iparent, "#address-cells", &acells, 4);
449 if (i <= 0)
450 acells = 0;
451 else if (i != 4)
452 return -1;
453 if (OF_getprop(iparent, "#interrupt-cells", &icells, 4) != 4)
454 return -1;
455
456 /* Found. */
457 if (match == 0) {
458 /*
459 * We matched on address/interrupt, but are we done?
460 */
461 if (acells == 0) { /* XXX */
462 /*
463 * If we are at the interrupt controller,
464 * we are finally done. Save the result and
465 * return.
466 */
467 memcpy(intr, mp, icells * 4);
468 return icells * 4;
469 }
470 /*
471 * We are now at an intermedia interrupt node. We
472 * need to use its interrupt mask and map the
473 * supplied address/interrupt via its map.
474 */
475 mlen = OF_getprop(iparent, "interrupt-map-mask",
476 imapmask, sizeof(imapmask));
477 #ifdef DIAGNOSTIC
478 if (mlen != (acells + icells)*4) {
479 aprint_error("interrupt-map inconsistent (%d, %d)\n",
480 mlen, (acells + icells)*4);
481 return -1;
482 }
483 #endif
484 memcpy(maskedaddr, mp, mlen);
485 len = OF_getprop(iparent, "interrupt-map", map,
486 sizeof(map));
487 goto again;
488 }
489
490 mp += (acells + icells);
491 len -= (acells + icells) * 4;
492 }
493
494 nomap:
495 /*
496 * If the node has no interrupt property and the parent is a
497 * pci-bridge, use parent's interrupt. This occurs on a PCI
498 * slot. (e.g. AHA-3940)
499 */
500 memset(name, 0, sizeof(name));
501 OF_getprop(parent, "name", name, sizeof(name));
502 if (strcmp(name, "pci-bridge") == 0) {
503 len = OF_getprop(parent, "AAPL,interrupts", intr, 4) ;
504 if (len == 4)
505 return len;
506 #if 0
507 /*
508 * XXX I don't know what is the correct local address.
509 * XXX Use the first entry for now.
510 */
511 len = OF_getprop(parent, "interrupt-map", map, sizeof(map));
512 if (len >= 36) {
513 addr = &map[5];
514 return find_node_intr(parent, addr, intr);
515 }
516 #endif
517 }
518
519 /*
520 * If all else fails, attempt to get AAPL, interrupts property.
521 * Grackle, at least, uses this instead of above in some cases.
522 */
523 len = OF_getprop(node, "AAPL,interrupts", intr, 4) ;
524 if (len == 4)
525 return len;
526
527 return -1;
528 }
529