uninorth.c revision 1.21
1 /* $NetBSD: uninorth.c,v 1.21 2021/04/24 23:36:41 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: uninorth.c,v 1.21 2021/04/24 23:36:41 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/ofw/openfirm.h> 38 #include <dev/ofw/ofw_pci.h> 39 #include <powerpc/oea/cpufeat.h> 40 41 #include <machine/autoconf.h> 42 #include <machine/pio.h> 43 44 struct uninorth_softc { 45 device_t sc_dev; 46 struct genppc_pci_chipset sc_pc; 47 struct powerpc_bus_space sc_iot; 48 struct powerpc_bus_space sc_memt; 49 }; 50 51 static void uninorth_attach(device_t, device_t, void *); 52 static int uninorth_match(device_t, cfdata_t, void *); 53 54 static pcireg_t uninorth_conf_read(void *, pcitag_t, int); 55 static void uninorth_conf_write(void *, pcitag_t, int, pcireg_t); 56 static pcireg_t uninorth_conf_read_v3(void *, pcitag_t, int); 57 static void uninorth_conf_write_v3(void *, pcitag_t, int, pcireg_t); 58 59 CFATTACH_DECL_NEW(uninorth, sizeof(struct uninorth_softc), 60 uninorth_match, uninorth_attach, NULL, NULL); 61 62 static int 63 uninorth_match(device_t parent, cfdata_t cf, void *aux) 64 { 65 struct confargs *ca = aux; 66 char compat[32]; 67 68 if (strcmp(ca->ca_name, "pci") != 0) 69 return 0; 70 71 memset(compat, 0, sizeof(compat)); 72 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 73 if (strcmp(compat, "uni-north") != 0 && 74 strcmp(compat, "u3-agp") != 0 && 75 strcmp(compat, "u4-pcie") != 0) 76 return 0; 77 78 return 1; 79 } 80 81 static void 82 uninorth_attach(device_t parent, device_t self, void *aux) 83 { 84 struct uninorth_softc *sc = device_private(self); 85 pci_chipset_tag_t pc = &sc->sc_pc; 86 struct confargs *ca = aux; 87 struct pcibus_attach_args pba; 88 int len, child, node = ca->ca_node; 89 uint32_t reg[2], busrange[2]; 90 char compat[32]; 91 int ver; 92 struct ranges { 93 uint32_t pci_hi, pci_mid, pci_lo; 94 uint32_t host; 95 uint32_t size_hi, size_lo; 96 } ranges[6], *rp = ranges; 97 98 printf("\n"); 99 sc->sc_dev = self; 100 101 memset(compat, 0, sizeof(compat)); 102 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 103 if (strcmp(compat, "u3-agp") == 0) 104 ver = 3; 105 else if (strcmp(compat, "u4-pcie") == 0) 106 ver = 4; 107 else 108 ver = 0; 109 110 /* UniNorth address */ 111 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 112 return; 113 114 /* PCI bus number */ 115 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8) 116 return; 117 118 memset(&sc->sc_iot, 0, sizeof(sc->sc_iot)); 119 120 /* find i/o tag */ 121 len = OF_getprop(node, "ranges", ranges, sizeof(ranges)); 122 if (len == -1) 123 return; 124 while (len >= sizeof(ranges[0])) { 125 if ((rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 126 OFW_PCI_PHYS_HI_SPACE_IO) { 127 sc->sc_iot.pbs_base = rp->host; 128 sc->sc_iot.pbs_limit = rp->host + rp->size_lo; 129 break; 130 } 131 len -= sizeof(ranges[0]); 132 rp++; 133 } 134 135 /* XXX enable gmac ethernet */ 136 for (child = OF_child(node); child; child = OF_peer(child)) { 137 volatile int *gmac_gbclock_en = (void *)0xf8000020; 138 139 memset(compat, 0, sizeof(compat)); 140 OF_getprop(child, "compatible", compat, sizeof(compat)); 141 if (strcmp(compat, "gmac") == 0) 142 *gmac_gbclock_en |= 0x02; 143 } 144 145 sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE; 146 sc->sc_iot.pbs_offset = 0; 147 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot, 148 "uninorth io-space") != 0) 149 panic("Can't init uninorth io tag"); 150 151 memset(&sc->sc_memt, 0, sizeof(sc->sc_memt)); 152 sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE; 153 sc->sc_memt.pbs_base = 0x00000000; 154 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt, 155 "uninorth mem-space") != 0) 156 panic("Can't init uninorth mem tag"); 157 158 macppc_pci_get_chipset_tag(pc); 159 pc->pc_node = node; 160 pc->pc_bus = busrange[0]; 161 pc->pc_iot = &sc->sc_iot; 162 pc->pc_memt = &sc->sc_memt; 163 164 if (ver < 3) { 165 pc->pc_addr = oea_mapiodev(reg[0] + 0x800000, 4); 166 pc->pc_data = oea_mapiodev(reg[0] + 0xc00000, 8); 167 pc->pc_conf_read = uninorth_conf_read; 168 pc->pc_conf_write = uninorth_conf_write; 169 } else { 170 pc->pc_addr = oea_mapiodev(reg[1] + 0x800000, 4); 171 pc->pc_data = oea_mapiodev(reg[1] + 0xc00000, 8); 172 pc->pc_conf_read = uninorth_conf_read_v3; 173 pc->pc_conf_write = uninorth_conf_write_v3; 174 } 175 176 memset(&pba, 0, sizeof(pba)); 177 pba.pba_memt = pc->pc_memt; 178 pba.pba_iot = pc->pc_iot; 179 pba.pba_dmat = &pci_bus_dma_tag; 180 pba.pba_dmat64 = NULL; 181 pba.pba_bus = pc->pc_bus; 182 pba.pba_bridgetag = NULL; 183 pba.pba_pc = pc; 184 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 185 186 config_found(self, &pba, pcibusprint, 187 CFARG_DEVHANDLE, devhandle_from_of(node), 188 CFARG_EOL); 189 } 190 191 static pcireg_t 192 uninorth_conf_read(void *cookie, pcitag_t tag, int reg) 193 { 194 pci_chipset_tag_t pc = cookie; 195 int32_t *daddr = pc->pc_data; 196 pcireg_t data; 197 int bus, dev, func, s; 198 uint32_t x; 199 200 if ((unsigned int)reg >= PCI_CONF_SIZE) 201 return (pcireg_t) -1; 202 203 /* UniNorth seems to have a 64bit data port */ 204 if (reg & 0x04) 205 daddr++; 206 207 pci_decompose_tag(pc, tag, &bus, &dev, &func); 208 209 /* 210 * bandit's minimum device number of the first bus is 11. 211 * So we behave as if there is no device when dev < 11. 212 */ 213 if (func > 7) 214 panic("pci_conf_read: func > 7"); 215 216 if (bus == pc->pc_bus) { 217 if (dev < 11) 218 return 0xffffffff; 219 x = (1 << dev) | (func << 8) | reg; 220 } else 221 x = tag | reg | 1; 222 223 s = splhigh(); 224 225 out32rb(pc->pc_addr, x); 226 in32rb(pc->pc_addr); 227 data = 0xffffffff; 228 if (!badaddr(daddr, 4)) 229 data = in32rb(daddr); 230 out32rb(pc->pc_addr, 0); 231 in32rb(pc->pc_addr); 232 splx(s); 233 234 return data; 235 } 236 237 static void 238 uninorth_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data) 239 { 240 pci_chipset_tag_t pc = cookie; 241 int32_t *daddr = pc->pc_data; 242 int bus, dev, func, s; 243 uint32_t x; 244 245 if ((unsigned int)reg >= PCI_CONF_SIZE) 246 return; 247 248 /* UniNorth seems to have a 64bit data port */ 249 if (reg & 0x04) 250 daddr++; 251 252 pci_decompose_tag(pc, tag, &bus, &dev, &func); 253 254 if (func > 7) 255 panic("pci_conf_write: func > 7"); 256 257 if (bus == pc->pc_bus) { 258 if (dev < 11) 259 panic("pci_conf_write: dev < 11"); 260 x = (1 << dev) | (func << 8) | reg; 261 } else 262 x = tag | reg | 1; 263 264 s = splhigh(); 265 266 out32rb(pc->pc_addr, x); 267 in32rb(pc->pc_addr); 268 out32rb(daddr, data); 269 out32rb(pc->pc_addr, 0); 270 in32rb(pc->pc_addr); 271 272 splx(s); 273 } 274 275 static pcireg_t 276 uninorth_conf_read_v3(void *cookie, pcitag_t tag, int reg) 277 { 278 pci_chipset_tag_t pc = cookie; 279 int32_t *daddr = pc->pc_data; 280 pcireg_t data; 281 int bus, dev, func, s; 282 uint32_t x; 283 284 if ((unsigned int)reg >= PCI_CONF_SIZE) 285 return (pcireg_t) -1; 286 287 /* UniNorth seems to have a 64bit data port */ 288 if (reg & 0x04) 289 daddr++; 290 291 pci_decompose_tag(pc, tag, &bus, &dev, &func); 292 293 if (bus == 0) { 294 if (dev < 11) return 0xffffffff; 295 x = (1 << dev) | (func << 8) | reg; 296 } else 297 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 298 /* Set extended register bits */ 299 x |= (reg >> 8) << 28; 300 301 s = splhigh(); 302 303 out32rb(pc->pc_addr, x); 304 in32rb(pc->pc_addr); 305 data = 0xffffffff; 306 if (!badaddr(daddr, 4)) { 307 data = in32rb(daddr); 308 } 309 out32rb(pc->pc_addr, 0); 310 in32rb(pc->pc_addr); 311 splx(s); 312 313 return data; 314 } 315 316 static void 317 uninorth_conf_write_v3(void *cookie, pcitag_t tag, int reg, pcireg_t data) 318 { 319 pci_chipset_tag_t pc = cookie; 320 int32_t *daddr = pc->pc_data; 321 int bus, dev, func, s; 322 uint32_t x; 323 324 if ((unsigned int)reg >= PCI_CONF_SIZE) 325 return; 326 327 /* UniNorth seems to have a 64bit data port */ 328 if (reg & 0x04) 329 daddr++; 330 331 pci_decompose_tag(pc, tag, &bus, &dev, &func); 332 333 if (bus == 0) { 334 if (dev < 11) return; 335 x = (1 << dev) | (func << 8) | reg; 336 } else 337 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 338 /* Set extended register bits */ 339 x |= (reg >> 8) << 28; 340 341 s = splhigh(); 342 343 out32rb(pc->pc_addr, x); 344 in32rb(pc->pc_addr); 345 out32rb(daddr, data); 346 out32rb(pc->pc_addr, 0); 347 in32rb(pc->pc_addr); 348 349 splx(s); 350 } 351
Indexes created Thu Sep 25 16:09:42 GMT 2025