if_aumac.c revision 1.17.8.1
1/* $NetBSD: if_aumac.c,v 1.17.8.1 2006/11/18 21:29:25 ad Exp $ */ 2 3/* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48#include <sys/cdefs.h> 49__KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.17.8.1 2006/11/18 21:29:25 ad Exp $"); 50 51#include "bpfilter.h" 52#include "rnd.h" 53 54#include <sys/param.h> 55#include <sys/systm.h> 56#include <sys/callout.h> 57#include <sys/mbuf.h> 58#include <sys/malloc.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/ioctl.h> 62#include <sys/errno.h> 63#include <sys/device.h> 64#include <sys/queue.h> 65 66#include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 67 68#include <net/if.h> 69#include <net/if_dl.h> 70#include <net/if_media.h> 71#include <net/if_ether.h> 72 73#if NBPFILTER > 0 74#include <net/bpf.h> 75#endif 76#if NRND > 0 77#include <sys/rnd.h> 78#endif 79 80#include <machine/bus.h> 81#include <machine/intr.h> 82#include <machine/endian.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <mips/alchemy/include/aureg.h> 88#include <mips/alchemy/include/auvar.h> 89#include <mips/alchemy/include/aubusvar.h> 90#include <mips/alchemy/dev/if_aumacreg.h> 91 92/* 93 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 94 * must consist of a single DMA segment, and must be aligned to a 2K 95 * boundary. Therefore, this driver does not perform DMA directly 96 * to/from mbufs. Instead, we copy the data to/from buffers allocated 97 * at device attach time. 98 * 99 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 100 * there's little point in not making assumptions based on the CPU type. 101 * We also program the Au1X00 cache to be DMA coherent, so the buffers 102 * are accessed via KSEG0 addresses. 103 */ 104#define AUMAC_NTXDESC 4 105#define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 106 107#define AUMAC_NRXDESC 4 108#define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 109 110#define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 111#define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 112 113#define AUMAC_TXBUF_OFFSET 0 114#define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 115#define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 116 117struct aumac_buf { 118 caddr_t buf_vaddr; /* virtual address of buffer */ 119 bus_addr_t buf_paddr; /* DMA address of buffer */ 120}; 121 122/* 123 * Software state per device. 124 */ 125struct aumac_softc { 126 struct device sc_dev; /* generic device information */ 127 bus_space_tag_t sc_st; /* bus space tag */ 128 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 129 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 130 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 131 struct ethercom sc_ethercom; /* Ethernet common data */ 132 void *sc_sdhook; /* shutdown hook */ 133 134 void *sc_ih; /* interrupt cookie */ 135 136 struct mii_data sc_mii; /* MII/media information */ 137 138 struct callout sc_tick_ch; /* tick callout */ 139 140 /* Transmit and receive buffers */ 141 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 142 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 143 caddr_t sc_bufaddr; 144 145 int sc_txfree; /* number of free Tx descriptors */ 146 int sc_txnext; /* next Tx descriptor to use */ 147 int sc_txdirty; /* first dirty Tx descriptor */ 148 149 int sc_rxptr; /* next ready Rx descriptor */ 150 151#if NRND > 0 152 rndsource_element_t rnd_source; 153#endif 154 155#ifdef AUMAC_EVENT_COUNTERS 156 struct evcnt sc_ev_txstall; /* Tx stalled */ 157 struct evcnt sc_ev_rxstall; /* Rx stalled */ 158 struct evcnt sc_ev_txintr; /* Tx interrupts */ 159 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 160#endif 161 162 uint32_t sc_control; /* MAC_CONTROL contents */ 163 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 164}; 165 166#ifdef AUMAC_EVENT_COUNTERS 167#define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 168#else 169#define AUMAC_EVCNT_INCR(ev) /* nothing */ 170#endif 171 172#define AUMAC_INIT_RXDESC(sc, x) \ 173do { \ 174 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 175 MACDMA_RX_STAT((x)), 0); \ 176 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 177 MACDMA_RX_ADDR((x)), \ 178 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 179} while (/*CONSTCOND*/0) 180 181static void aumac_start(struct ifnet *); 182static void aumac_watchdog(struct ifnet *); 183static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 184static int aumac_init(struct ifnet *); 185static void aumac_stop(struct ifnet *, int); 186 187static void aumac_shutdown(void *); 188 189static void aumac_tick(void *); 190 191static void aumac_set_filter(struct aumac_softc *); 192 193static void aumac_powerup(struct aumac_softc *); 194static void aumac_powerdown(struct aumac_softc *); 195 196static int aumac_intr(void *); 197static int aumac_txintr(struct aumac_softc *); 198static int aumac_rxintr(struct aumac_softc *); 199 200static int aumac_mii_readreg(struct device *, int, int); 201static void aumac_mii_writereg(struct device *, int, int, int); 202static void aumac_mii_statchg(struct device *); 203static int aumac_mii_wait(struct aumac_softc *, const char *); 204 205static int aumac_mediachange(struct ifnet *); 206static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 207 208static int aumac_match(struct device *, struct cfdata *, void *); 209static void aumac_attach(struct device *, struct device *, void *); 210 211int aumac_copy_small = 0; 212 213CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 214 aumac_match, aumac_attach, NULL, NULL); 215 216static int 217aumac_match(struct device *parent, struct cfdata *cf, void *aux) 218{ 219 struct aubus_attach_args *aa = aux; 220 221 if (strcmp(aa->aa_name, cf->cf_name) == 0) 222 return (1); 223 224 return (0); 225} 226 227static void 228aumac_attach(struct device *parent, struct device *self, void *aux) 229{ 230 const uint8_t *enaddr; 231 prop_data_t ea; 232 struct aumac_softc *sc = (void *) self; 233 struct aubus_attach_args *aa = aux; 234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 235 struct pglist pglist; 236 paddr_t bufaddr; 237 caddr_t vbufaddr; 238 int i; 239 240 callout_init(&sc->sc_tick_ch); 241 242 printf(": Au1X00 10/100 Ethernet\n"); 243 244 sc->sc_st = aa->aa_st; 245 246 /* Get the MAC address. */ 247 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 248 if (ea == NULL) { 249 printf("%s: unable to get mac-addr property\n", 250 sc->sc_dev.dv_xname); 251 return; 252 } 253 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 254 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 255 enaddr = prop_data_data_nocopy(ea); 256 257 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 258 ether_sprintf(enaddr)); 259 260 /* Map the device. */ 261 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 262 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 263 printf("%s: unable to map MAC registers\n", 264 sc->sc_dev.dv_xname); 265 return; 266 } 267 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 268 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 269 printf("%s: unable to map MACEN registers\n", 270 sc->sc_dev.dv_xname); 271 return; 272 } 273 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 274 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 275 printf("%s: unable to map MACDMA registers\n", 276 sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* Make sure the MAC is powered off. */ 281 aumac_powerdown(sc); 282 283 /* Hook up the interrupt handler. */ 284 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 285 aumac_intr, sc); 286 if (sc->sc_ih == NULL) { 287 printf("%s: unable to register interrupt handler\n", 288 sc->sc_dev.dv_xname); 289 return; 290 } 291 292 /* 293 * Allocate space for the transmit and receive buffers. 294 */ 295 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 296 &pglist, 1, 0)) 297 return; 298 299 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 300 vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 301 302 for (i = 0; i < AUMAC_NTXDESC; i++) { 303 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 304 305 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 306 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 307 } 308 309 for (i = 0; i < AUMAC_NRXDESC; i++) { 310 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 311 312 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 313 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 314 } 315 316 /* 317 * Power up the MAC before accessing any MAC registers (including 318 * MII configuration. 319 */ 320 aumac_powerup(sc); 321 322 /* 323 * Initialize the media structures and probe the MII. 324 */ 325 sc->sc_mii.mii_ifp = ifp; 326 sc->sc_mii.mii_readreg = aumac_mii_readreg; 327 sc->sc_mii.mii_writereg = aumac_mii_writereg; 328 sc->sc_mii.mii_statchg = aumac_mii_statchg; 329 ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 330 aumac_mediastatus); 331 332 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 333 MII_OFFSET_ANY, 0); 334 335 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 336 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 337 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 338 } else 339 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 340 341 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 342 ifp->if_softc = sc; 343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 344 ifp->if_ioctl = aumac_ioctl; 345 ifp->if_start = aumac_start; 346 ifp->if_watchdog = aumac_watchdog; 347 ifp->if_init = aumac_init; 348 ifp->if_stop = aumac_stop; 349 IFQ_SET_READY(&ifp->if_snd); 350 351 /* Attach the interface. */ 352 if_attach(ifp); 353 ether_ifattach(ifp, enaddr); 354 355#if NRND > 0 356 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 357 RND_TYPE_NET, 0); 358#endif 359 360#ifdef AUMAC_EVENT_COUNTERS 361 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 362 NULL, sc->sc_dev.dv_xname, "txstall"); 363 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 364 NULL, sc->sc_dev.dv_xname, "rxstall"); 365 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 366 NULL, sc->sc_dev.dv_xname, "txintr"); 367 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 368 NULL, sc->sc_dev.dv_xname, "rxintr"); 369#endif 370 371 /* Make sure the interface is shutdown during reboot. */ 372 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 373 if (sc->sc_sdhook == NULL) 374 printf("%s: WARNING: unable to establish shutdown hook\n", 375 sc->sc_dev.dv_xname); 376 return; 377} 378 379/* 380 * aumac_shutdown: 381 * 382 * Make sure the interface is stopped at reboot time. 383 */ 384static void 385aumac_shutdown(void *arg) 386{ 387 struct aumac_softc *sc = arg; 388 389 aumac_stop(&sc->sc_ethercom.ec_if, 1); 390 391 /* 392 * XXX aumac_stop leaves device powered up at the moment 393 * XXX but this still isn't enough to keep yamon happy... :-( 394 */ 395 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 396} 397 398/* 399 * aumac_start: [ifnet interface function] 400 * 401 * Start packet transmission on the interface. 402 */ 403static void 404aumac_start(struct ifnet *ifp) 405{ 406 struct aumac_softc *sc = ifp->if_softc; 407 struct mbuf *m; 408 int nexttx; 409 410 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 411 return; 412 413 /* 414 * Loop through the send queue, setting up transmit descriptors 415 * unitl we drain the queue, or use up all available transmit 416 * descriptors. 417 */ 418 for (;;) { 419 /* Grab a packet off the queue. */ 420 IFQ_POLL(&ifp->if_snd, m); 421 if (m == NULL) 422 return; 423 424 /* Get a spare descriptor. */ 425 if (sc->sc_txfree == 0) { 426 /* No more slots left; notify upper layer. */ 427 ifp->if_flags |= IFF_OACTIVE; 428 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 429 return; 430 } 431 nexttx = sc->sc_txnext; 432 433 IFQ_DEQUEUE(&ifp->if_snd, m); 434 435 /* 436 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 437 */ 438 439 m_copydata(m, 0, m->m_pkthdr.len, 440 sc->sc_txbufs[nexttx].buf_vaddr); 441 442 /* Zero out the remainder of any short packets. */ 443 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 444 memset(sc->sc_txbufs[nexttx].buf_vaddr + 445 m->m_pkthdr.len, 0, 446 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 447 448 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 449 MACDMA_TX_STAT(nexttx), 0); 450 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 451 MACDMA_TX_LEN(nexttx), 452 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 453 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 454 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 455 MACDMA_TX_ADDR(nexttx), 456 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 457 /* XXX - needed?? we should be coherent */ 458 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 459 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 460 461 /* Advance the Tx pointer. */ 462 sc->sc_txfree--; 463 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 464 465#if NBPFILTER > 0 466 /* Pass the packet to any BPF listeners. */ 467 if (ifp->if_bpf) 468 bpf_mtap(ifp->if_bpf, m); 469#endif /* NBPFILTER */ 470 471 m_freem(m); 472 473 /* Set a watchdog timer in case the chip flakes out. */ 474 ifp->if_timer = 5; 475 } 476 /* NOTREACHED */ 477} 478 479/* 480 * aumac_watchdog: [ifnet interface function] 481 * 482 * Watchdog timer handler. 483 */ 484static void 485aumac_watchdog(struct ifnet *ifp) 486{ 487 struct aumac_softc *sc = ifp->if_softc; 488 489 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 490 (void) aumac_init(ifp); 491 492 /* Try to get more packets going. */ 493 aumac_start(ifp); 494} 495 496/* 497 * aumac_ioctl: [ifnet interface function] 498 * 499 * Handle control requests from the operator. 500 */ 501static int 502aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 503{ 504 struct aumac_softc *sc = ifp->if_softc; 505 struct ifreq *ifr = (struct ifreq *) data; 506 int s, error; 507 508 s = splnet(); 509 510 switch (cmd) { 511 case SIOCSIFMEDIA: 512 case SIOCGIFMEDIA: 513 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 514 break; 515 516 default: 517 error = ether_ioctl(ifp, cmd, data); 518 if (error == ENETRESET) { 519 /* 520 * Multicast list has changed; set the hardware filter 521 * accordingly. 522 */ 523 if (ifp->if_flags & IFF_RUNNING) 524 aumac_set_filter(sc); 525 } 526 break; 527 } 528 529 /* Try to get more packets going. */ 530 aumac_start(ifp); 531 532 splx(s); 533 return (error); 534} 535 536/* 537 * aumac_intr: 538 * 539 * Interrupt service routine. 540 */ 541static int 542aumac_intr(void *arg) 543{ 544 struct aumac_softc *sc = arg; 545 int status; 546 547 /* 548 * There aren't really any interrupt status bits on the 549 * Au1X00 MAC, and each MAC has a dedicated interrupt 550 * in the CPU's built-in interrupt controller. Just 551 * check for new incoming packets, and then Tx completions 552 * (for status updating). 553 */ 554 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 555 return (0); 556 557 status = aumac_rxintr(sc); 558 status += aumac_txintr(sc); 559 560#if NRND > 0 561 if (RND_ENABLED(&sc->rnd_source)) 562 rnd_add_uint32(&sc->rnd_source, status); 563#endif 564 565 return status; 566} 567 568/* 569 * aumac_txintr: 570 * 571 * Helper; handle transmit interrupts. 572 */ 573static int 574aumac_txintr(struct aumac_softc *sc) 575{ 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 uint32_t stat; 578 int i; 579 int pkts = 0; 580 581 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 582 i = AUMAC_NEXTTX(i)) { 583 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 584 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 585 break; 586 pkts++; 587 588 /* ACK interrupt. */ 589 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 590 MACDMA_TX_ADDR(i), 0); 591 592 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 593 MACDMA_TX_STAT(i)); 594 595 if (stat & TX_STAT_FA) { 596 /* XXX STATS */ 597 ifp->if_oerrors++; 598 } else 599 ifp->if_opackets++; 600 601 if (stat & TX_STAT_EC) 602 ifp->if_collisions += 16; 603 else 604 ifp->if_collisions += TX_STAT_CC(stat); 605 606 sc->sc_txfree++; 607 ifp->if_flags &= ~IFF_OACTIVE; 608 609 /* Try to queue more packets. */ 610 aumac_start(ifp); 611 } 612 613 if (pkts) 614 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 615 616 /* Update the dirty descriptor pointer. */ 617 sc->sc_txdirty = i; 618 619 /* 620 * If there are no more pending transmissions, cancel the watchdog 621 * timer. 622 */ 623 if (sc->sc_txfree == AUMAC_NTXDESC) 624 ifp->if_timer = 0; 625 626 return pkts; 627} 628 629/* 630 * aumac_rxintr: 631 * 632 * Helper; handle receive interrupts. 633 */ 634static int 635aumac_rxintr(struct aumac_softc *sc) 636{ 637 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 638 struct mbuf *m; 639 uint32_t stat; 640 int i, len; 641 int pkts = 0; 642 643 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 644 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 645 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 646 break; 647 pkts++; 648 649 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 650 MACDMA_RX_STAT(i)); 651 652#define PRINTERR(str) \ 653 do { \ 654 error++; \ 655 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 656 } while (0) 657 658 if (stat & RX_STAT_ERRS) { 659 int error = 0; 660 661#if 0 /* 662 * Missed frames are a semi-frequent occurence with this hardware, 663 * and reporting of them just makes everything run slower and fills 664 * the system log. Be silent. 665 * 666 * Additionally, this missed bit indicates an error with the previous 667 * packet, and not with this one! So PRINTERR is definitely wrong 668 * here. 669 * 670 * These should probably all be converted to evcnt counters anyway. 671 */ 672 if (stat & RX_STAT_MI) 673 PRINTERR("missed frame"); 674#endif 675 if (stat & RX_STAT_UC) 676 PRINTERR("unknown control frame"); 677 if (stat & RX_STAT_LE) 678 PRINTERR("short frame"); 679 if (stat & RX_STAT_CR) 680 PRINTERR("CRC error"); 681 if (stat & RX_STAT_ME) 682 PRINTERR("medium error"); 683 if (stat & RX_STAT_CS) 684 PRINTERR("late collision"); 685 if (stat & RX_STAT_FL) 686 PRINTERR("frame too big"); 687 if (stat & RX_STAT_RF) 688 PRINTERR("runt frame (collision)"); 689 if (stat & RX_STAT_WT) 690 PRINTERR("watch dog"); 691 if (stat & RX_STAT_DB) { 692 if (stat & (RX_STAT_CS | RX_STAT_RF | 693 RX_STAT_CR)) { 694 if (!error) 695 goto pktok; 696 } else 697 PRINTERR("dribbling bit"); 698 } 699#undef PRINTERR 700 ifp->if_ierrors++; 701 702 dropit: 703 /* reuse the current descriptor */ 704 AUMAC_INIT_RXDESC(sc, i); 705 continue; 706 } 707 pktok: 708 len = RX_STAT_L(stat); 709 710 /* 711 * The Au1X00 MAC includes the CRC with every packet; 712 * trim it off here. 713 */ 714 len -= ETHER_CRC_LEN; 715 716 /* 717 * Truncate the packet if it's too big to fit in 718 * a single mbuf cluster. 719 */ 720 if (len > MCLBYTES - 2) 721 len = MCLBYTES - 2; 722 723 MGETHDR(m, M_DONTWAIT, MT_DATA); 724 if (m == NULL) { 725 printf("%s: unable to allocate Rx mbuf\n", 726 sc->sc_dev.dv_xname); 727 goto dropit; 728 } 729 if (len > MHLEN - 2) { 730 MCLGET(m, M_DONTWAIT); 731 if ((m->m_flags & M_EXT) == 0) { 732 printf("%s: unable to allocate Rx cluster\n", 733 sc->sc_dev.dv_xname); 734 m_freem(m); 735 goto dropit; 736 } 737 } 738 739 m->m_data += 2; /* align payload */ 740 memcpy(mtod(m, caddr_t), 741 sc->sc_rxbufs[i].buf_vaddr, len); 742 AUMAC_INIT_RXDESC(sc, i); 743 744 m->m_pkthdr.rcvif = ifp; 745 m->m_pkthdr.len = m->m_len = len; 746 747#if NBPFILTER > 0 748 /* Pass this up to any BPF listeners. */ 749 if (ifp->if_bpf) 750 bpf_mtap(ifp->if_bpf, m); 751#endif /* NBPFILTER > 0 */ 752 753 /* Pass it on. */ 754 (*ifp->if_input)(ifp, m); 755 ifp->if_ipackets++; 756 } 757 if (pkts) 758 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 759 if (pkts == AUMAC_NRXDESC) 760 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 761 762 /* Update the receive pointer. */ 763 sc->sc_rxptr = i; 764 765 return pkts; 766} 767 768/* 769 * aumac_tick: 770 * 771 * One second timer, used to tick the MII. 772 */ 773static void 774aumac_tick(void *arg) 775{ 776 struct aumac_softc *sc = arg; 777 int s; 778 779 s = splnet(); 780 mii_tick(&sc->sc_mii); 781 splx(s); 782 783 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 784} 785 786/* 787 * aumac_init: [ifnet interface function] 788 * 789 * Initialize the interface. Must be called at splnet(). 790 */ 791static int 792aumac_init(struct ifnet *ifp) 793{ 794 struct aumac_softc *sc = ifp->if_softc; 795 int i, error = 0; 796 797 /* Cancel any pending I/O, reset MAC. */ 798 aumac_stop(ifp, 0); 799 800 /* Set up the transmit ring. */ 801 for (i = 0; i < AUMAC_NTXDESC; i++) { 802 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 803 MACDMA_TX_STAT(i), 0); 804 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 805 MACDMA_TX_LEN(i), 0); 806 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 807 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 808 } 809 sc->sc_txfree = AUMAC_NTXDESC; 810 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 811 MACDMA_TX_ADDR(0))); 812 sc->sc_txdirty = sc->sc_txnext; 813 814 /* Set up the receive ring. */ 815 for (i = 0; i < AUMAC_NRXDESC; i++) 816 AUMAC_INIT_RXDESC(sc, i); 817 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 818 MACDMA_RX_ADDR(0))); 819 820 /* 821 * Power up the MAC. 822 */ 823 aumac_powerup(sc); 824 825 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 826#if _BYTE_ORDER == _BIG_ENDIAN 827 sc->sc_control |= CONTROL_EM; 828#endif 829 830 /* Set the media. */ 831 aumac_mediachange(ifp); 832 833 /* 834 * Set the receive filter. This will actually start the transmit 835 * and receive processes. 836 */ 837 aumac_set_filter(sc); 838 839 /* Start the one second clock. */ 840 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 841 842 /* ...all done! */ 843 ifp->if_flags |= IFF_RUNNING; 844 ifp->if_flags &= ~IFF_OACTIVE; 845 846 if (error) 847 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 848 return (error); 849} 850 851/* 852 * aumac_stop: [ifnet interface function] 853 * 854 * Stop transmission on the interface. 855 */ 856static void 857aumac_stop(struct ifnet *ifp, int disable) 858{ 859 struct aumac_softc *sc = ifp->if_softc; 860 861 /* Stop the one-second clock. */ 862 callout_stop(&sc->sc_tick_ch); 863 864 /* Down the MII. */ 865 mii_down(&sc->sc_mii); 866 867 /* Stop the transmit and receive processes. */ 868 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 869 870 /* Power down/reset the MAC. */ 871 aumac_powerdown(sc); 872 873 /* Mark the interface as down and cancel the watchdog timer. */ 874 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 875 ifp->if_timer = 0; 876} 877 878/* 879 * aumac_powerdown: 880 * 881 * Power down the MAC. 882 */ 883static void 884aumac_powerdown(struct aumac_softc *sc) 885{ 886 887 /* Disable the MAC clocks, and place the device in reset. */ 888 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 889 890 // delay(10000); 891} 892 893/* 894 * aumac_powerup: 895 * 896 * Bring the device out of reset. 897 */ 898static void 899aumac_powerup(struct aumac_softc *sc) 900{ 901 902 /* Enable clocks to the MAC. */ 903 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 904 905 /* Enable MAC, coherent transactions, pass only valid frames. */ 906 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 907 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 908 909 delay(20000); 910} 911 912/* 913 * aumac_set_filter: 914 * 915 * Set up the receive filter. 916 */ 917static void 918aumac_set_filter(struct aumac_softc *sc) 919{ 920 struct ethercom *ec = &sc->sc_ethercom; 921 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 922 struct ether_multi *enm; 923 struct ether_multistep step; 924 const uint8_t *enaddr = LLADDR(ifp->if_sadl); 925 uint32_t mchash[2], crc; 926 927 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 928 929 /* Stop the receiver. */ 930 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 931 sc->sc_control & ~CONTROL_RE); 932 933 if (ifp->if_flags & IFF_PROMISC) { 934 sc->sc_control |= CONTROL_PR; 935 goto allmulti; 936 } 937 938 /* Set the station address. */ 939 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 940 enaddr[4] | (enaddr[5] << 8)); 941 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 942 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 943 (enaddr[3] << 24)); 944 945 sc->sc_control |= CONTROL_HP; 946 947 mchash[0] = mchash[1] = 0; 948 949 /* 950 * Set up the multicast address filter by passing all multicast 951 * addresses through a CRC generator, and then using the high 952 * order 6 bits as an index into the 64-bit multicast hash table. 953 * The high order bits select the word, while the rest of the bits 954 * select the bit within the word. 955 */ 956 ETHER_FIRST_MULTI(step, ec, enm); 957 while (enm != NULL) { 958 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 959 /* 960 * We must listen to a range of multicast addresses. 961 * For now, just accept all multicasts, rather than 962 * trying to set only those filter bits needed to match 963 * the range. (At this time, the only use of address 964 * ranges is for IP multicast routing, for which the 965 * range is large enough to require all bits set.) 966 */ 967 goto allmulti; 968 } 969 970 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 971 972 /* Just want the 6 most significant bits. */ 973 crc >>= 26; 974 975 /* Set the corresponding bit in the filter. */ 976 mchash[crc >> 5] |= 1U << (crc & 0x1f); 977 978 ETHER_NEXT_MULTI(step, enm); 979 } 980 981 ifp->if_flags &= ~IFF_ALLMULTI; 982 983 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 984 mchash[1]); 985 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 986 mchash[0]); 987 988 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 989 sc->sc_control); 990 return; 991 992 allmulti: 993 sc->sc_control |= CONTROL_PM; 994 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 995 sc->sc_control); 996} 997 998/* 999 * aumac_mediastatus: [ifmedia interface function] 1000 * 1001 * Get the current interface media status. 1002 */ 1003static void 1004aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1005{ 1006 struct aumac_softc *sc = ifp->if_softc; 1007 1008 mii_pollstat(&sc->sc_mii); 1009 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1010 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1011} 1012 1013/* 1014 * aumac_mediachange: [ifmedia interface function] 1015 * 1016 * Set hardware to newly selected media. 1017 */ 1018static int 1019aumac_mediachange(struct ifnet *ifp) 1020{ 1021 struct aumac_softc *sc = ifp->if_softc; 1022 1023 if (ifp->if_flags & IFF_UP) 1024 mii_mediachg(&sc->sc_mii); 1025 return (0); 1026} 1027 1028/* 1029 * aumac_mii_wait: 1030 * 1031 * Wait for the MII interface to not be busy. 1032 */ 1033static int 1034aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1035{ 1036 int i; 1037 1038 for (i = 0; i < 10000; i++) { 1039 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1040 MAC_MIICTRL) & MIICTRL_MB) == 0) 1041 return (0); 1042 delay(10); 1043 } 1044 1045 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1046 return (1); 1047} 1048 1049/* 1050 * aumac_mii_readreg: [mii interface function] 1051 * 1052 * Read a PHY register on the MII. 1053 */ 1054static int 1055aumac_mii_readreg(struct device *self, int phy, int reg) 1056{ 1057 struct aumac_softc *sc = (void *) self; 1058 1059 if (aumac_mii_wait(sc, "become ready")) 1060 return (0); 1061 1062 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1063 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1064 1065 if (aumac_mii_wait(sc, "complete")) 1066 return (0); 1067 1068 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1069 MIIDATA_MASK); 1070} 1071 1072/* 1073 * aumac_mii_writereg: [mii interface function] 1074 * 1075 * Write a PHY register on the MII. 1076 */ 1077static void 1078aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1079{ 1080 struct aumac_softc *sc = (void *) self; 1081 1082 if (aumac_mii_wait(sc, "become ready")) 1083 return; 1084 1085 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1086 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1087 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1088 1089 (void) aumac_mii_wait(sc, "complete"); 1090} 1091 1092/* 1093 * aumac_mii_statchg: [mii interface function] 1094 * 1095 * Callback from MII layer when media changes. 1096 */ 1097static void 1098aumac_mii_statchg(struct device *self) 1099{ 1100 struct aumac_softc *sc = (void *) self; 1101 1102 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1103 sc->sc_control |= CONTROL_F; 1104 else 1105 sc->sc_control &= ~CONTROL_F; 1106 1107 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1108 sc->sc_control); 1109} 1110