octeon_intc.c revision 1.3 
1/* $NetBSD: octeon_intc.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 2020 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: octeon_intc.c,v 1.3 2021/01/18 02:35:49 thorpej Exp $");
31
32#include <sys/param.h>
33#include <sys/bus.h>
34#include <sys/device.h>
35#include <sys/intr.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/kmem.h>
39
40#include <dev/fdt/fdtvar.h>
41
42#include <arch/mips/cavium/octeonvar.h>
43
44static int	octeon_intc_match(device_t, cfdata_t, void *);
45static void	octeon_intc_attach(device_t, device_t, void *);
46
47static void *	octeon_intc_establish(device_t, u_int *, int, int,
48		    int (*)(void *), void *, const char *);
49static void	octeon_intc_disestablish(device_t, void *);
50static bool	octeon_intc_intrstr(device_t, u_int *, char *, size_t);
51
52struct fdtbus_interrupt_controller_func octeon_intc_funcs = {
53	.establish = octeon_intc_establish,
54	.disestablish = octeon_intc_disestablish,
55	.intrstr = octeon_intc_intrstr
56};
57
58enum octeon_intc_type {
59	OCTEON_INTC_CIU,
60};
61
62struct octeon_intc_softc {
63	device_t		sc_dev;
64	int			sc_phandle;
65	enum octeon_intc_type	sc_type;
66	const char		*sc_descr;
67};
68
69CFATTACH_DECL_NEW(octintc, sizeof(struct octeon_intc_softc),
70	octeon_intc_match, octeon_intc_attach, NULL, NULL);
71
72static const struct device_compatible_entry compat_data[] = {
73	{ .compat = "cavium,octeon-3860-ciu",	.value = OCTEON_INTC_CIU },
74
75	{ 0 }
76};
77
78static int
79octeon_intc_match(device_t parent, cfdata_t cf, void *aux)
80{
81	struct fdt_attach_args * const faa = aux;
82
83	return of_match_compat_data(faa->faa_phandle, compat_data);
84}
85
86static void
87octeon_intc_attach(device_t parent, device_t self, void *aux)
88{
89	struct octeon_intc_softc * const sc = device_private(self);
90	struct fdt_attach_args * const faa = aux;
91	const int phandle = faa->faa_phandle;
92	int error;
93
94	sc->sc_dev = self;
95	sc->sc_phandle = phandle;
96	sc->sc_type = of_search_compatible(phandle, compat_data)->value;
97
98	switch (sc->sc_type) {
99	case OCTEON_INTC_CIU:
100		sc->sc_descr = "CIU";
101		break;
102	}
103
104	error = fdtbus_register_interrupt_controller(self, phandle,
105	    &octeon_intc_funcs);
106	if (error != 0) {
107		aprint_error(": couldn't register with fdtbus: %d\n", error);
108		return;
109	}
110
111	aprint_naive("\n");
112	aprint_normal(": %s\n", sc->sc_descr);
113}
114
115static void *
116octeon_intc_establish(device_t dev, u_int *specifier, int ipl, int flags,
117    int (*func)(void *), void *arg, const char *xname)
118{
119	struct octeon_intc_softc * const sc = device_private(dev);
120
121	/* 1st cell is the controller register (0 or 1) */
122	/* 2nd cell is the bit within the register (0..63) */
123
124	const u_int reg = be32toh(specifier[0]);
125	const u_int bit = be32toh(specifier[1]);
126	const u_int irq = (reg * 64) + bit;
127
128	if (irq >= NIRQS) {
129		aprint_error_dev(dev, "%s irq %d (%d, %d) out of range\n",
130		    sc->sc_descr, irq, reg, bit);
131		return NULL;
132	}
133
134	return octeon_intr_establish(irq, ipl, func, arg);
135}
136
137static void
138octeon_intc_disestablish(device_t dev, void *ih)
139{
140	octeon_intr_disestablish(ih);
141}
142
143static bool
144octeon_intc_intrstr(device_t dev, u_int *specifier, char *buf,
145    size_t buflen)
146{
147	struct octeon_intc_softc * const sc = device_private(dev);
148
149	/* 1st cell is the controller register (0 or 1) */
150	/* 2nd cell is the bit within the register (0..63) */
151
152	const u_int reg = be32toh(specifier[0]);
153	const u_int bit = be32toh(specifier[1]);
154	const u_int irq = (reg * 64) + bit;
155
156	snprintf(buf, buflen, "%s irq %d", sc->sc_descr, irq);
157
158	return true;
159}
160