files.alchemy revision 1.13
1 1.13 gdamore # $NetBSD: files.alchemy,v 1.13 2006/10/02 08:00:07 gdamore Exp $ 2 1.1 simonb 3 1.5 gdamore defflag opt_alchemy.h ALCHEMY_AU1000 4 1.5 gdamore ALCHEMY_AU1100 5 1.5 gdamore ALCHEMY_AU1500 6 1.5 gdamore ALCHEMY_AU1550 7 1.5 gdamore 8 1.5 gdamore file arch/mips/alchemy/au_chipdep.c 9 1.5 gdamore file arch/mips/alchemy/au1000.c alchemy_au1000 10 1.5 gdamore file arch/mips/alchemy/au1100.c alchemy_au1100 11 1.5 gdamore file arch/mips/alchemy/au1500.c alchemy_au1500 12 1.5 gdamore file arch/mips/alchemy/au1550.c alchemy_au1550 13 1.1 simonb file arch/mips/alchemy/au_icu.c 14 1.1 simonb file arch/mips/alchemy/au_timer.c 15 1.1 simonb file arch/mips/alchemy/au_cpureg_mem.c 16 1.9 gdamore #file arch/mips/alchemy/au_wired_space.c 17 1.8 gdamore file arch/mips/alchemy/au_himem_space.c 18 1.1 simonb 19 1.1 simonb # Alchemy peripheral bus 20 1.1 simonb device aubus { [addr=-1] } 21 1.1 simonb attach aubus at mainbus 22 1.1 simonb file arch/mips/alchemy/aubus.c aubus 23 1.1 simonb 24 1.1 simonb # "fake" RTC for using an Au1x00 timer for boards without a real RTC 25 1.1 simonb device aurtc 26 1.1 simonb attach aurtc at aubus 27 1.1 simonb file arch/mips/alchemy/dev/aurtc.c aurtc 28 1.1 simonb 29 1.12 gdamore # On-chip UART device 30 1.12 gdamore attach com at aubus with com_aubus 31 1.12 gdamore file arch/mips/alchemy/dev/com_aubus.c com_aubus 32 1.12 gdamore options COM_AU1x00 # Au1x00 support in com driver 33 1.12 gdamore options COM_REGMAP 34 1.1 simonb 35 1.1 simonb # On-chip ethernet device(s) 36 1.1 simonb device aumac: ether, ifnet, arp, mii 37 1.1 simonb attach aumac at aubus 38 1.1 simonb file arch/mips/alchemy/dev/if_aumac.c aumac 39 1.1 simonb 40 1.1 simonb # On-chip OHCI USB controller 41 1.1 simonb attach ohci at aubus with ohci_aubus 42 1.2 hpeyerl file arch/mips/alchemy/dev/ohci_aubus.c ohci 43 1.1 simonb 44 1.1 simonb # On-chip AC'97 audio controller 45 1.1 simonb device auaudio: audiobus, auconv, mulaw, ac97, aurateconv 46 1.1 simonb attach auaudio at aubus 47 1.1 simonb file arch/mips/alchemy/dev/auaudio.c auaudio 48 1.6 gdamore 49 1.6 gdamore # On-chip PCI 50 1.6 gdamore device aupci: pcibus 51 1.6 gdamore attach aupci at aubus 52 1.6 gdamore file arch/mips/alchemy/dev/aupci.c aupci 53 1.7 gdamore 54 1.7 gdamore # On-chip GPIO 55 1.7 gdamore device augpio: gpiobus 56 1.7 gdamore attach augpio at aubus 57 1.7 gdamore file arch/mips/alchemy/dev/augpio.c augpio 58 1.9 gdamore 59 1.10 shige # On-chip PSC 60 1.11 shige device aupsc { [ addr = -1 ] } 61 1.10 shige attach aupsc at aubus 62 1.10 shige file arch/mips/alchemy/dev/aupsc.c aupsc 63 1.10 shige 64 1.11 shige # On-chip PSC SMBus Protocol 65 1.11 shige device ausmbus: i2cbus, i2c_bitbang 66 1.11 shige attach ausmbus at aupsc 67 1.11 shige file arch/mips/alchemy/dev/ausmbus_psc.c ausmbus 68 1.11 shige 69 1.13 gdamore # On-chip PSC SPI Protocol 70 1.13 gdamore device auspi: spibus 71 1.13 gdamore attach auspi at aupsc 72 1.13 gdamore file arch/mips/alchemy/dev/auspi.c auspi needs-flag 73 1.13 gdamore 74 1.9 gdamore # On-chip PCMCIA 75 1.9 gdamore # 76 1.9 gdamore # XXX: NOTE: As of Feb. 22, 2006, the aupcmcia bus is not quite 77 1.9 gdamore # functional. Some cards have CIS misparsed, and there seems to 78 1.9 gdamore # some kind of problem with the IO address mapping. This is really 79 1.9 gdamore # for development only at this point. If you do enable this, it will 80 1.9 gdamore # generally be benign in your kernel unless you actually insert 81 1.9 gdamore # a card. After that, all bets are off! 82 1.9 gdamore # 83 1.9 gdamore device aupcmcia: pcmciabus 84 1.9 gdamore attach aupcmcia at aubus 85 1.9 gdamore file arch/mips/alchemy/dev/aupcmcia.c aupcmcia 86
Indexes created Tue Sep 23 02:09:52 GMT 2025