files.alchemy revision 1.13
11.13Sgdamore# $NetBSD: files.alchemy,v 1.13 2006/10/02 08:00:07 gdamore Exp $ 21.1Ssimonb 31.5Sgdamoredefflag opt_alchemy.h ALCHEMY_AU1000 41.5Sgdamore ALCHEMY_AU1100 51.5Sgdamore ALCHEMY_AU1500 61.5Sgdamore ALCHEMY_AU1550 71.5Sgdamore 81.5Sgdamorefile arch/mips/alchemy/au_chipdep.c 91.5Sgdamorefile arch/mips/alchemy/au1000.c alchemy_au1000 101.5Sgdamorefile arch/mips/alchemy/au1100.c alchemy_au1100 111.5Sgdamorefile arch/mips/alchemy/au1500.c alchemy_au1500 121.5Sgdamorefile arch/mips/alchemy/au1550.c alchemy_au1550 131.1Ssimonbfile arch/mips/alchemy/au_icu.c 141.1Ssimonbfile arch/mips/alchemy/au_timer.c 151.1Ssimonbfile arch/mips/alchemy/au_cpureg_mem.c 161.9Sgdamore#file arch/mips/alchemy/au_wired_space.c 171.8Sgdamorefile arch/mips/alchemy/au_himem_space.c 181.1Ssimonb 191.1Ssimonb# Alchemy peripheral bus 201.1Ssimonbdevice aubus { [addr=-1] } 211.1Ssimonbattach aubus at mainbus 221.1Ssimonbfile arch/mips/alchemy/aubus.c aubus 231.1Ssimonb 241.1Ssimonb# "fake" RTC for using an Au1x00 timer for boards without a real RTC 251.1Ssimonbdevice aurtc 261.1Ssimonbattach aurtc at aubus 271.1Ssimonbfile arch/mips/alchemy/dev/aurtc.c aurtc 281.1Ssimonb 291.12Sgdamore# On-chip UART device 301.12Sgdamoreattach com at aubus with com_aubus 311.12Sgdamorefile arch/mips/alchemy/dev/com_aubus.c com_aubus 321.12Sgdamoreoptions COM_AU1x00 # Au1x00 support in com driver 331.12Sgdamoreoptions COM_REGMAP 341.1Ssimonb 351.1Ssimonb# On-chip ethernet device(s) 361.1Ssimonbdevice aumac: ether, ifnet, arp, mii 371.1Ssimonbattach aumac at aubus 381.1Ssimonbfile arch/mips/alchemy/dev/if_aumac.c aumac 391.1Ssimonb 401.1Ssimonb# On-chip OHCI USB controller 411.1Ssimonbattach ohci at aubus with ohci_aubus 421.2Shpeyerlfile arch/mips/alchemy/dev/ohci_aubus.c ohci 431.1Ssimonb 441.1Ssimonb# On-chip AC'97 audio controller 451.1Ssimonbdevice auaudio: audiobus, auconv, mulaw, ac97, aurateconv 461.1Ssimonbattach auaudio at aubus 471.1Ssimonbfile arch/mips/alchemy/dev/auaudio.c auaudio 481.6Sgdamore 491.6Sgdamore# On-chip PCI 501.6Sgdamoredevice aupci: pcibus 511.6Sgdamoreattach aupci at aubus 521.6Sgdamorefile arch/mips/alchemy/dev/aupci.c aupci 531.7Sgdamore 541.7Sgdamore# On-chip GPIO 551.7Sgdamoredevice augpio: gpiobus 561.7Sgdamoreattach augpio at aubus 571.7Sgdamorefile arch/mips/alchemy/dev/augpio.c augpio 581.9Sgdamore 591.10Sshige# On-chip PSC 601.11Sshigedevice aupsc { [ addr = -1 ] } 611.10Sshigeattach aupsc at aubus 621.10Sshigefile arch/mips/alchemy/dev/aupsc.c aupsc 631.10Sshige 641.11Sshige# On-chip PSC SMBus Protocol 651.11Sshigedevice ausmbus: i2cbus, i2c_bitbang 661.11Sshigeattach ausmbus at aupsc 671.11Sshigefile arch/mips/alchemy/dev/ausmbus_psc.c ausmbus 681.11Sshige 691.13Sgdamore# On-chip PSC SPI Protocol 701.13Sgdamoredevice auspi: spibus 711.13Sgdamoreattach auspi at aupsc 721.13Sgdamorefile arch/mips/alchemy/dev/auspi.c auspi needs-flag 731.13Sgdamore 741.9Sgdamore# On-chip PCMCIA 751.9Sgdamore# 761.9Sgdamore# XXX: NOTE: As of Feb. 22, 2006, the aupcmcia bus is not quite 771.9Sgdamore# functional. Some cards have CIS misparsed, and there seems to 781.9Sgdamore# some kind of problem with the IO address mapping. This is really 791.9Sgdamore# for development only at this point. If you do enable this, it will 801.9Sgdamore# generally be benign in your kernel unless you actually insert 811.9Sgdamore# a card. After that, all bets are off! 821.9Sgdamore# 831.9Sgdamoredevice aupcmcia: pcmciabus 841.9Sgdamoreattach aupcmcia at aubus 851.9Sgdamorefile arch/mips/alchemy/dev/aupcmcia.c aupcmcia 86