sbtimer.c revision 1.20
1/* $NetBSD: sbtimer.c,v 1.20 2016/07/21 17:02:47 christos Exp $ */ 2 3/* 4 * Copyright 2000, 2001 5 * Broadcom Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and copied only 8 * in accordance with the following terms and conditions. Subject to these 9 * conditions, you may download, copy, install, use, modify and distribute 10 * modified or unmodified copies of this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce and 14 * retain this copyright notice and list of conditions as they appear in 15 * the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Broadcom Corporation. The "Broadcom Corporation" name may not be 19 * used to endorse or promote products derived from this software 20 * without the prior written permission of Broadcom Corporation. 21 * 22 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 25 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 26 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 27 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 32 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36__KERNEL_RCSID(0, "$NetBSD: sbtimer.c,v 1.20 2016/07/21 17:02:47 christos Exp $"); 37 38#include <sys/param.h> 39#include <sys/device.h> 40#include <sys/systm.h> 41#include <sys/kernel.h> 42#include <sys/cpu.h> 43 44#include <mips/locore.h> 45 46#include <mips/sibyte/include/sb1250_regs.h> 47#include <mips/sibyte/include/sb1250_scd.h> 48#include <mips/sibyte/dev/sbscdvar.h> 49 50struct sbtimer_softc { 51 device_t sc_dev; 52 void *sc_intrhand; 53 int sc_flags; 54 void *sc_addr_icnt, *sc_addr_cnt, *sc_addr_cfg; 55}; 56#define SBTIMER_CLOCK 1 57#define SBTIMER_STATCLOCK 2 58 59#define READ_REG(rp) mips3_ld((register_t)(rp)) 60#define WRITE_REG(rp, val) mips3_sd((register_t)(rp), (val)) 61 62static int sbtimer_match(device_t, cfdata_t, void *); 63static void sbtimer_attach(device_t, device_t, void *); 64 65CFATTACH_DECL_NEW(sbtimer, sizeof(struct sbtimer_softc), 66 sbtimer_match, sbtimer_attach, NULL, NULL); 67 68static void sbtimer_clockintr(void *arg, uint32_t status, vaddr_t pc); 69static void sbtimer_statclockintr(void *arg, uint32_t status, vaddr_t pc); 70static void sbtimer_miscintr(void *arg, uint32_t status, vaddr_t pc); 71 72static void sbtimer_clock_init(void *arg); 73 74static int 75sbtimer_match(device_t parent, cfdata_t match, void *aux) 76{ 77 struct sbscd_attach_args *sap = aux; 78 79 if (sap->sa_locs.sa_type != SBSCD_DEVTYPE_TIMER) 80 return (0); 81 82 return 1; 83} 84 85static void 86sbtimer_attach(device_t parent, device_t self, void *aux) 87{ 88 struct sbscd_attach_args *sa = aux; 89 struct sbtimer_softc *sc = device_private(self); 90 void (*fun)(void *, uint32_t, vaddr_t); 91 int ipl; 92 const char *comment = ""; 93 94 sc->sc_dev = self; 95 96 sc->sc_flags = device_cfdata(sc->sc_dev)->cf_flags; 97 sc->sc_addr_icnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base + 98 sa->sa_locs.sa_offset + R_SCD_TIMER_INIT); 99 sc->sc_addr_cnt = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base + 100 sa->sa_locs.sa_offset + R_SCD_TIMER_CNT); 101 sc->sc_addr_cfg = (uint64_t *)MIPS_PHYS_TO_KSEG1(sa->sa_base + 102 sa->sa_locs.sa_offset + R_SCD_TIMER_CFG); 103 104 aprint_normal(": "); 105 if ((sc->sc_flags & SBTIMER_CLOCK) != 0) { 106 ipl = IPL_CLOCK; 107 fun = sbtimer_clockintr; 108 109 if (system_set_clockfns(sc, sbtimer_clock_init)) { 110 /* not really the clock */ 111 sc->sc_flags &= ~SBTIMER_CLOCK; 112 comment = " (not system timer)"; 113 goto not_really; 114 } 115 aprint_normal("system timer"); 116 } else if ((sc->sc_flags & SBTIMER_STATCLOCK) != 0) { 117 ipl = IPL_HIGH; 118 fun = sbtimer_statclockintr; 119 120 /* XXX make sure it's the statclock */ 121 if (1) { 122 /* not really the statclock */ 123 sc->sc_flags &= ~SBTIMER_STATCLOCK; 124 comment = " (not system statistics timer)"; 125 goto not_really; 126 } 127 aprint_normal("system statistics timer"); 128 } else { 129not_really: 130 ipl = IPL_BIO; /* XXX -- pretty low */ 131 fun = sbtimer_miscintr; 132 aprint_normal("general-purpose timer%s", comment); 133 } 134 aprint_normal("\n"); 135 136 /* clear intr & disable timer. */ 137 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 138 139 sc->sc_intrhand = cpu_intr_establish(sa->sa_locs.sa_intr[0], ipl, 140 fun, sc); 141} 142 143static void 144sbtimer_clock_init(void *arg) 145{ 146 struct sbtimer_softc *sc = arg; 147 148 if ((1000000 % hz) == 0) { 149 aprint_normal_dev(sc->sc_dev, "%dHz system timer\n", hz); 150 } else { 151 aprint_error_dev(sc->sc_dev, 152 "cannot get %dHz clock; using 1000Hz\n", hz); 153 hz = 1000; 154 tick = 1000000 / hz; 155 } 156 157 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 158 if (G_SYS_PLL_DIV(READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_SYSTEM_CFG))) == 0) { 159 aprint_debug_dev(sc->sc_dev, 160 "PLL_DIV == 0; speeding up clock ticks for simulator\n"); 161 WRITE_REG(sc->sc_addr_icnt, (tick/100) - 1); /* XXX */ 162 } else { 163 WRITE_REG(sc->sc_addr_icnt, tick - 1); /* XXX */ 164 } 165 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */ 166} 167 168static void 169sbtimer_clockintr(void *arg, uint32_t status, vaddr_t pc) 170{ 171 struct sbtimer_softc *sc = arg; 172 struct clockframe cf; 173 174 /* clear interrupt, but leave timer enabled and in repeating mode */ 175 WRITE_REG(sc->sc_addr_cfg, 0x03); /* XXX */ 176 177 cf.pc = pc; 178 cf.sr = status; 179 cf.intr = (curcpu()->ci_idepth > 1); 180 181 hardclock(&cf); 182 183 /* 184 * We never want a CPU core clock interrupt, so adjust the CP0 185 * compare register to just before the CP0 clock register's value 186 * each time. 187 */ 188 mips3_cp0_compare_write(mips3_cp0_count_read() - 1); 189} 190 191static void 192sbtimer_statclockintr(void *arg, uint32_t status, vaddr_t pc) 193{ 194 struct sbtimer_softc *sc = arg; 195 struct clockframe cf; 196 197 /* clear intr & disable timer, reset initial count, re-enable timer */ 198 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 199 /* XXX more to do */ 200 201 cf.pc = pc; 202 cf.sr = status; 203 204 statclock(&cf); 205} 206 207static void 208sbtimer_miscintr(void *arg, uint32_t status, vaddr_t pc) 209{ 210 struct sbtimer_softc *sc = arg; 211 212 /* disable timer */ 213 WRITE_REG(sc->sc_addr_cfg, 0x00); /* XXX */ 214 215 /* XXX more to do */ 216} 217