asc.c revision 1.5.2.2
1 1.5.2.2 bouyer /* $NetBSD: asc.c,v 1.5.2.2 2000/11/20 20:14:11 bouyer Exp $ */ 2 1.5.2.2 bouyer /*- 3 1.5.2.2 bouyer * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 1.5.2.2 bouyer * All rights reserved. 5 1.5.2.2 bouyer * 6 1.5.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 7 1.5.2.2 bouyer * by Wayne Knowles 8 1.5.2.2 bouyer * 9 1.5.2.2 bouyer * Redistribution and use in source and binary forms, with or without 10 1.5.2.2 bouyer * modification, are permitted provided that the following conditions 11 1.5.2.2 bouyer * are met: 12 1.5.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 13 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer. 14 1.5.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 16 1.5.2.2 bouyer * documentation and/or other materials provided with the distribution. 17 1.5.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 18 1.5.2.2 bouyer * must display the following acknowledgement: 19 1.5.2.2 bouyer * This product includes software developed by the NetBSD 20 1.5.2.2 bouyer * Foundation, Inc. and its contributors. 21 1.5.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 22 1.5.2.2 bouyer * contributors may be used to endorse or promote products derived 23 1.5.2.2 bouyer * from this software without specific prior written permission. 24 1.5.2.2 bouyer * 25 1.5.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 1.5.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.5.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.5.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 1.5.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.5.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.5.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.5.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.5.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.5.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.5.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 36 1.5.2.2 bouyer */ 37 1.5.2.2 bouyer 38 1.5.2.2 bouyer #include <sys/types.h> 39 1.5.2.2 bouyer #include <sys/param.h> 40 1.5.2.2 bouyer #include <sys/systm.h> 41 1.5.2.2 bouyer #include <sys/kernel.h> 42 1.5.2.2 bouyer #include <sys/errno.h> 43 1.5.2.2 bouyer #include <sys/device.h> 44 1.5.2.2 bouyer #include <sys/buf.h> 45 1.5.2.2 bouyer #include <sys/malloc.h> 46 1.5.2.2 bouyer 47 1.5.2.2 bouyer #include <dev/scsipi/scsi_all.h> 48 1.5.2.2 bouyer #include <dev/scsipi/scsipi_all.h> 49 1.5.2.2 bouyer #include <dev/scsipi/scsiconf.h> 50 1.5.2.2 bouyer #include <dev/scsipi/scsi_message.h> 51 1.5.2.2 bouyer 52 1.5.2.2 bouyer #include <machine/cpu.h> 53 1.5.2.2 bouyer #include <machine/autoconf.h> 54 1.5.2.2 bouyer #include <machine/mainboard.h> 55 1.5.2.2 bouyer #include <machine/bus.h> 56 1.5.2.2 bouyer 57 1.5.2.2 bouyer #include <mipsco/obio/rambo.h> 58 1.5.2.2 bouyer 59 1.5.2.2 bouyer #include <dev/ic/ncr53c9xreg.h> 60 1.5.2.2 bouyer #include <dev/ic/ncr53c9xvar.h> 61 1.5.2.2 bouyer 62 1.5.2.2 bouyer struct asc_softc { 63 1.5.2.2 bouyer struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 1.5.2.2 bouyer struct evcnt sc_intrcnt; /* Interrupt counter */ 65 1.5.2.2 bouyer bus_space_tag_t sc_bst; 66 1.5.2.2 bouyer bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 1.5.2.2 bouyer bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 1.5.2.2 bouyer bus_dma_tag_t sc_dmat; 69 1.5.2.2 bouyer bus_dmamap_t sc_dmamap; 70 1.5.2.2 bouyer caddr_t *sc_dmaaddr; 71 1.5.2.2 bouyer size_t *sc_dmalen; 72 1.5.2.2 bouyer size_t sc_dmasize; 73 1.5.2.2 bouyer size_t sc_blkcnt; 74 1.5.2.2 bouyer int sc_flags; 75 1.5.2.2 bouyer #define DMA_IDLE 0x0 76 1.5.2.2 bouyer #define DMA_PULLUP 0x1 77 1.5.2.2 bouyer #define DMA_ACTIVE 0x2 78 1.5.2.2 bouyer #define DMA_MAPLOADED 0x4 79 1.5.2.2 bouyer u_int32_t dm_mode; 80 1.5.2.2 bouyer int dm_curseg; 81 1.5.2.2 bouyer }; 82 1.5.2.2 bouyer 83 1.5.2.2 bouyer static int ascmatch __P((struct device *, struct cfdata *, void *)); 84 1.5.2.2 bouyer static void ascattach __P((struct device *, struct device *, void *)); 85 1.5.2.2 bouyer 86 1.5.2.2 bouyer struct cfattach asc_ca = { 87 1.5.2.2 bouyer sizeof(struct asc_softc), ascmatch, ascattach 88 1.5.2.2 bouyer }; 89 1.5.2.2 bouyer 90 1.5.2.2 bouyer /* 91 1.5.2.2 bouyer * Functions and the switch for the MI code. 92 1.5.2.2 bouyer */ 93 1.5.2.2 bouyer static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 94 1.5.2.2 bouyer static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 95 1.5.2.2 bouyer static int asc_dma_isintr __P((struct ncr53c9x_softc *)); 96 1.5.2.2 bouyer static void asc_dma_reset __P((struct ncr53c9x_softc *)); 97 1.5.2.2 bouyer static int asc_dma_intr __P((struct ncr53c9x_softc *)); 98 1.5.2.2 bouyer static int asc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 99 1.5.2.2 bouyer size_t *, int, size_t *)); 100 1.5.2.2 bouyer static void asc_dma_go __P((struct ncr53c9x_softc *)); 101 1.5.2.2 bouyer static void asc_dma_stop __P((struct ncr53c9x_softc *)); 102 1.5.2.2 bouyer static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 103 1.5.2.2 bouyer 104 1.5.2.2 bouyer static struct ncr53c9x_glue asc_glue = { 105 1.5.2.2 bouyer asc_read_reg, 106 1.5.2.2 bouyer asc_write_reg, 107 1.5.2.2 bouyer asc_dma_isintr, 108 1.5.2.2 bouyer asc_dma_reset, 109 1.5.2.2 bouyer asc_dma_intr, 110 1.5.2.2 bouyer asc_dma_setup, 111 1.5.2.2 bouyer asc_dma_go, 112 1.5.2.2 bouyer asc_dma_stop, 113 1.5.2.2 bouyer asc_dma_isactive, 114 1.5.2.2 bouyer NULL, /* gl_clear_latched_intr */ 115 1.5.2.2 bouyer }; 116 1.5.2.2 bouyer 117 1.5.2.2 bouyer static int asc_intr __P((void *)); 118 1.5.2.2 bouyer 119 1.5.2.2 bouyer #define MAX_SCSI_XFER (64*1024) 120 1.5.2.2 bouyer #define MAX_DMA_SZ MAX_SCSI_XFER 121 1.5.2.2 bouyer #define DMA_SEGS (MAX_DMA_SZ/NBPG) 122 1.5.2.2 bouyer 123 1.5.2.2 bouyer static int 124 1.5.2.2 bouyer ascmatch(parent, cf, aux) 125 1.5.2.2 bouyer struct device *parent; 126 1.5.2.2 bouyer struct cfdata *cf; 127 1.5.2.2 bouyer void *aux; 128 1.5.2.2 bouyer { 129 1.5.2.2 bouyer return 1; 130 1.5.2.2 bouyer } 131 1.5.2.2 bouyer 132 1.5.2.2 bouyer static void 133 1.5.2.2 bouyer ascattach(parent, self, aux) 134 1.5.2.2 bouyer struct device *parent, *self; 135 1.5.2.2 bouyer void *aux; 136 1.5.2.2 bouyer { 137 1.5.2.2 bouyer struct confargs *ca = aux; 138 1.5.2.2 bouyer struct asc_softc *esc = (void *)self; 139 1.5.2.2 bouyer struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 140 1.5.2.2 bouyer 141 1.5.2.2 bouyer /* 142 1.5.2.2 bouyer * Set up glue for MI code early; we use some of it here. 143 1.5.2.2 bouyer */ 144 1.5.2.2 bouyer sc->sc_glue = &asc_glue; 145 1.5.2.2 bouyer 146 1.5.2.2 bouyer esc->sc_bst = ca->ca_bustag; 147 1.5.2.2 bouyer esc->sc_dmat = ca->ca_dmatag; 148 1.5.2.2 bouyer 149 1.5.2.2 bouyer if (bus_space_map(ca->ca_bustag, ca->ca_addr, 150 1.5.2.2 bouyer 16*4, /* sizeof (ncr53c9xreg) */ 151 1.5.2.2 bouyer BUS_SPACE_MAP_LINEAR, 152 1.5.2.2 bouyer &esc->sc_bsh) != 0) { 153 1.5.2.2 bouyer printf(": cannot map registers\n"); 154 1.5.2.2 bouyer return; 155 1.5.2.2 bouyer } 156 1.5.2.2 bouyer 157 1.5.2.2 bouyer if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 158 1.5.2.2 bouyer BUS_SPACE_MAP_LINEAR, 159 1.5.2.2 bouyer &esc->dm_bsh) != 0) { 160 1.5.2.2 bouyer printf(": cannot map dma registers\n"); 161 1.5.2.2 bouyer return; 162 1.5.2.2 bouyer } 163 1.5.2.2 bouyer 164 1.5.2.2 bouyer if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 165 1.5.2.2 bouyer DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 166 1.5.2.2 bouyer BUS_DMA_WAITOK, 167 1.5.2.2 bouyer &esc->sc_dmamap) != 0) { 168 1.5.2.2 bouyer printf(": failed to create dmamap\n"); 169 1.5.2.2 bouyer return; 170 1.5.2.2 bouyer } 171 1.5.2.2 bouyer 172 1.5.2.2 bouyer evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 173 1.5.2.2 bouyer self->dv_xname, "intr"); 174 1.5.2.2 bouyer 175 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 176 1.5.2.2 bouyer asc_dma_reset(sc); 177 1.5.2.2 bouyer 178 1.5.2.2 bouyer /* Other settings */ 179 1.5.2.2 bouyer sc->sc_id = 7; 180 1.5.2.2 bouyer sc->sc_freq = 24; /* 24 MHz clock */ 181 1.5.2.2 bouyer 182 1.5.2.2 bouyer /* 183 1.5.2.2 bouyer * Setup for genuine NCR 53C94 SCSI Controller 184 1.5.2.2 bouyer */ 185 1.5.2.2 bouyer 186 1.5.2.2 bouyer sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 1.5.2.2 bouyer sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 188 1.5.2.2 bouyer sc->sc_cfg3 = 0; /* NCRCFG3_CDB; */ 189 1.5.2.2 bouyer sc->sc_rev = NCR_VARIANT_NCR53C94; 190 1.5.2.2 bouyer 191 1.5.2.2 bouyer sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 192 1.5.2.2 bouyer sc->sc_maxxfer = MAX_SCSI_XFER; 193 1.5.2.2 bouyer 194 1.5.2.2 bouyer #ifdef OLDNCR 195 1.5.2.2 bouyer if (!NCR_READ_REG(sc, NCR_CFG3)) { 196 1.5.2.2 bouyer printf(" [old revision]"); 197 1.5.2.2 bouyer sc->sc_cfg2 = 0; 198 1.5.2.2 bouyer sc->sc_cfg3 = 0; 199 1.5.2.2 bouyer sc->sc_minsync = 0; 200 1.5.2.2 bouyer } 201 1.5.2.2 bouyer #endif 202 1.5.2.2 bouyer 203 1.5.2.2 bouyer ncr53c9x_dmaselect = 0; 204 1.5.2.2 bouyer ncr53c9x_attach(sc, NULL, NULL); 205 1.5.2.2 bouyer 206 1.5.2.2 bouyer bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 207 1.5.2.2 bouyer } 208 1.5.2.2 bouyer 209 1.5.2.2 bouyer /* 210 1.5.2.2 bouyer * Glue functions. 211 1.5.2.2 bouyer */ 212 1.5.2.2 bouyer 213 1.5.2.2 bouyer u_char 214 1.5.2.2 bouyer asc_read_reg(sc, reg) 215 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 216 1.5.2.2 bouyer int reg; 217 1.5.2.2 bouyer { 218 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 219 1.5.2.2 bouyer 220 1.5.2.2 bouyer return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 221 1.5.2.2 bouyer } 222 1.5.2.2 bouyer 223 1.5.2.2 bouyer void 224 1.5.2.2 bouyer asc_write_reg(sc, reg, val) 225 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 226 1.5.2.2 bouyer int reg; 227 1.5.2.2 bouyer u_char val; 228 1.5.2.2 bouyer { 229 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 230 1.5.2.2 bouyer 231 1.5.2.2 bouyer bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 232 1.5.2.2 bouyer } 233 1.5.2.2 bouyer 234 1.5.2.2 bouyer void 235 1.5.2.2 bouyer dma_status(sc) 236 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 237 1.5.2.2 bouyer { 238 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 239 1.5.2.2 bouyer int count; 240 1.5.2.2 bouyer int stat; 241 1.5.2.2 bouyer void *addr; 242 1.5.2.2 bouyer u_int32_t tc; 243 1.5.2.2 bouyer 244 1.5.2.2 bouyer tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 245 1.5.2.2 bouyer count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 246 1.5.2.2 bouyer stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 247 1.5.2.2 bouyer addr = (void *) 248 1.5.2.2 bouyer bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 249 1.5.2.2 bouyer 250 1.5.2.2 bouyer printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 251 1.5.2.2 bouyer "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 252 1.5.2.2 bouyer count, addr, stat, tc, 253 1.5.2.2 bouyer asc_read_reg(sc, NCR_STAT), 254 1.5.2.2 bouyer asc_read_reg(sc, NCR_FFLAG)); 255 1.5.2.2 bouyer } 256 1.5.2.2 bouyer 257 1.5.2.2 bouyer static __inline void 258 1.5.2.2 bouyer check_fifo(esc) 259 1.5.2.2 bouyer struct asc_softc *esc; 260 1.5.2.2 bouyer { 261 1.5.2.2 bouyer register int i=100; 262 1.5.2.2 bouyer 263 1.5.2.2 bouyer while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 264 1.5.2.2 bouyer RAMBO_MODE) & RB_FIFO_EMPTY)) { 265 1.5.2.2 bouyer DELAY(1); i--; 266 1.5.2.2 bouyer } 267 1.5.2.2 bouyer 268 1.5.2.2 bouyer if (!i) { 269 1.5.2.2 bouyer dma_status((void *)esc); 270 1.5.2.2 bouyer panic("fifo didn't flush"); 271 1.5.2.2 bouyer } 272 1.5.2.2 bouyer } 273 1.5.2.2 bouyer 274 1.5.2.2 bouyer int 275 1.5.2.2 bouyer asc_dma_isintr(sc) 276 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 277 1.5.2.2 bouyer { 278 1.5.2.2 bouyer return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 279 1.5.2.2 bouyer } 280 1.5.2.2 bouyer 281 1.5.2.2 bouyer void 282 1.5.2.2 bouyer asc_dma_reset(sc) 283 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 284 1.5.2.2 bouyer { 285 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 286 1.5.2.2 bouyer 287 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 288 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 289 1.5.2.2 bouyer RB_CLRFIFO|RB_CLRERROR); 290 1.5.2.2 bouyer DELAY(10); 291 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 292 1.5.2.2 bouyer 293 1.5.2.2 bouyer if (esc->sc_flags & DMA_MAPLOADED) 294 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 295 1.5.2.2 bouyer 296 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 297 1.5.2.2 bouyer } 298 1.5.2.2 bouyer 299 1.5.2.2 bouyer /* 300 1.5.2.2 bouyer * Setup a DMA transfer 301 1.5.2.2 bouyer */ 302 1.5.2.2 bouyer 303 1.5.2.2 bouyer static int 304 1.5.2.2 bouyer asc_dma_setup(sc, addr, len, datain, dmasize) 305 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 306 1.5.2.2 bouyer caddr_t *addr; 307 1.5.2.2 bouyer size_t *len; 308 1.5.2.2 bouyer int datain; 309 1.5.2.2 bouyer size_t *dmasize; 310 1.5.2.2 bouyer { 311 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 312 1.5.2.2 bouyer paddr_t paddr; 313 1.5.2.2 bouyer size_t count, blocks; 314 1.5.2.2 bouyer int prime, err; 315 1.5.2.2 bouyer 316 1.5.2.2 bouyer #ifdef DIAGNOSTIC 317 1.5.2.2 bouyer if (esc->sc_flags & DMA_ACTIVE) { 318 1.5.2.2 bouyer dma_status(sc); 319 1.5.2.2 bouyer panic("DMA active"); 320 1.5.2.2 bouyer } 321 1.5.2.2 bouyer #endif 322 1.5.2.2 bouyer 323 1.5.2.2 bouyer esc->sc_dmaaddr = addr; 324 1.5.2.2 bouyer esc->sc_dmalen = len; 325 1.5.2.2 bouyer esc->sc_dmasize = *dmasize; 326 1.5.2.2 bouyer esc->sc_flags = datain ? DMA_PULLUP : 0; 327 1.5.2.2 bouyer 328 1.5.2.2 bouyer NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 329 1.5.2.2 bouyer *addr, *len, datain, esc->sc_dmasize)); 330 1.5.2.2 bouyer 331 1.5.2.2 bouyer if (esc->sc_dmasize == 0) 332 1.5.2.2 bouyer return 0; 333 1.5.2.2 bouyer 334 1.5.2.2 bouyer /* have dmamap for the transfering addresses */ 335 1.5.2.2 bouyer if (err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 336 1.5.2.2 bouyer *esc->sc_dmaaddr, esc->sc_dmasize, 337 1.5.2.2 bouyer NULL /* kernel address */, 338 1.5.2.2 bouyer BUS_DMA_NOWAIT)) 339 1.5.2.2 bouyer panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 340 1.5.2.2 bouyer 341 1.5.2.2 bouyer esc->sc_flags |= DMA_MAPLOADED; 342 1.5.2.2 bouyer 343 1.5.2.2 bouyer /* No cache flush required for R3000 processors */ 344 1.5.2.2 bouyer 345 1.5.2.2 bouyer paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 346 1.5.2.2 bouyer count = esc->sc_dmamap->dm_segs[0].ds_len; 347 1.5.2.2 bouyer blocks = (((u_int32_t)*addr & 0x3f) + count + 63) >> 6; 348 1.5.2.2 bouyer 349 1.5.2.2 bouyer esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD) | RB_DMA_ENABLE; 350 1.5.2.2 bouyer if (esc->sc_dmamap->dm_nsegs > 1) 351 1.5.2.2 bouyer esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 352 1.5.2.2 bouyer 353 1.5.2.2 bouyer /* Load DMA transfer address */ 354 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 355 1.5.2.2 bouyer paddr & ~0x3f); 356 1.5.2.2 bouyer 357 1.5.2.2 bouyer /* Set count to zero bytes as this will prevent DMA from starting */ 358 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 359 1.5.2.2 bouyer 360 1.5.2.2 bouyer /* Set transfer direction and enable DMA FIFO */ 361 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 362 1.5.2.2 bouyer 363 1.5.2.2 bouyer /* If non block-aligned transfer prime FIFO manually */ 364 1.5.2.2 bouyer prime = (u_int32_t)*esc->sc_dmaaddr & 0x3f; 365 1.5.2.2 bouyer if (prime) { 366 1.5.2.2 bouyer if (esc->sc_flags & DMA_PULLUP) { 367 1.5.2.2 bouyer /* Read from NCR 53c94 controller*/ 368 1.5.2.2 bouyer u_int16_t *p; 369 1.5.2.2 bouyer 370 1.5.2.2 bouyer p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 371 1.5.2.2 bouyer bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 372 1.5.2.2 bouyer RAMBO_FIFO, p, prime>>1); 373 1.5.2.2 bouyer } else { 374 1.5.2.2 bouyer /* Fetch the first block */ 375 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, 376 1.5.2.2 bouyer RAMBO_BLKCNT, 1); 377 1.5.2.2 bouyer while (prime > 0) { 378 1.5.2.2 bouyer (void)bus_space_read_2(esc->sc_bst, 379 1.5.2.2 bouyer esc->dm_bsh, 380 1.5.2.2 bouyer RAMBO_FIFO); 381 1.5.2.2 bouyer prime -= 2; 382 1.5.2.2 bouyer } 383 1.5.2.2 bouyer blocks--; /* 1 block has been prefetched */ 384 1.5.2.2 bouyer } 385 1.5.2.2 bouyer } 386 1.5.2.2 bouyer esc->sc_blkcnt = blocks; 387 1.5.2.2 bouyer esc->dm_curseg = 0; 388 1.5.2.2 bouyer return 0; 389 1.5.2.2 bouyer } 390 1.5.2.2 bouyer 391 1.5.2.2 bouyer void 392 1.5.2.2 bouyer asc_dma_go(sc) 393 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 394 1.5.2.2 bouyer { 395 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 396 1.5.2.2 bouyer 397 1.5.2.2 bouyer /* Load block count to start transfer */ 398 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, 399 1.5.2.2 bouyer RAMBO_BLKCNT, esc->sc_blkcnt); 400 1.5.2.2 bouyer esc->sc_flags |= DMA_ACTIVE; 401 1.5.2.2 bouyer } 402 1.5.2.2 bouyer 403 1.5.2.2 bouyer int 404 1.5.2.2 bouyer asc_dma_intr(sc) 405 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 406 1.5.2.2 bouyer { 407 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 408 1.5.2.2 bouyer 409 1.5.2.2 bouyer size_t resid, len; 410 1.5.2.2 bouyer int trans; 411 1.5.2.2 bouyer u_int32_t status; 412 1.5.2.2 bouyer u_int tcl, tcm; 413 1.5.2.2 bouyer 414 1.5.2.2 bouyer #ifdef DIAGNOSTIC 415 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_ACTIVE)) { 416 1.5.2.2 bouyer dma_status(sc); 417 1.5.2.2 bouyer panic("DMA not active"); 418 1.5.2.2 bouyer } 419 1.5.2.2 bouyer #endif 420 1.5.2.2 bouyer 421 1.5.2.2 bouyer resid = 0; 422 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_PULLUP) && 423 1.5.2.2 bouyer (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 424 1.5.2.2 bouyer NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 425 1.5.2.2 bouyer DELAY(10); 426 1.5.2.2 bouyer } 427 1.5.2.2 bouyer 428 1.5.2.2 bouyer resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 429 1.5.2.2 bouyer ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 430 1.5.2.2 bouyer 431 1.5.2.2 bouyer if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 432 1.5.2.2 bouyer NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 433 1.5.2.2 bouyer return 0; 434 1.5.2.2 bouyer } 435 1.5.2.2 bouyer 436 1.5.2.2 bouyer trans = esc->sc_dmasize - resid; 437 1.5.2.2 bouyer if (trans < 0) { /* transferred < 0 ? */ 438 1.5.2.2 bouyer printf("asc_intr: xfer (%d) > req (%d)\n", 439 1.5.2.2 bouyer trans, esc->sc_dmasize); 440 1.5.2.2 bouyer trans = esc->sc_dmasize; 441 1.5.2.2 bouyer } 442 1.5.2.2 bouyer 443 1.5.2.2 bouyer NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 444 1.5.2.2 bouyer tcl, tcm, trans, resid)); 445 1.5.2.2 bouyer 446 1.5.2.2 bouyer status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 447 1.5.2.2 bouyer 448 1.5.2.2 bouyer if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 449 1.5.2.2 bouyer if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 450 1.5.2.2 bouyer paddr_t ptr; 451 1.5.2.2 bouyer u_int16_t *p; 452 1.5.2.2 bouyer 453 1.5.2.2 bouyer resid = status & 0x1f; 454 1.5.2.2 bouyer 455 1.5.2.2 bouyer /* take the address of block to fixed up */ 456 1.5.2.2 bouyer ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 457 1.5.2.2 bouyer RAMBO_CADDR); 458 1.5.2.2 bouyer /* find the starting address of fractional data */ 459 1.5.2.2 bouyer p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 460 1.5.2.2 bouyer 461 1.5.2.2 bouyer /* duplicate trailing data to FIFO for force flush */ 462 1.5.2.2 bouyer len = RB_BLK_CNT - resid; 463 1.5.2.2 bouyer bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 464 1.5.2.2 bouyer RAMBO_FIFO, p, len); 465 1.5.2.2 bouyer check_fifo(esc); 466 1.5.2.2 bouyer } else { /* SCSI Write */ 467 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 468 1.5.2.2 bouyer RAMBO_MODE, 0); 469 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 470 1.5.2.2 bouyer RAMBO_MODE, RB_CLRFIFO); 471 1.5.2.2 bouyer } 472 1.5.2.2 bouyer } 473 1.5.2.2 bouyer 474 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 475 1.5.2.2 bouyer 476 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 477 1.5.2.2 bouyer 478 1.5.2.2 bouyer bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 479 1.5.2.2 bouyer 0, esc->sc_dmasize, 480 1.5.2.2 bouyer (esc->sc_flags & DMA_PULLUP) 481 1.5.2.2 bouyer ? BUS_DMASYNC_POSTREAD 482 1.5.2.2 bouyer : BUS_DMASYNC_POSTWRITE); 483 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 484 1.5.2.2 bouyer 485 1.5.2.2 bouyer *esc->sc_dmaaddr += trans; 486 1.5.2.2 bouyer *esc->sc_dmalen -= trans; 487 1.5.2.2 bouyer 488 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 489 1.5.2.2 bouyer 490 1.5.2.2 bouyer return 0; 491 1.5.2.2 bouyer } 492 1.5.2.2 bouyer 493 1.5.2.2 bouyer 494 1.5.2.2 bouyer void 495 1.5.2.2 bouyer asc_dma_stop(sc) 496 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 497 1.5.2.2 bouyer { 498 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 499 1.5.2.2 bouyer 500 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 501 1.5.2.2 bouyer if (esc->sc_flags & DMA_MAPLOADED) 502 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 503 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 504 1.5.2.2 bouyer } 505 1.5.2.2 bouyer 506 1.5.2.2 bouyer int 507 1.5.2.2 bouyer asc_dma_isactive(sc) 508 1.5.2.2 bouyer struct ncr53c9x_softc *sc; 509 1.5.2.2 bouyer { 510 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 511 1.5.2.2 bouyer return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 512 1.5.2.2 bouyer } 513 1.5.2.2 bouyer 514 1.5.2.2 bouyer void 515 1.5.2.2 bouyer rambo_dma_chain(esc) 516 1.5.2.2 bouyer struct asc_softc *esc; 517 1.5.2.2 bouyer { 518 1.5.2.2 bouyer int seg; 519 1.5.2.2 bouyer size_t count, blocks; 520 1.5.2.2 bouyer paddr_t paddr; 521 1.5.2.2 bouyer 522 1.5.2.2 bouyer seg = ++esc->dm_curseg; 523 1.5.2.2 bouyer 524 1.5.2.2 bouyer #ifdef DIAGNOSTIC 525 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 526 1.5.2.2 bouyer panic("Unexpected DMA chaining intr"); 527 1.5.2.2 bouyer 528 1.5.2.2 bouyer /* Interrupt can only occur at terminal count, but double check */ 529 1.5.2.2 bouyer if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 530 1.5.2.2 bouyer dma_status((void *)esc); 531 1.5.2.2 bouyer panic("rambo blkcnt != 0"); 532 1.5.2.2 bouyer } 533 1.5.2.2 bouyer #endif 534 1.5.2.2 bouyer 535 1.5.2.2 bouyer paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 536 1.5.2.2 bouyer count = esc->sc_dmamap->dm_segs[seg].ds_len; 537 1.5.2.2 bouyer blocks = (count + 63) >> 6; 538 1.5.2.2 bouyer 539 1.5.2.2 bouyer /* Disable DMA interrupt if last segment */ 540 1.5.2.2 bouyer if (seg+1 > esc->sc_dmamap->dm_nsegs) { 541 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 542 1.5.2.2 bouyer RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 543 1.5.2.2 bouyer } 544 1.5.2.2 bouyer 545 1.5.2.2 bouyer /* Load transfer address for next DMA chain */ 546 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 547 1.5.2.2 bouyer 548 1.5.2.2 bouyer /* DMA restarts when we enter a new block count */ 549 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 550 1.5.2.2 bouyer } 551 1.5.2.2 bouyer 552 1.5.2.2 bouyer int 553 1.5.2.2 bouyer asc_intr(arg) 554 1.5.2.2 bouyer void *arg; 555 1.5.2.2 bouyer { 556 1.5.2.2 bouyer register u_int32_t dma_stat; 557 1.5.2.2 bouyer struct asc_softc *esc = arg; 558 1.5.2.2 bouyer struct ncr53c9x_softc *sc = arg; 559 1.5.2.2 bouyer 560 1.5.2.2 bouyer esc->sc_intrcnt.ev_count++; 561 1.5.2.2 bouyer 562 1.5.2.2 bouyer /* Check for RAMBO DMA Interrupt */ 563 1.5.2.2 bouyer dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 564 1.5.2.2 bouyer if (dma_stat & RB_INTR_PEND) { 565 1.5.2.2 bouyer rambo_dma_chain(esc); 566 1.5.2.2 bouyer } 567 1.5.2.2 bouyer /* Check for NCR 53c94 interrupt */ 568 1.5.2.2 bouyer if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 569 1.5.2.2 bouyer ncr53c9x_intr(sc); 570 1.5.2.2 bouyer } 571 1.5.2.2 bouyer return 0; 572 1.5.2.2 bouyer } 573
Indexes created Tue Oct 21 19:09:51 GMT 2025