asc.c revision 1.5.2.4
1 1.5.2.4 bouyer /* $NetBSD: asc.c,v 1.5.2.4 2001/03/12 13:29:04 bouyer Exp $ */ 2 1.5.2.2 bouyer /*- 3 1.5.2.2 bouyer * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 1.5.2.2 bouyer * All rights reserved. 5 1.5.2.2 bouyer * 6 1.5.2.2 bouyer * This code is derived from software contributed to The NetBSD Foundation 7 1.5.2.2 bouyer * by Wayne Knowles 8 1.5.2.2 bouyer * 9 1.5.2.2 bouyer * Redistribution and use in source and binary forms, with or without 10 1.5.2.2 bouyer * modification, are permitted provided that the following conditions 11 1.5.2.2 bouyer * are met: 12 1.5.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 13 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer. 14 1.5.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 16 1.5.2.2 bouyer * documentation and/or other materials provided with the distribution. 17 1.5.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 18 1.5.2.2 bouyer * must display the following acknowledgement: 19 1.5.2.2 bouyer * This product includes software developed by the NetBSD 20 1.5.2.2 bouyer * Foundation, Inc. and its contributors. 21 1.5.2.2 bouyer * 4. Neither the name of The NetBSD Foundation nor the names of its 22 1.5.2.2 bouyer * contributors may be used to endorse or promote products derived 23 1.5.2.2 bouyer * from this software without specific prior written permission. 24 1.5.2.2 bouyer * 25 1.5.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 1.5.2.2 bouyer * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 1.5.2.2 bouyer * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 1.5.2.2 bouyer * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 1.5.2.2 bouyer * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 1.5.2.2 bouyer * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 1.5.2.2 bouyer * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 1.5.2.2 bouyer * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 1.5.2.2 bouyer * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 1.5.2.2 bouyer * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 1.5.2.2 bouyer * POSSIBILITY OF SUCH DAMAGE. 36 1.5.2.2 bouyer */ 37 1.5.2.2 bouyer 38 1.5.2.2 bouyer #include <sys/types.h> 39 1.5.2.2 bouyer #include <sys/param.h> 40 1.5.2.2 bouyer #include <sys/systm.h> 41 1.5.2.2 bouyer #include <sys/kernel.h> 42 1.5.2.2 bouyer #include <sys/errno.h> 43 1.5.2.2 bouyer #include <sys/device.h> 44 1.5.2.2 bouyer #include <sys/buf.h> 45 1.5.2.2 bouyer #include <sys/malloc.h> 46 1.5.2.2 bouyer 47 1.5.2.2 bouyer #include <dev/scsipi/scsi_all.h> 48 1.5.2.2 bouyer #include <dev/scsipi/scsipi_all.h> 49 1.5.2.2 bouyer #include <dev/scsipi/scsiconf.h> 50 1.5.2.2 bouyer #include <dev/scsipi/scsi_message.h> 51 1.5.2.2 bouyer 52 1.5.2.2 bouyer #include <machine/cpu.h> 53 1.5.2.2 bouyer #include <machine/autoconf.h> 54 1.5.2.2 bouyer #include <machine/mainboard.h> 55 1.5.2.2 bouyer #include <machine/bus.h> 56 1.5.2.2 bouyer 57 1.5.2.2 bouyer #include <mipsco/obio/rambo.h> 58 1.5.2.2 bouyer 59 1.5.2.2 bouyer #include <dev/ic/ncr53c9xreg.h> 60 1.5.2.2 bouyer #include <dev/ic/ncr53c9xvar.h> 61 1.5.2.2 bouyer 62 1.5.2.2 bouyer struct asc_softc { 63 1.5.2.2 bouyer struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 1.5.2.2 bouyer struct evcnt sc_intrcnt; /* Interrupt counter */ 65 1.5.2.2 bouyer bus_space_tag_t sc_bst; 66 1.5.2.2 bouyer bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 1.5.2.2 bouyer bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 1.5.2.2 bouyer bus_dma_tag_t sc_dmat; 69 1.5.2.2 bouyer bus_dmamap_t sc_dmamap; 70 1.5.2.2 bouyer caddr_t *sc_dmaaddr; 71 1.5.2.2 bouyer size_t *sc_dmalen; 72 1.5.2.2 bouyer size_t sc_dmasize; 73 1.5.2.2 bouyer int sc_flags; 74 1.5.2.2 bouyer #define DMA_IDLE 0x0 75 1.5.2.2 bouyer #define DMA_PULLUP 0x1 76 1.5.2.2 bouyer #define DMA_ACTIVE 0x2 77 1.5.2.2 bouyer #define DMA_MAPLOADED 0x4 78 1.5.2.2 bouyer u_int32_t dm_mode; 79 1.5.2.2 bouyer int dm_curseg; 80 1.5.2.2 bouyer }; 81 1.5.2.2 bouyer 82 1.5.2.3 bouyer static int ascmatch (struct device *, struct cfdata *, void *); 83 1.5.2.3 bouyer static void ascattach (struct device *, struct device *, void *); 84 1.5.2.2 bouyer 85 1.5.2.2 bouyer struct cfattach asc_ca = { 86 1.5.2.2 bouyer sizeof(struct asc_softc), ascmatch, ascattach 87 1.5.2.2 bouyer }; 88 1.5.2.2 bouyer 89 1.5.2.2 bouyer /* 90 1.5.2.2 bouyer * Functions and the switch for the MI code. 91 1.5.2.2 bouyer */ 92 1.5.2.3 bouyer static u_char asc_read_reg (struct ncr53c9x_softc *, int); 93 1.5.2.3 bouyer static void asc_write_reg (struct ncr53c9x_softc *, int, u_char); 94 1.5.2.3 bouyer static int asc_dma_isintr (struct ncr53c9x_softc *); 95 1.5.2.3 bouyer static void asc_dma_reset (struct ncr53c9x_softc *); 96 1.5.2.3 bouyer static int asc_dma_intr (struct ncr53c9x_softc *); 97 1.5.2.3 bouyer static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *, 98 1.5.2.3 bouyer size_t *, int, size_t *); 99 1.5.2.3 bouyer static void asc_dma_go (struct ncr53c9x_softc *); 100 1.5.2.3 bouyer static void asc_dma_stop (struct ncr53c9x_softc *); 101 1.5.2.3 bouyer static int asc_dma_isactive (struct ncr53c9x_softc *); 102 1.5.2.2 bouyer 103 1.5.2.2 bouyer static struct ncr53c9x_glue asc_glue = { 104 1.5.2.2 bouyer asc_read_reg, 105 1.5.2.2 bouyer asc_write_reg, 106 1.5.2.2 bouyer asc_dma_isintr, 107 1.5.2.2 bouyer asc_dma_reset, 108 1.5.2.2 bouyer asc_dma_intr, 109 1.5.2.2 bouyer asc_dma_setup, 110 1.5.2.2 bouyer asc_dma_go, 111 1.5.2.2 bouyer asc_dma_stop, 112 1.5.2.2 bouyer asc_dma_isactive, 113 1.5.2.2 bouyer NULL, /* gl_clear_latched_intr */ 114 1.5.2.2 bouyer }; 115 1.5.2.2 bouyer 116 1.5.2.3 bouyer static int asc_intr (void *); 117 1.5.2.2 bouyer 118 1.5.2.2 bouyer #define MAX_SCSI_XFER (64*1024) 119 1.5.2.2 bouyer #define MAX_DMA_SZ MAX_SCSI_XFER 120 1.5.2.2 bouyer #define DMA_SEGS (MAX_DMA_SZ/NBPG) 121 1.5.2.2 bouyer 122 1.5.2.2 bouyer static int 123 1.5.2.3 bouyer ascmatch(struct device *parent, struct cfdata *cf, void *aux) 124 1.5.2.2 bouyer { 125 1.5.2.2 bouyer return 1; 126 1.5.2.2 bouyer } 127 1.5.2.2 bouyer 128 1.5.2.2 bouyer static void 129 1.5.2.3 bouyer ascattach(struct device *parent, struct device *self, void *aux) 130 1.5.2.2 bouyer { 131 1.5.2.2 bouyer struct confargs *ca = aux; 132 1.5.2.2 bouyer struct asc_softc *esc = (void *)self; 133 1.5.2.2 bouyer struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 134 1.5.2.2 bouyer 135 1.5.2.2 bouyer /* 136 1.5.2.2 bouyer * Set up glue for MI code early; we use some of it here. 137 1.5.2.2 bouyer */ 138 1.5.2.2 bouyer sc->sc_glue = &asc_glue; 139 1.5.2.2 bouyer 140 1.5.2.2 bouyer esc->sc_bst = ca->ca_bustag; 141 1.5.2.2 bouyer esc->sc_dmat = ca->ca_dmatag; 142 1.5.2.2 bouyer 143 1.5.2.2 bouyer if (bus_space_map(ca->ca_bustag, ca->ca_addr, 144 1.5.2.2 bouyer 16*4, /* sizeof (ncr53c9xreg) */ 145 1.5.2.2 bouyer BUS_SPACE_MAP_LINEAR, 146 1.5.2.2 bouyer &esc->sc_bsh) != 0) { 147 1.5.2.2 bouyer printf(": cannot map registers\n"); 148 1.5.2.2 bouyer return; 149 1.5.2.2 bouyer } 150 1.5.2.2 bouyer 151 1.5.2.2 bouyer if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 152 1.5.2.2 bouyer BUS_SPACE_MAP_LINEAR, 153 1.5.2.2 bouyer &esc->dm_bsh) != 0) { 154 1.5.2.2 bouyer printf(": cannot map dma registers\n"); 155 1.5.2.2 bouyer return; 156 1.5.2.2 bouyer } 157 1.5.2.2 bouyer 158 1.5.2.2 bouyer if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 159 1.5.2.2 bouyer DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 160 1.5.2.2 bouyer BUS_DMA_WAITOK, 161 1.5.2.2 bouyer &esc->sc_dmamap) != 0) { 162 1.5.2.2 bouyer printf(": failed to create dmamap\n"); 163 1.5.2.2 bouyer return; 164 1.5.2.2 bouyer } 165 1.5.2.2 bouyer 166 1.5.2.2 bouyer evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 167 1.5.2.2 bouyer self->dv_xname, "intr"); 168 1.5.2.2 bouyer 169 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 170 1.5.2.2 bouyer asc_dma_reset(sc); 171 1.5.2.2 bouyer 172 1.5.2.2 bouyer /* Other settings */ 173 1.5.2.2 bouyer sc->sc_id = 7; 174 1.5.2.2 bouyer sc->sc_freq = 24; /* 24 MHz clock */ 175 1.5.2.2 bouyer 176 1.5.2.2 bouyer /* 177 1.5.2.2 bouyer * Setup for genuine NCR 53C94 SCSI Controller 178 1.5.2.2 bouyer */ 179 1.5.2.2 bouyer 180 1.5.2.2 bouyer sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 181 1.5.2.4 bouyer sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 182 1.5.2.4 bouyer sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI; 183 1.5.2.2 bouyer sc->sc_rev = NCR_VARIANT_NCR53C94; 184 1.5.2.2 bouyer 185 1.5.2.2 bouyer sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 186 1.5.2.2 bouyer sc->sc_maxxfer = MAX_SCSI_XFER; 187 1.5.2.2 bouyer 188 1.5.2.2 bouyer #ifdef OLDNCR 189 1.5.2.2 bouyer if (!NCR_READ_REG(sc, NCR_CFG3)) { 190 1.5.2.2 bouyer printf(" [old revision]"); 191 1.5.2.2 bouyer sc->sc_cfg2 = 0; 192 1.5.2.2 bouyer sc->sc_cfg3 = 0; 193 1.5.2.2 bouyer sc->sc_minsync = 0; 194 1.5.2.2 bouyer } 195 1.5.2.2 bouyer #endif 196 1.5.2.2 bouyer 197 1.5.2.2 bouyer ncr53c9x_dmaselect = 0; 198 1.5.2.2 bouyer ncr53c9x_attach(sc, NULL, NULL); 199 1.5.2.2 bouyer 200 1.5.2.2 bouyer bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 201 1.5.2.2 bouyer } 202 1.5.2.2 bouyer 203 1.5.2.2 bouyer /* 204 1.5.2.2 bouyer * Glue functions. 205 1.5.2.2 bouyer */ 206 1.5.2.2 bouyer 207 1.5.2.3 bouyer static u_char 208 1.5.2.3 bouyer asc_read_reg(struct ncr53c9x_softc *sc, int reg) 209 1.5.2.2 bouyer { 210 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 211 1.5.2.2 bouyer 212 1.5.2.2 bouyer return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 213 1.5.2.2 bouyer } 214 1.5.2.2 bouyer 215 1.5.2.3 bouyer static void 216 1.5.2.3 bouyer asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 217 1.5.2.2 bouyer { 218 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 219 1.5.2.2 bouyer 220 1.5.2.2 bouyer bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 221 1.5.2.2 bouyer } 222 1.5.2.2 bouyer 223 1.5.2.3 bouyer static void 224 1.5.2.3 bouyer dma_status(struct ncr53c9x_softc *sc) 225 1.5.2.2 bouyer { 226 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 227 1.5.2.2 bouyer int count; 228 1.5.2.2 bouyer int stat; 229 1.5.2.2 bouyer void *addr; 230 1.5.2.2 bouyer u_int32_t tc; 231 1.5.2.2 bouyer 232 1.5.2.2 bouyer tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 233 1.5.2.2 bouyer count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 234 1.5.2.2 bouyer stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 235 1.5.2.2 bouyer addr = (void *) 236 1.5.2.2 bouyer bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 237 1.5.2.2 bouyer 238 1.5.2.2 bouyer printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 239 1.5.2.2 bouyer "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 240 1.5.2.2 bouyer count, addr, stat, tc, 241 1.5.2.2 bouyer asc_read_reg(sc, NCR_STAT), 242 1.5.2.2 bouyer asc_read_reg(sc, NCR_FFLAG)); 243 1.5.2.2 bouyer } 244 1.5.2.2 bouyer 245 1.5.2.2 bouyer static __inline void 246 1.5.2.3 bouyer check_fifo(struct asc_softc *esc) 247 1.5.2.2 bouyer { 248 1.5.2.2 bouyer register int i=100; 249 1.5.2.2 bouyer 250 1.5.2.2 bouyer while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 251 1.5.2.2 bouyer RAMBO_MODE) & RB_FIFO_EMPTY)) { 252 1.5.2.2 bouyer DELAY(1); i--; 253 1.5.2.2 bouyer } 254 1.5.2.2 bouyer 255 1.5.2.2 bouyer if (!i) { 256 1.5.2.2 bouyer dma_status((void *)esc); 257 1.5.2.2 bouyer panic("fifo didn't flush"); 258 1.5.2.2 bouyer } 259 1.5.2.2 bouyer } 260 1.5.2.2 bouyer 261 1.5.2.3 bouyer static int 262 1.5.2.3 bouyer asc_dma_isintr(struct ncr53c9x_softc *sc) 263 1.5.2.2 bouyer { 264 1.5.2.2 bouyer return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 265 1.5.2.2 bouyer } 266 1.5.2.2 bouyer 267 1.5.2.3 bouyer static void 268 1.5.2.3 bouyer asc_dma_reset(struct ncr53c9x_softc *sc) 269 1.5.2.2 bouyer { 270 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 271 1.5.2.2 bouyer 272 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 273 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 274 1.5.2.2 bouyer RB_CLRFIFO|RB_CLRERROR); 275 1.5.2.2 bouyer DELAY(10); 276 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 277 1.5.2.2 bouyer 278 1.5.2.2 bouyer if (esc->sc_flags & DMA_MAPLOADED) 279 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 280 1.5.2.2 bouyer 281 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 282 1.5.2.2 bouyer } 283 1.5.2.2 bouyer 284 1.5.2.2 bouyer /* 285 1.5.2.2 bouyer * Setup a DMA transfer 286 1.5.2.2 bouyer */ 287 1.5.2.2 bouyer 288 1.5.2.2 bouyer static int 289 1.5.2.3 bouyer asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 290 1.5.2.3 bouyer int datain, size_t *dmasize) 291 1.5.2.2 bouyer { 292 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 293 1.5.2.2 bouyer paddr_t paddr; 294 1.5.2.2 bouyer size_t count, blocks; 295 1.5.2.2 bouyer int prime, err; 296 1.5.2.2 bouyer 297 1.5.2.2 bouyer #ifdef DIAGNOSTIC 298 1.5.2.2 bouyer if (esc->sc_flags & DMA_ACTIVE) { 299 1.5.2.2 bouyer dma_status(sc); 300 1.5.2.2 bouyer panic("DMA active"); 301 1.5.2.2 bouyer } 302 1.5.2.2 bouyer #endif 303 1.5.2.2 bouyer 304 1.5.2.2 bouyer esc->sc_dmaaddr = addr; 305 1.5.2.2 bouyer esc->sc_dmalen = len; 306 1.5.2.2 bouyer esc->sc_dmasize = *dmasize; 307 1.5.2.2 bouyer esc->sc_flags = datain ? DMA_PULLUP : 0; 308 1.5.2.2 bouyer 309 1.5.2.2 bouyer NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 310 1.5.2.2 bouyer *addr, *len, datain, esc->sc_dmasize)); 311 1.5.2.2 bouyer 312 1.5.2.2 bouyer if (esc->sc_dmasize == 0) 313 1.5.2.2 bouyer return 0; 314 1.5.2.2 bouyer 315 1.5.2.2 bouyer /* have dmamap for the transfering addresses */ 316 1.5.2.3 bouyer if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 317 1.5.2.2 bouyer *esc->sc_dmaaddr, esc->sc_dmasize, 318 1.5.2.2 bouyer NULL /* kernel address */, 319 1.5.2.3 bouyer BUS_DMA_NOWAIT)) != 0) 320 1.5.2.2 bouyer panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 321 1.5.2.2 bouyer 322 1.5.2.2 bouyer esc->sc_flags |= DMA_MAPLOADED; 323 1.5.2.2 bouyer 324 1.5.2.2 bouyer /* No cache flush required for R3000 processors */ 325 1.5.2.2 bouyer 326 1.5.2.2 bouyer paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 327 1.5.2.2 bouyer count = esc->sc_dmamap->dm_segs[0].ds_len; 328 1.5.2.4 bouyer prime = (u_int32_t)paddr & 0x3f; 329 1.5.2.4 bouyer blocks = (prime + count + 63) >> 6; 330 1.5.2.2 bouyer 331 1.5.2.4 bouyer esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD); 332 1.5.2.4 bouyer 333 1.5.2.4 bouyer /* Set transfer direction and disable DMA */ 334 1.5.2.4 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 335 1.5.2.2 bouyer 336 1.5.2.2 bouyer /* Load DMA transfer address */ 337 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 338 1.5.2.2 bouyer paddr & ~0x3f); 339 1.5.2.2 bouyer 340 1.5.2.4 bouyer /* Load number of blocks to DMA (1 block = 64 bytes) */ 341 1.5.2.4 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 342 1.5.2.2 bouyer 343 1.5.2.2 bouyer /* If non block-aligned transfer prime FIFO manually */ 344 1.5.2.2 bouyer if (prime) { 345 1.5.2.4 bouyer /* Enable DMA to prime the FIFO buffer */ 346 1.5.2.4 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 347 1.5.2.4 bouyer RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE); 348 1.5.2.4 bouyer 349 1.5.2.2 bouyer if (esc->sc_flags & DMA_PULLUP) { 350 1.5.2.2 bouyer /* Read from NCR 53c94 controller*/ 351 1.5.2.2 bouyer u_int16_t *p; 352 1.5.2.2 bouyer 353 1.5.2.2 bouyer p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 354 1.5.2.2 bouyer bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 355 1.5.2.2 bouyer RAMBO_FIFO, p, prime>>1); 356 1.5.2.4 bouyer } else 357 1.5.2.4 bouyer /* Write to NCR 53C94 controller */ 358 1.5.2.2 bouyer while (prime > 0) { 359 1.5.2.2 bouyer (void)bus_space_read_2(esc->sc_bst, 360 1.5.2.2 bouyer esc->dm_bsh, 361 1.5.2.2 bouyer RAMBO_FIFO); 362 1.5.2.2 bouyer prime -= 2; 363 1.5.2.2 bouyer } 364 1.5.2.4 bouyer /* Leave DMA disabled while we setup NCR controller */ 365 1.5.2.4 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 366 1.5.2.4 bouyer esc->dm_mode); 367 1.5.2.2 bouyer } 368 1.5.2.4 bouyer 369 1.5.2.2 bouyer esc->dm_curseg = 0; 370 1.5.2.4 bouyer esc->dm_mode |= RB_DMA_ENABLE; 371 1.5.2.4 bouyer if (esc->sc_dmamap->dm_nsegs > 1) 372 1.5.2.4 bouyer esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 373 1.5.2.4 bouyer 374 1.5.2.2 bouyer return 0; 375 1.5.2.2 bouyer } 376 1.5.2.2 bouyer 377 1.5.2.3 bouyer static void 378 1.5.2.3 bouyer asc_dma_go(struct ncr53c9x_softc *sc) 379 1.5.2.2 bouyer { 380 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 381 1.5.2.2 bouyer 382 1.5.2.4 bouyer /* Start DMA */ 383 1.5.2.4 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 384 1.5.2.4 bouyer 385 1.5.2.2 bouyer esc->sc_flags |= DMA_ACTIVE; 386 1.5.2.2 bouyer } 387 1.5.2.2 bouyer 388 1.5.2.3 bouyer static int 389 1.5.2.3 bouyer asc_dma_intr(struct ncr53c9x_softc *sc) 390 1.5.2.2 bouyer { 391 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 392 1.5.2.2 bouyer 393 1.5.2.2 bouyer size_t resid, len; 394 1.5.2.2 bouyer int trans; 395 1.5.2.2 bouyer u_int32_t status; 396 1.5.2.2 bouyer u_int tcl, tcm; 397 1.5.2.2 bouyer 398 1.5.2.2 bouyer #ifdef DIAGNOSTIC 399 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_ACTIVE)) { 400 1.5.2.2 bouyer dma_status(sc); 401 1.5.2.2 bouyer panic("DMA not active"); 402 1.5.2.2 bouyer } 403 1.5.2.2 bouyer #endif 404 1.5.2.2 bouyer 405 1.5.2.2 bouyer resid = 0; 406 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_PULLUP) && 407 1.5.2.2 bouyer (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 408 1.5.2.2 bouyer NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 409 1.5.2.2 bouyer DELAY(10); 410 1.5.2.2 bouyer } 411 1.5.2.2 bouyer 412 1.5.2.2 bouyer resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 413 1.5.2.2 bouyer ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 414 1.5.2.2 bouyer 415 1.5.2.2 bouyer if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 416 1.5.2.2 bouyer NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 417 1.5.2.2 bouyer return 0; 418 1.5.2.2 bouyer } 419 1.5.2.2 bouyer 420 1.5.2.2 bouyer trans = esc->sc_dmasize - resid; 421 1.5.2.2 bouyer if (trans < 0) { /* transferred < 0 ? */ 422 1.5.2.2 bouyer printf("asc_intr: xfer (%d) > req (%d)\n", 423 1.5.2.2 bouyer trans, esc->sc_dmasize); 424 1.5.2.2 bouyer trans = esc->sc_dmasize; 425 1.5.2.2 bouyer } 426 1.5.2.2 bouyer 427 1.5.2.2 bouyer NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 428 1.5.2.2 bouyer tcl, tcm, trans, resid)); 429 1.5.2.2 bouyer 430 1.5.2.2 bouyer status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 431 1.5.2.2 bouyer 432 1.5.2.2 bouyer if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 433 1.5.2.2 bouyer if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 434 1.5.2.2 bouyer paddr_t ptr; 435 1.5.2.2 bouyer u_int16_t *p; 436 1.5.2.2 bouyer 437 1.5.2.2 bouyer resid = status & 0x1f; 438 1.5.2.2 bouyer 439 1.5.2.2 bouyer /* take the address of block to fixed up */ 440 1.5.2.2 bouyer ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 441 1.5.2.2 bouyer RAMBO_CADDR); 442 1.5.2.2 bouyer /* find the starting address of fractional data */ 443 1.5.2.2 bouyer p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 444 1.5.2.2 bouyer 445 1.5.2.2 bouyer /* duplicate trailing data to FIFO for force flush */ 446 1.5.2.2 bouyer len = RB_BLK_CNT - resid; 447 1.5.2.2 bouyer bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 448 1.5.2.2 bouyer RAMBO_FIFO, p, len); 449 1.5.2.2 bouyer check_fifo(esc); 450 1.5.2.2 bouyer } else { /* SCSI Write */ 451 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 452 1.5.2.2 bouyer RAMBO_MODE, 0); 453 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 454 1.5.2.2 bouyer RAMBO_MODE, RB_CLRFIFO); 455 1.5.2.2 bouyer } 456 1.5.2.2 bouyer } 457 1.5.2.2 bouyer 458 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 459 1.5.2.2 bouyer 460 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 461 1.5.2.2 bouyer 462 1.5.2.2 bouyer bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 463 1.5.2.2 bouyer 0, esc->sc_dmasize, 464 1.5.2.2 bouyer (esc->sc_flags & DMA_PULLUP) 465 1.5.2.2 bouyer ? BUS_DMASYNC_POSTREAD 466 1.5.2.2 bouyer : BUS_DMASYNC_POSTWRITE); 467 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 468 1.5.2.2 bouyer 469 1.5.2.2 bouyer *esc->sc_dmaaddr += trans; 470 1.5.2.2 bouyer *esc->sc_dmalen -= trans; 471 1.5.2.2 bouyer 472 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 473 1.5.2.2 bouyer 474 1.5.2.2 bouyer return 0; 475 1.5.2.2 bouyer } 476 1.5.2.2 bouyer 477 1.5.2.2 bouyer 478 1.5.2.3 bouyer static void 479 1.5.2.3 bouyer asc_dma_stop(struct ncr53c9x_softc *sc) 480 1.5.2.2 bouyer { 481 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 482 1.5.2.2 bouyer 483 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 484 1.5.2.2 bouyer if (esc->sc_flags & DMA_MAPLOADED) 485 1.5.2.2 bouyer bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 486 1.5.2.2 bouyer esc->sc_flags = DMA_IDLE; 487 1.5.2.2 bouyer } 488 1.5.2.2 bouyer 489 1.5.2.3 bouyer static int 490 1.5.2.3 bouyer asc_dma_isactive(struct ncr53c9x_softc *sc) 491 1.5.2.2 bouyer { 492 1.5.2.2 bouyer struct asc_softc *esc = (struct asc_softc *)sc; 493 1.5.2.2 bouyer return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 494 1.5.2.2 bouyer } 495 1.5.2.2 bouyer 496 1.5.2.3 bouyer static void 497 1.5.2.3 bouyer rambo_dma_chain(struct asc_softc *esc) 498 1.5.2.2 bouyer { 499 1.5.2.2 bouyer int seg; 500 1.5.2.2 bouyer size_t count, blocks; 501 1.5.2.2 bouyer paddr_t paddr; 502 1.5.2.2 bouyer 503 1.5.2.2 bouyer seg = ++esc->dm_curseg; 504 1.5.2.2 bouyer 505 1.5.2.2 bouyer #ifdef DIAGNOSTIC 506 1.5.2.2 bouyer if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 507 1.5.2.2 bouyer panic("Unexpected DMA chaining intr"); 508 1.5.2.2 bouyer 509 1.5.2.2 bouyer /* Interrupt can only occur at terminal count, but double check */ 510 1.5.2.2 bouyer if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 511 1.5.2.2 bouyer dma_status((void *)esc); 512 1.5.2.2 bouyer panic("rambo blkcnt != 0"); 513 1.5.2.2 bouyer } 514 1.5.2.2 bouyer #endif 515 1.5.2.2 bouyer 516 1.5.2.2 bouyer paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 517 1.5.2.2 bouyer count = esc->sc_dmamap->dm_segs[seg].ds_len; 518 1.5.2.2 bouyer blocks = (count + 63) >> 6; 519 1.5.2.2 bouyer 520 1.5.2.2 bouyer /* Disable DMA interrupt if last segment */ 521 1.5.2.2 bouyer if (seg+1 > esc->sc_dmamap->dm_nsegs) { 522 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, 523 1.5.2.2 bouyer RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 524 1.5.2.2 bouyer } 525 1.5.2.2 bouyer 526 1.5.2.2 bouyer /* Load transfer address for next DMA chain */ 527 1.5.2.2 bouyer bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 528 1.5.2.2 bouyer 529 1.5.2.2 bouyer /* DMA restarts when we enter a new block count */ 530 1.5.2.2 bouyer bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 531 1.5.2.2 bouyer } 532 1.5.2.2 bouyer 533 1.5.2.3 bouyer static int 534 1.5.2.3 bouyer asc_intr(void *arg) 535 1.5.2.2 bouyer { 536 1.5.2.2 bouyer register u_int32_t dma_stat; 537 1.5.2.2 bouyer struct asc_softc *esc = arg; 538 1.5.2.2 bouyer struct ncr53c9x_softc *sc = arg; 539 1.5.2.2 bouyer 540 1.5.2.2 bouyer esc->sc_intrcnt.ev_count++; 541 1.5.2.2 bouyer 542 1.5.2.2 bouyer /* Check for RAMBO DMA Interrupt */ 543 1.5.2.2 bouyer dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 544 1.5.2.2 bouyer if (dma_stat & RB_INTR_PEND) { 545 1.5.2.2 bouyer rambo_dma_chain(esc); 546 1.5.2.2 bouyer } 547 1.5.2.2 bouyer /* Check for NCR 53c94 interrupt */ 548 1.5.2.2 bouyer if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 549 1.5.2.2 bouyer ncr53c9x_intr(sc); 550 1.5.2.2 bouyer } 551 1.5.2.2 bouyer return 0; 552 1.5.2.2 bouyer } 553
Indexes created Tue Oct 28 12:10:06 GMT 2025