asc.c revision 1.1
1 /* $NetBSD: asc.c,v 1.1 2000/08/12 22:58:55 wdk Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 size_t sc_blkcnt; 74 int sc_flags; 75 #define DMA_IDLE 0x0 76 #define DMA_PULLUP 0x1 77 #define DMA_ACTIVE 0x2 78 #define DMA_MAPLOADED 0x4 79 u_int32_t dm_mode; 80 int dm_curseg; 81 }; 82 83 static int ascmatch __P((struct device *, struct cfdata *, void *)); 84 static void ascattach __P((struct device *, struct device *, void *)); 85 86 static struct asc_softc *asc0; 87 88 struct cfattach asc_ca = { 89 sizeof(struct asc_softc), ascmatch, ascattach 90 }; 91 92 /* 93 * Functions and the switch for the MI code. 94 */ 95 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 96 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 97 static int asc_dma_isintr __P((struct ncr53c9x_softc *)); 98 static void asc_dma_reset __P((struct ncr53c9x_softc *)); 99 static int asc_dma_intr __P((struct ncr53c9x_softc *)); 100 static int asc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 101 size_t *, int, size_t *)); 102 static void asc_dma_go __P((struct ncr53c9x_softc *)); 103 static void asc_dma_stop __P((struct ncr53c9x_softc *)); 104 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 105 106 static struct ncr53c9x_glue asc_glue = { 107 asc_read_reg, 108 asc_write_reg, 109 asc_dma_isintr, 110 asc_dma_reset, 111 asc_dma_intr, 112 asc_dma_setup, 113 asc_dma_go, 114 asc_dma_stop, 115 asc_dma_isactive, 116 NULL, /* gl_clear_latched_intr */ 117 }; 118 119 #define MAX_SCSI_XFER (64*1024) 120 #define MAX_DMA_SZ MAX_SCSI_XFER 121 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 122 123 static int 124 ascmatch(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 return 1; 130 } 131 132 static void 133 ascattach(parent, self, aux) 134 struct device *parent, *self; 135 void *aux; 136 { 137 struct confargs *ca = aux; 138 struct asc_softc *esc = (void *)self; 139 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 140 141 /* 142 * Set up glue for MI code early; we use some of it here. 143 */ 144 sc->sc_glue = &asc_glue; 145 146 esc->sc_bst = ca->ca_bustag; 147 esc->sc_dmat = ca->ca_dmatag; 148 149 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 150 16*4, /* sizeof (ncr53c9xreg) */ 151 BUS_SPACE_MAP_LINEAR, 152 &esc->sc_bsh) != 0) { 153 printf(": cannot map registers\n"); 154 return; 155 } 156 157 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 158 BUS_SPACE_MAP_LINEAR, 159 &esc->dm_bsh) != 0) { 160 printf(": cannot map dma registers\n"); 161 return; 162 } 163 164 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 165 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 166 BUS_DMA_WAITOK, 167 &esc->sc_dmamap) != 0) { 168 printf(": failed to create dmamap\n"); 169 return; 170 } 171 172 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 173 self->dv_xname, "intr"); 174 175 esc->sc_flags = DMA_IDLE; 176 asc_dma_reset(sc); 177 178 /* Other settings */ 179 sc->sc_id = 7; 180 sc->sc_freq = 24; /* 24 MHz clock */ 181 182 /* 183 * Setup for genuine NCR 53C94 SCSI Controller 184 */ 185 186 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 188 sc->sc_cfg3 = 0; /* NCRCFG3_CDB; */ 189 sc->sc_rev = NCR_VARIANT_NCR53C94; 190 191 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 192 sc->sc_maxxfer = MAX_SCSI_XFER; 193 194 #ifdef OLDNCR 195 if (!NCR_READ_REG(sc, NCR_CFG3)) { 196 printf(" [old revision]"); 197 sc->sc_cfg2 = 0; 198 sc->sc_cfg3 = 0; 199 sc->sc_minsync = 0; 200 } 201 #endif 202 203 ncr53c9x_attach(sc, NULL, NULL); 204 205 ncr53c9x_dmaselect = 0; 206 asc0 = esc; 207 } 208 209 /* 210 * Glue functions. 211 */ 212 213 u_char 214 asc_read_reg(sc, reg) 215 struct ncr53c9x_softc *sc; 216 int reg; 217 { 218 struct asc_softc *esc = (struct asc_softc *)sc; 219 220 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 221 } 222 223 void 224 asc_write_reg(sc, reg, val) 225 struct ncr53c9x_softc *sc; 226 int reg; 227 u_char val; 228 { 229 struct asc_softc *esc = (struct asc_softc *)sc; 230 231 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 232 } 233 234 void 235 dma_status(sc) 236 struct ncr53c9x_softc *sc; 237 { 238 struct asc_softc *esc = (struct asc_softc *)sc; 239 int count; 240 int stat; 241 void *addr; 242 u_int32_t tc; 243 244 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 245 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 246 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 247 addr = (void *) 248 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 249 250 NCR_DMA(("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 251 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 252 count, addr, stat, tc, 253 asc_read_reg(sc, NCR_STAT), 254 asc_read_reg(sc, NCR_FFLAG))); 255 } 256 257 int 258 asc_dma_isintr(sc) 259 struct ncr53c9x_softc *sc; 260 { 261 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 262 } 263 264 void 265 asc_dma_reset(sc) 266 struct ncr53c9x_softc *sc; 267 { 268 struct asc_softc *esc = (struct asc_softc *)sc; 269 270 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 271 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 272 RB_CLRFIFO|RB_CLRERROR); 273 DELAY(10); 274 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 275 276 if (esc->sc_flags & DMA_MAPLOADED) 277 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 278 279 esc->sc_flags = DMA_IDLE; 280 } 281 282 /* 283 * Setup a DMA transfer 284 */ 285 286 static int 287 asc_dma_setup(sc, addr, len, datain, dmasize) 288 struct ncr53c9x_softc *sc; 289 caddr_t *addr; 290 size_t *len; 291 int datain; 292 size_t *dmasize; 293 { 294 struct asc_softc *esc = (struct asc_softc *)sc; 295 paddr_t paddr; 296 size_t count, blocks; 297 int prime, err; 298 299 #ifdef DIAGNOSTIC 300 if (esc->sc_flags & DMA_ACTIVE) { 301 dma_status(sc); 302 panic("DMA active"); 303 } 304 #endif 305 306 /* Flush FIFO from previous operation */ 307 308 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 309 RB_CLRFIFO|RB_CLRERROR); 310 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 311 312 esc->sc_dmaaddr = addr; 313 esc->sc_dmalen = len; 314 esc->sc_dmasize = *dmasize; 315 esc->sc_flags = datain ? DMA_PULLUP : 0; 316 317 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 318 *addr, *len, datain, esc->sc_dmasize)); 319 320 /* have dmamap for the transfering addresses */ 321 if (err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 322 *esc->sc_dmaaddr, esc->sc_dmasize, 323 NULL /* kernel address */, 324 BUS_DMA_NOWAIT)) 325 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 326 327 esc->sc_flags |= DMA_MAPLOADED; 328 329 /* No cache flush required for R3000 processors */ 330 331 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 332 count = esc->sc_dmamap->dm_segs[0].ds_len; 333 blocks = (((u_int32_t)*addr & 0x3f) + count + 63) >> 6; 334 335 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD) | RB_DMA_ENABLE; 336 if (esc->sc_dmamap->dm_nsegs > 1) 337 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 338 339 /* Load DMA transfer address */ 340 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 341 paddr & ~0x3f); 342 343 /* Set count to zero bytes as this will prevent DMA from starting */ 344 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 345 346 /* Set transfer direction and enable DMA FIFO */ 347 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 348 349 /* If non block-aligned transfer prime FIFO manually */ 350 prime = (u_int32_t)*esc->sc_dmaaddr & 0x3f; 351 if (prime) { 352 if (esc->sc_flags & DMA_PULLUP) { 353 u_int16_t *p; 354 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 355 /* Read from NCR 53c94 controller*/ 356 while (prime > 0) { 357 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 358 RAMBO_FIFO, *p++); 359 prime -= 2; 360 } 361 } else { 362 /* Fetch the first block */ 363 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 364 RAMBO_BLKCNT, 1); 365 while (prime > 0) { 366 (void)bus_space_read_2(esc->sc_bst, 367 esc->dm_bsh, 368 RAMBO_FIFO); 369 prime -= 2; 370 } 371 } 372 } 373 esc->sc_blkcnt = blocks; 374 esc->dm_curseg = 0; 375 return 0; 376 } 377 378 void 379 asc_dma_go(sc) 380 struct ncr53c9x_softc *sc; 381 { 382 struct asc_softc *esc = (struct asc_softc *)sc; 383 384 /* Load block count to start transfer */ 385 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 386 RAMBO_BLKCNT, esc->sc_blkcnt); 387 esc->sc_flags |= DMA_ACTIVE; 388 } 389 390 int 391 asc_dma_intr(sc) 392 struct ncr53c9x_softc *sc; 393 { 394 struct asc_softc *esc = (struct asc_softc *)sc; 395 396 size_t resid, len; 397 int trans; 398 u_int32_t status; 399 u_int tcl, tcm; 400 401 #ifdef DIAGNOSTIC 402 if (!(esc->sc_flags & DMA_ACTIVE)) { 403 dma_status(sc); 404 panic("DMA not active"); 405 } 406 #endif 407 408 #if 0 409 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 410 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 411 DELAY(10); 412 } 413 #endif 414 resid = (tcl = NCR_READ_REG(sc, NCR_TCL)) + 415 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 416 trans = esc->sc_dmasize - resid; 417 if (trans < 0) { /* transferred < 0 ? */ 418 printf("asc_intr: xfer (%d) > req (%d)\n", 419 trans, esc->sc_dmasize); 420 trans = esc->sc_dmasize; 421 } 422 423 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 424 tcl, tcm, trans, resid)); 425 426 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 427 resid = status & 0x1f; 428 429 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 430 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 431 paddr_t ptr; 432 u_int16_t *p; 433 434 /* take the address of block to fixed up */ 435 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 436 RAMBO_CADDR); 437 /* find the starting address of fractional data */ 438 p = (u_int16_t *)MIPS_PHYS_TO_KSEG1(ptr+(resid<<1)); 439 440 /* XXX - disable DMA xfer before flushing FIFO ? */ 441 len = RB_BLK_CNT - resid; 442 while (len--) { 443 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 444 RAMBO_FIFO, *p++); 445 } 446 } else { /* SCSI Write */ 447 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 448 RAMBO_MODE, RB_CLRFIFO); 449 } 450 } 451 452 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 453 454 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 455 0, esc->sc_dmasize, 456 (esc->sc_flags & DMA_PULLUP) 457 ? BUS_DMASYNC_POSTREAD 458 : BUS_DMASYNC_POSTWRITE); 459 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 460 461 *esc->sc_dmaaddr += trans; 462 *esc->sc_dmalen -= trans; 463 464 esc->sc_flags = DMA_IDLE; 465 466 return 0; 467 } 468 469 470 void 471 asc_dma_stop(sc) 472 struct ncr53c9x_softc *sc; 473 { 474 struct asc_softc *esc = (struct asc_softc *)sc; 475 476 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 477 if (esc->sc_flags & DMA_MAPLOADED) 478 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 479 esc->sc_flags = DMA_IDLE; 480 } 481 482 int 483 asc_dma_isactive(sc) 484 struct ncr53c9x_softc *sc; 485 { 486 struct asc_softc *esc = (struct asc_softc *)sc; 487 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 488 } 489 490 void 491 rambo_dma_chain(esc) 492 struct asc_softc *esc; 493 { 494 int seg; 495 size_t count, blocks; 496 paddr_t paddr; 497 498 seg = ++esc->dm_curseg; 499 500 /* XXX: Check rambo status */ 501 502 #ifdef DIAGNOSTIC 503 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 504 panic("Unexpected DMA chaining intr"); 505 #endif 506 507 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 508 count = esc->sc_dmamap->dm_segs[seg].ds_len; 509 blocks = (count + 63) >> 6; 510 511 /* Disable DMA interrupt if last segment */ 512 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 513 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 514 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 515 } 516 517 /* Load transfer address for next DMA chain */ 518 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 519 520 /* DMA restarts when we enter a new block count */ 521 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 522 } 523 524 void 525 asc_intr() 526 { 527 register u_int32_t dma_stat; 528 struct asc_softc *esc = asc0; 529 struct ncr53c9x_softc *sc = (void *)asc0; 530 531 esc->sc_intrcnt.ev_count++; 532 533 /* Check for NCR 53c94 interrupt */ 534 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 535 ncr53c9x_intr((struct ncr53c9x_softc *) asc0); 536 } 537 /* Check for RAMBO DMA Interrupt */ 538 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 539 if (dma_stat & RB_INTR_PEND) { 540 rambo_dma_chain(esc); 541 } 542 } 543
Indexes created Thu Oct 02 01:09:59 GMT 2025