asc.c revision 1.10
1 /* $NetBSD: asc.c,v 1.10 2001/12/15 11:11:49 wdk Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 int sc_flags; 74 #define DMA_IDLE 0x0 75 #define DMA_PULLUP 0x1 76 #define DMA_ACTIVE 0x2 77 #define DMA_MAPLOADED 0x4 78 u_int32_t dm_mode; 79 int dm_curseg; 80 }; 81 82 static int ascmatch (struct device *, struct cfdata *, void *); 83 static void ascattach (struct device *, struct device *, void *); 84 85 struct cfattach asc_ca = { 86 sizeof(struct asc_softc), ascmatch, ascattach 87 }; 88 89 /* 90 * Functions and the switch for the MI code. 91 */ 92 static u_char asc_read_reg (struct ncr53c9x_softc *, int); 93 static void asc_write_reg (struct ncr53c9x_softc *, int, u_char); 94 static int asc_dma_isintr (struct ncr53c9x_softc *); 95 static void asc_dma_reset (struct ncr53c9x_softc *); 96 static int asc_dma_intr (struct ncr53c9x_softc *); 97 static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *, 98 size_t *, int, size_t *); 99 static void asc_dma_go (struct ncr53c9x_softc *); 100 static void asc_dma_stop (struct ncr53c9x_softc *); 101 static int asc_dma_isactive (struct ncr53c9x_softc *); 102 103 static struct ncr53c9x_glue asc_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 asc_dma_isintr, 107 asc_dma_reset, 108 asc_dma_intr, 109 asc_dma_setup, 110 asc_dma_go, 111 asc_dma_stop, 112 asc_dma_isactive, 113 NULL, /* gl_clear_latched_intr */ 114 }; 115 116 static int asc_intr (void *); 117 118 #define MAX_SCSI_XFER (64*1024) 119 #define MAX_DMA_SZ MAX_SCSI_XFER 120 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 121 122 static int 123 ascmatch(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 return 1; 126 } 127 128 static void 129 ascattach(struct device *parent, struct device *self, void *aux) 130 { 131 struct confargs *ca = aux; 132 struct asc_softc *esc = (void *)self; 133 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 134 135 /* 136 * Set up glue for MI code early; we use some of it here. 137 */ 138 sc->sc_glue = &asc_glue; 139 140 esc->sc_bst = ca->ca_bustag; 141 esc->sc_dmat = ca->ca_dmatag; 142 143 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 144 16*4, /* sizeof (ncr53c9xreg) */ 145 BUS_SPACE_MAP_LINEAR, 146 &esc->sc_bsh) != 0) { 147 printf(": cannot map registers\n"); 148 return; 149 } 150 151 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 152 BUS_SPACE_MAP_LINEAR, 153 &esc->dm_bsh) != 0) { 154 printf(": cannot map dma registers\n"); 155 return; 156 } 157 158 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 159 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 160 BUS_DMA_WAITOK, 161 &esc->sc_dmamap) != 0) { 162 printf(": failed to create dmamap\n"); 163 return; 164 } 165 166 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 167 self->dv_xname, "intr"); 168 169 esc->sc_flags = DMA_IDLE; 170 asc_dma_reset(sc); 171 172 /* Other settings */ 173 sc->sc_id = 7; 174 sc->sc_freq = 24; /* 24 MHz clock */ 175 176 /* 177 * Setup for genuine NCR 53C94 SCSI Controller 178 */ 179 180 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 181 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 182 sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI; 183 sc->sc_rev = NCR_VARIANT_NCR53C94; 184 185 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 186 sc->sc_maxxfer = MAX_SCSI_XFER; 187 188 #ifdef OLDNCR 189 if (!NCR_READ_REG(sc, NCR_CFG3)) { 190 printf(" [old revision]"); 191 sc->sc_cfg2 = 0; 192 sc->sc_cfg3 = 0; 193 sc->sc_minsync = 0; 194 } 195 #endif 196 197 sc->sc_adapter.adapt_minphys = minphys; 198 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 199 ncr53c9x_attach(sc); 200 201 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 202 } 203 204 /* 205 * Glue functions. 206 */ 207 208 static u_char 209 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 210 { 211 struct asc_softc *esc = (struct asc_softc *)sc; 212 213 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 214 } 215 216 static void 217 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 218 { 219 struct asc_softc *esc = (struct asc_softc *)sc; 220 221 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 222 } 223 224 static void 225 dma_status(struct ncr53c9x_softc *sc) 226 { 227 struct asc_softc *esc = (struct asc_softc *)sc; 228 int count; 229 int stat; 230 void *addr; 231 u_int32_t tc; 232 233 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 234 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 235 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 236 addr = (void *) 237 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 238 239 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 240 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 241 count, addr, stat, tc, 242 asc_read_reg(sc, NCR_STAT), 243 asc_read_reg(sc, NCR_FFLAG)); 244 } 245 246 static __inline void 247 check_fifo(struct asc_softc *esc) 248 { 249 register int i=100; 250 251 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 252 RAMBO_MODE) & RB_FIFO_EMPTY)) { 253 DELAY(1); i--; 254 } 255 256 if (!i) { 257 dma_status((void *)esc); 258 panic("fifo didn't flush"); 259 } 260 } 261 262 static int 263 asc_dma_isintr(struct ncr53c9x_softc *sc) 264 { 265 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 266 } 267 268 static void 269 asc_dma_reset(struct ncr53c9x_softc *sc) 270 { 271 struct asc_softc *esc = (struct asc_softc *)sc; 272 273 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 274 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 275 RB_CLRFIFO|RB_CLRERROR); 276 DELAY(10); 277 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 278 279 if (esc->sc_flags & DMA_MAPLOADED) 280 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 281 282 esc->sc_flags = DMA_IDLE; 283 } 284 285 /* 286 * Setup a DMA transfer 287 */ 288 289 static int 290 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 291 int datain, size_t *dmasize) 292 { 293 struct asc_softc *esc = (struct asc_softc *)sc; 294 paddr_t paddr; 295 size_t count, blocks; 296 int prime, err; 297 298 #ifdef DIAGNOSTIC 299 if (esc->sc_flags & DMA_ACTIVE) { 300 dma_status(sc); 301 panic("DMA active"); 302 } 303 #endif 304 305 esc->sc_dmaaddr = addr; 306 esc->sc_dmalen = len; 307 esc->sc_dmasize = *dmasize; 308 esc->sc_flags = datain ? DMA_PULLUP : 0; 309 310 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 311 *addr, *len, datain, esc->sc_dmasize)); 312 313 if (esc->sc_dmasize == 0) 314 return 0; 315 316 /* have dmamap for the transfering addresses */ 317 if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 318 *esc->sc_dmaaddr, esc->sc_dmasize, 319 NULL /* kernel address */, 320 BUS_DMA_NOWAIT)) != 0) 321 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 322 323 esc->sc_flags |= DMA_MAPLOADED; 324 325 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 326 count = esc->sc_dmamap->dm_segs[0].ds_len; 327 prime = (u_int32_t)paddr & 0x3f; 328 blocks = (prime + count + 63) >> 6; 329 330 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD); 331 332 /* Set transfer direction and disable DMA */ 333 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 334 335 /* Load DMA transfer address */ 336 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 337 paddr & ~0x3f); 338 339 /* Load number of blocks to DMA (1 block = 64 bytes) */ 340 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 341 342 /* If non block-aligned transfer prime FIFO manually */ 343 if (prime) { 344 /* Enable DMA to prime the FIFO buffer */ 345 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 346 RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE); 347 348 if (esc->sc_flags & DMA_PULLUP) { 349 /* Read from NCR 53c94 controller*/ 350 u_int16_t *p; 351 352 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 353 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 354 RAMBO_FIFO, p, prime>>1); 355 } else 356 /* Write to NCR 53C94 controller */ 357 while (prime > 0) { 358 (void)bus_space_read_2(esc->sc_bst, 359 esc->dm_bsh, 360 RAMBO_FIFO); 361 prime -= 2; 362 } 363 /* Leave DMA disabled while we setup NCR controller */ 364 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 365 esc->dm_mode); 366 } 367 368 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 0, esc->sc_dmasize, 369 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 370 371 esc->dm_curseg = 0; 372 esc->dm_mode |= RB_DMA_ENABLE; 373 if (esc->sc_dmamap->dm_nsegs > 1) 374 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 375 376 return 0; 377 } 378 379 static void 380 asc_dma_go(struct ncr53c9x_softc *sc) 381 { 382 struct asc_softc *esc = (struct asc_softc *)sc; 383 384 /* Start DMA */ 385 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 386 387 esc->sc_flags |= DMA_ACTIVE; 388 } 389 390 static int 391 asc_dma_intr(struct ncr53c9x_softc *sc) 392 { 393 struct asc_softc *esc = (struct asc_softc *)sc; 394 395 size_t resid, len; 396 int trans; 397 u_int32_t status; 398 u_int tcl, tcm; 399 400 #ifdef DIAGNOSTIC 401 if (!(esc->sc_flags & DMA_ACTIVE)) { 402 dma_status(sc); 403 panic("DMA not active"); 404 } 405 #endif 406 407 resid = 0; 408 if (!(esc->sc_flags & DMA_PULLUP) && 409 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 410 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 411 DELAY(10); 412 } 413 414 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 415 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 416 417 if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 418 NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 419 return 0; 420 } 421 422 trans = esc->sc_dmasize - resid; 423 if (trans < 0) { /* transferred < 0 ? */ 424 printf("asc_intr: xfer (%d) > req (%d)\n", 425 trans, esc->sc_dmasize); 426 trans = esc->sc_dmasize; 427 } 428 429 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 430 tcl, tcm, trans, resid)); 431 432 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 433 434 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 435 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 436 paddr_t ptr; 437 u_int16_t *p; 438 439 resid = status & 0x1f; 440 441 /* take the address of block to fixed up */ 442 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 443 RAMBO_CADDR); 444 /* find the starting address of fractional data */ 445 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 446 447 /* duplicate trailing data to FIFO for force flush */ 448 len = RB_BLK_CNT - resid; 449 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 450 RAMBO_FIFO, p, len); 451 check_fifo(esc); 452 } else { /* SCSI Write */ 453 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 454 RAMBO_MODE, 0); 455 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 456 RAMBO_MODE, RB_CLRFIFO); 457 } 458 } 459 460 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 461 462 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 463 464 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 465 0, esc->sc_dmasize, 466 (esc->sc_flags & DMA_PULLUP) 467 ? BUS_DMASYNC_POSTREAD 468 : BUS_DMASYNC_POSTWRITE); 469 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 470 471 *esc->sc_dmaaddr += trans; 472 *esc->sc_dmalen -= trans; 473 474 esc->sc_flags = DMA_IDLE; 475 476 return 0; 477 } 478 479 480 static void 481 asc_dma_stop(struct ncr53c9x_softc *sc) 482 { 483 struct asc_softc *esc = (struct asc_softc *)sc; 484 485 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 486 if (esc->sc_flags & DMA_MAPLOADED) 487 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 488 esc->sc_flags = DMA_IDLE; 489 } 490 491 static int 492 asc_dma_isactive(struct ncr53c9x_softc *sc) 493 { 494 struct asc_softc *esc = (struct asc_softc *)sc; 495 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 496 } 497 498 static void 499 rambo_dma_chain(struct asc_softc *esc) 500 { 501 int seg; 502 size_t count, blocks; 503 paddr_t paddr; 504 505 seg = ++esc->dm_curseg; 506 507 #ifdef DIAGNOSTIC 508 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 509 panic("Unexpected DMA chaining intr"); 510 511 /* Interrupt can only occur at terminal count, but double check */ 512 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 513 dma_status((void *)esc); 514 panic("rambo blkcnt != 0"); 515 } 516 #endif 517 518 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 519 count = esc->sc_dmamap->dm_segs[seg].ds_len; 520 blocks = (count + 63) >> 6; 521 522 /* Disable DMA interrupt if last segment */ 523 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 524 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 525 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 526 } 527 528 /* Load transfer address for next DMA chain */ 529 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 530 531 /* DMA restarts when we enter a new block count */ 532 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 533 } 534 535 static int 536 asc_intr(void *arg) 537 { 538 register u_int32_t dma_stat; 539 struct asc_softc *esc = arg; 540 struct ncr53c9x_softc *sc = arg; 541 542 esc->sc_intrcnt.ev_count++; 543 544 /* Check for RAMBO DMA Interrupt */ 545 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 546 if (dma_stat & RB_INTR_PEND) { 547 rambo_dma_chain(esc); 548 } 549 /* Check for NCR 53c94 interrupt */ 550 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 551 ncr53c9x_intr(sc); 552 } 553 return 0; 554 } 555
Indexes created Thu Oct 02 01:09:59 GMT 2025