asc.c revision 1.21
1 /* $NetBSD: asc.c,v 1.21 2008/04/13 04:55:52 tsutsui Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.21 2008/04/13 04:55:52 tsutsui Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/errno.h> 46 #include <sys/device.h> 47 #include <sys/buf.h> 48 #include <sys/malloc.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #include <dev/scsipi/scsi_all.h> 53 #include <dev/scsipi/scsipi_all.h> 54 #include <dev/scsipi/scsiconf.h> 55 #include <dev/scsipi/scsi_message.h> 56 57 #include <machine/cpu.h> 58 #include <machine/autoconf.h> 59 #include <machine/mainboard.h> 60 #include <machine/bus.h> 61 62 #include <mipsco/obio/rambo.h> 63 64 #include <dev/ic/ncr53c9xreg.h> 65 #include <dev/ic/ncr53c9xvar.h> 66 67 struct asc_softc { 68 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 69 struct evcnt sc_intrcnt; /* Interrupt counter */ 70 bus_space_tag_t sc_bst; 71 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 72 bus_space_handle_t dm_bsh; /* RAMBO registers */ 73 bus_dma_tag_t sc_dmat; 74 bus_dmamap_t sc_dmamap; 75 uint8_t **sc_dmaaddr; 76 size_t *sc_dmalen; 77 size_t sc_dmasize; 78 int sc_flags; 79 #define DMA_IDLE 0x0 80 #define DMA_PULLUP 0x1 81 #define DMA_ACTIVE 0x2 82 #define DMA_MAPLOADED 0x4 83 uint32_t dm_mode; 84 int dm_curseg; 85 }; 86 87 static int ascmatch(device_t, cfdata_t, void *); 88 static void ascattach(device_t, device_t, void *); 89 90 CFATTACH_DECL_NEW(asc, sizeof(struct asc_softc), 91 ascmatch, ascattach, NULL, NULL); 92 93 /* 94 * Functions and the switch for the MI code. 95 */ 96 static uint8_t asc_read_reg(struct ncr53c9x_softc *, int); 97 static void asc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 98 static int asc_dma_isintr(struct ncr53c9x_softc *); 99 static void asc_dma_reset(struct ncr53c9x_softc *); 100 static int asc_dma_intr(struct ncr53c9x_softc *); 101 static int asc_dma_setup(struct ncr53c9x_softc *, uint8_t **, 102 size_t *, int, size_t *); 103 static void asc_dma_go(struct ncr53c9x_softc *); 104 static void asc_dma_stop(struct ncr53c9x_softc *); 105 static int asc_dma_isactive(struct ncr53c9x_softc *); 106 107 static struct ncr53c9x_glue asc_glue = { 108 asc_read_reg, 109 asc_write_reg, 110 asc_dma_isintr, 111 asc_dma_reset, 112 asc_dma_intr, 113 asc_dma_setup, 114 asc_dma_go, 115 asc_dma_stop, 116 asc_dma_isactive, 117 NULL, /* gl_clear_latched_intr */ 118 }; 119 120 static int asc_intr(void *); 121 122 #define MAX_SCSI_XFER (64 * 1024) 123 #define MAX_DMA_SZ MAX_SCSI_XFER 124 #define DMA_SEGS (MAX_DMA_SZ / PAGE_SIZE) 125 126 static int 127 ascmatch(device_t parent, cfdata_t cf, void *aux) 128 { 129 130 return 1; 131 } 132 133 static void 134 ascattach(device_t parent, device_t self, void *aux) 135 { 136 struct asc_softc *esc = device_private(self); 137 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 138 struct confargs *ca = aux; 139 140 /* 141 * Set up glue for MI code early; we use some of it here. 142 */ 143 sc->sc_dev = self; 144 sc->sc_glue = &asc_glue; 145 146 esc->sc_bst = ca->ca_bustag; 147 esc->sc_dmat = ca->ca_dmatag; 148 149 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 150 16 * 4, /* sizeof (ncr53c9xreg) */ 151 BUS_SPACE_MAP_LINEAR, 152 &esc->sc_bsh) != 0) { 153 aprint_error(": cannot map registers\n"); 154 return; 155 } 156 157 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 158 BUS_SPACE_MAP_LINEAR, &esc->dm_bsh) != 0) { 159 aprint_error(": cannot map DMA registers\n"); 160 return; 161 } 162 163 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 164 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, BUS_DMA_WAITOK, 165 &esc->sc_dmamap) != 0) { 166 aprint_error(": failed to create dmamap\n"); 167 return; 168 } 169 170 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 171 device_xname(self), "intr"); 172 173 esc->sc_flags = DMA_IDLE; 174 asc_dma_reset(sc); 175 176 /* Other settings */ 177 sc->sc_id = 7; 178 sc->sc_freq = 24; /* 24 MHz clock */ 179 180 /* 181 * Setup for genuine NCR 53C94 SCSI Controller 182 */ 183 184 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 185 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 186 sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI; 187 sc->sc_rev = NCR_VARIANT_NCR53C94; 188 189 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 190 sc->sc_maxxfer = MAX_SCSI_XFER; 191 192 #ifdef OLDNCR 193 if (NCR_READ_REG(sc, NCR_CFG3) == 0) { 194 aprint_normal(" [old revision]"); 195 sc->sc_cfg2 = 0; 196 sc->sc_cfg3 = 0; 197 sc->sc_minsync = 0; 198 } 199 #endif 200 201 sc->sc_adapter.adapt_minphys = minphys; 202 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 203 ncr53c9x_attach(sc); 204 205 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 206 } 207 208 /* 209 * Glue functions. 210 */ 211 212 static uint8_t 213 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 214 { 215 struct asc_softc *esc = (struct asc_softc *)sc; 216 217 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 218 } 219 220 static void 221 asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 222 { 223 struct asc_softc *esc = (struct asc_softc *)sc; 224 225 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 226 } 227 228 static void 229 dma_status(struct ncr53c9x_softc *sc) 230 { 231 struct asc_softc *esc = (struct asc_softc *)sc; 232 int count; 233 int stat; 234 void *addr; 235 uint32_t tc; 236 237 tc = (asc_read_reg(sc, NCR_TCM) << 8) + asc_read_reg(sc, NCR_TCL); 238 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 239 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 240 addr = (void *)bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 241 242 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 243 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 244 count, addr, stat, tc, 245 asc_read_reg(sc, NCR_STAT), 246 asc_read_reg(sc, NCR_FFLAG)); 247 } 248 249 static inline void 250 check_fifo(struct asc_softc *esc) 251 { 252 int i = 100; 253 254 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 255 RAMBO_MODE) & RB_FIFO_EMPTY)) { 256 DELAY(1); 257 i--; 258 } 259 260 if (i == 0) { 261 dma_status((void *)esc); 262 panic("fifo didn't flush"); 263 } 264 } 265 266 static int 267 asc_dma_isintr(struct ncr53c9x_softc *sc) 268 { 269 270 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 271 } 272 273 static void 274 asc_dma_reset(struct ncr53c9x_softc *sc) 275 { 276 struct asc_softc *esc = (struct asc_softc *)sc; 277 278 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 279 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 280 RB_CLRFIFO|RB_CLRERROR); 281 DELAY(10); 282 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 283 284 if (esc->sc_flags & DMA_MAPLOADED) 285 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 286 287 esc->sc_flags = DMA_IDLE; 288 } 289 290 /* 291 * Setup a DMA transfer 292 */ 293 294 static int 295 asc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 296 int datain, size_t *dmasize) 297 { 298 struct asc_softc *esc = (struct asc_softc *)sc; 299 paddr_t paddr; 300 size_t count, blocks; 301 int prime, err; 302 303 #ifdef DIAGNOSTIC 304 if (esc->sc_flags & DMA_ACTIVE) { 305 dma_status(sc); 306 panic("DMA active"); 307 } 308 #endif 309 310 esc->sc_dmaaddr = addr; 311 esc->sc_dmalen = len; 312 esc->sc_dmasize = *dmasize; 313 esc->sc_flags = datain ? DMA_PULLUP : 0; 314 315 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 316 *addr, *len, datain, esc->sc_dmasize)); 317 318 if (esc->sc_dmasize == 0) 319 return 0; 320 321 /* have dmamap for the transfering addresses */ 322 if ((err = bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 323 *esc->sc_dmaaddr, esc->sc_dmasize, NULL /* kernel address */, BUS_DMA_NOWAIT)) != 0) 324 panic("%s: bus_dmamap_load err=%d", 325 device_xname(sc->sc_dev), err); 326 327 esc->sc_flags |= DMA_MAPLOADED; 328 329 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 330 count = esc->sc_dmamap->dm_segs[0].ds_len; 331 prime = (uint32_t)paddr & 0x3f; 332 blocks = (prime + count + 63) >> 6; 333 334 esc->dm_mode = datain ? RB_DMA_WR : RB_DMA_RD; 335 336 /* Set transfer direction and disable DMA */ 337 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 338 339 /* Load DMA transfer address */ 340 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr & ~0x3f); 341 342 /* Load number of blocks to DMA (1 block = 64 bytes) */ 343 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 344 345 /* If non block-aligned transfer prime FIFO manually */ 346 if (prime) { 347 /* Enable DMA to prime the FIFO buffer */ 348 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 349 RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE); 350 351 if (esc->sc_flags & DMA_PULLUP) { 352 /* Read from NCR 53c94 controller*/ 353 uint16_t *p; 354 355 p = (uint16_t *)((uint32_t)*esc->sc_dmaaddr & ~0x3f); 356 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 357 RAMBO_FIFO, p, prime>>1); 358 } else 359 /* Write to NCR 53C94 controller */ 360 while (prime > 0) { 361 (void)bus_space_read_2(esc->sc_bst, esc->dm_bsh, 362 RAMBO_FIFO); 363 prime -= 2; 364 } 365 /* Leave DMA disabled while we setup NCR controller */ 366 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 367 esc->dm_mode); 368 } 369 370 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 0, esc->sc_dmasize, 371 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 372 373 esc->dm_curseg = 0; 374 esc->dm_mode |= RB_DMA_ENABLE; 375 if (esc->sc_dmamap->dm_nsegs > 1) 376 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 377 378 return 0; 379 } 380 381 static void 382 asc_dma_go(struct ncr53c9x_softc *sc) 383 { 384 struct asc_softc *esc = (struct asc_softc *)sc; 385 386 /* Start DMA */ 387 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 388 389 esc->sc_flags |= DMA_ACTIVE; 390 } 391 392 static int 393 asc_dma_intr(struct ncr53c9x_softc *sc) 394 { 395 struct asc_softc *esc = (struct asc_softc *)sc; 396 397 size_t resid, len; 398 int trans; 399 uint32_t status; 400 u_int tcl, tcm; 401 402 #ifdef DIAGNOSTIC 403 if ((esc->sc_flags & DMA_ACTIVE) == 0) { 404 dma_status(sc); 405 panic("DMA not active"); 406 } 407 #endif 408 409 resid = 0; 410 if ((esc->sc_flags & DMA_PULLUP) == 0 && 411 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 412 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 413 DELAY(10); 414 } 415 416 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 417 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 418 419 if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 420 NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 421 return 0; 422 } 423 424 trans = esc->sc_dmasize - resid; 425 if (trans < 0) { /* transferred < 0 ? */ 426 printf("%s: xfer (%d) > req (%d)\n", 427 __func__, trans, esc->sc_dmasize); 428 trans = esc->sc_dmasize; 429 } 430 431 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 432 tcl, tcm, trans, resid)); 433 434 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 435 436 if ((status & RB_FIFO_EMPTY) == 0) { /* Data left in RAMBO FIFO */ 437 if ((esc->sc_flags & DMA_PULLUP) != 0) { /* SCSI Read */ 438 paddr_t ptr; 439 uint16_t *p; 440 441 resid = status & 0x1f; 442 443 /* take the address of block to fixed up */ 444 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 445 RAMBO_CADDR); 446 /* find the starting address of fractional data */ 447 p = (uint16_t *)MIPS_PHYS_TO_KSEG0(ptr + (resid << 1)); 448 449 /* duplicate trailing data to FIFO for force flush */ 450 len = RB_BLK_CNT - resid; 451 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 452 RAMBO_FIFO, p, len); 453 check_fifo(esc); 454 } else { /* SCSI Write */ 455 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 456 RAMBO_MODE, 0); 457 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 458 RAMBO_MODE, RB_CLRFIFO); 459 } 460 } 461 462 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 463 464 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 465 466 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 467 0, esc->sc_dmasize, 468 (esc->sc_flags & DMA_PULLUP) != 0 ? 469 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 470 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 471 472 *esc->sc_dmaaddr += trans; 473 *esc->sc_dmalen -= trans; 474 475 esc->sc_flags = DMA_IDLE; 476 477 return 0; 478 } 479 480 481 static void 482 asc_dma_stop(struct ncr53c9x_softc *sc) 483 { 484 struct asc_softc *esc = (struct asc_softc *)sc; 485 486 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 487 if ((esc->sc_flags & DMA_MAPLOADED) != 0) 488 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 489 esc->sc_flags = DMA_IDLE; 490 } 491 492 static int 493 asc_dma_isactive(struct ncr53c9x_softc *sc) 494 { 495 struct asc_softc *esc = (struct asc_softc *)sc; 496 return (esc->sc_flags & DMA_ACTIVE) != 0 ? 1 : 0; 497 } 498 499 static void 500 rambo_dma_chain(struct asc_softc *esc) 501 { 502 int seg; 503 size_t count, blocks; 504 paddr_t paddr; 505 506 seg = ++esc->dm_curseg; 507 508 #ifdef DIAGNOSTIC 509 if ((esc->sc_flags & DMA_ACTIVE) == 0 || seg > esc->sc_dmamap->dm_nsegs) 510 panic("Unexpected DMA chaining intr"); 511 512 /* Interrupt can only occur at terminal count, but double check */ 513 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 514 dma_status((void *)esc); 515 panic("rambo blkcnt != 0"); 516 } 517 #endif 518 519 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 520 count = esc->sc_dmamap->dm_segs[seg].ds_len; 521 blocks = (count + 63) >> 6; 522 523 /* Disable DMA interrupt if last segment */ 524 if (seg + 1 > esc->sc_dmamap->dm_nsegs) { 525 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 526 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 527 } 528 529 /* Load transfer address for next DMA chain */ 530 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 531 532 /* DMA restarts when we enter a new block count */ 533 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 534 } 535 536 static int 537 asc_intr(void *arg) 538 { 539 uint32_t dma_stat; 540 struct asc_softc *esc = arg; 541 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 542 543 esc->sc_intrcnt.ev_count++; 544 545 /* Check for RAMBO DMA Interrupt */ 546 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 547 if ((dma_stat & RB_INTR_PEND) != 0) { 548 rambo_dma_chain(esc); 549 } 550 /* Check for NCR 53c94 interrupt */ 551 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 552 ncr53c9x_intr(sc); 553 } 554 return 0; 555 } 556
Indexes created Thu Oct 02 01:09:59 GMT 2025