asc.c revision 1.4
1 /* $NetBSD: asc.c,v 1.4 2000/08/29 08:24:06 wdk Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 size_t sc_blkcnt; 74 int sc_flags; 75 #define DMA_IDLE 0x0 76 #define DMA_PULLUP 0x1 77 #define DMA_ACTIVE 0x2 78 #define DMA_MAPLOADED 0x4 79 u_int32_t dm_mode; 80 int dm_curseg; 81 }; 82 83 static int ascmatch __P((struct device *, struct cfdata *, void *)); 84 static void ascattach __P((struct device *, struct device *, void *)); 85 86 struct cfattach asc_ca = { 87 sizeof(struct asc_softc), ascmatch, ascattach 88 }; 89 90 /* 91 * Functions and the switch for the MI code. 92 */ 93 static u_char asc_read_reg __P((struct ncr53c9x_softc *, int)); 94 static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 95 static int asc_dma_isintr __P((struct ncr53c9x_softc *)); 96 static void asc_dma_reset __P((struct ncr53c9x_softc *)); 97 static int asc_dma_intr __P((struct ncr53c9x_softc *)); 98 static int asc_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 99 size_t *, int, size_t *)); 100 static void asc_dma_go __P((struct ncr53c9x_softc *)); 101 static void asc_dma_stop __P((struct ncr53c9x_softc *)); 102 static int asc_dma_isactive __P((struct ncr53c9x_softc *)); 103 104 static struct ncr53c9x_glue asc_glue = { 105 asc_read_reg, 106 asc_write_reg, 107 asc_dma_isintr, 108 asc_dma_reset, 109 asc_dma_intr, 110 asc_dma_setup, 111 asc_dma_go, 112 asc_dma_stop, 113 asc_dma_isactive, 114 NULL, /* gl_clear_latched_intr */ 115 }; 116 117 static int asc_intr __P((void *)); 118 119 #define MAX_SCSI_XFER (64*1024) 120 #define MAX_DMA_SZ MAX_SCSI_XFER 121 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 122 123 static int 124 ascmatch(parent, cf, aux) 125 struct device *parent; 126 struct cfdata *cf; 127 void *aux; 128 { 129 return 1; 130 } 131 132 static void 133 ascattach(parent, self, aux) 134 struct device *parent, *self; 135 void *aux; 136 { 137 struct confargs *ca = aux; 138 struct asc_softc *esc = (void *)self; 139 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 140 141 /* 142 * Set up glue for MI code early; we use some of it here. 143 */ 144 sc->sc_glue = &asc_glue; 145 146 esc->sc_bst = ca->ca_bustag; 147 esc->sc_dmat = ca->ca_dmatag; 148 149 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 150 16*4, /* sizeof (ncr53c9xreg) */ 151 BUS_SPACE_MAP_LINEAR, 152 &esc->sc_bsh) != 0) { 153 printf(": cannot map registers\n"); 154 return; 155 } 156 157 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 158 BUS_SPACE_MAP_LINEAR, 159 &esc->dm_bsh) != 0) { 160 printf(": cannot map dma registers\n"); 161 return; 162 } 163 164 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 165 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 166 BUS_DMA_WAITOK, 167 &esc->sc_dmamap) != 0) { 168 printf(": failed to create dmamap\n"); 169 return; 170 } 171 172 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 173 self->dv_xname, "intr"); 174 175 esc->sc_flags = DMA_IDLE; 176 asc_dma_reset(sc); 177 178 /* Other settings */ 179 sc->sc_id = 7; 180 sc->sc_freq = 24; /* 24 MHz clock */ 181 182 /* 183 * Setup for genuine NCR 53C94 SCSI Controller 184 */ 185 186 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 187 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 188 sc->sc_cfg3 = 0; /* NCRCFG3_CDB; */ 189 sc->sc_rev = NCR_VARIANT_NCR53C94; 190 191 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 192 sc->sc_maxxfer = MAX_SCSI_XFER; 193 194 #ifdef OLDNCR 195 if (!NCR_READ_REG(sc, NCR_CFG3)) { 196 printf(" [old revision]"); 197 sc->sc_cfg2 = 0; 198 sc->sc_cfg3 = 0; 199 sc->sc_minsync = 0; 200 } 201 #endif 202 203 ncr53c9x_dmaselect = 0; 204 ncr53c9x_attach(sc, NULL, NULL); 205 206 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 207 } 208 209 /* 210 * Glue functions. 211 */ 212 213 u_char 214 asc_read_reg(sc, reg) 215 struct ncr53c9x_softc *sc; 216 int reg; 217 { 218 struct asc_softc *esc = (struct asc_softc *)sc; 219 220 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 221 } 222 223 void 224 asc_write_reg(sc, reg, val) 225 struct ncr53c9x_softc *sc; 226 int reg; 227 u_char val; 228 { 229 struct asc_softc *esc = (struct asc_softc *)sc; 230 231 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 232 } 233 234 void 235 dma_status(sc) 236 struct ncr53c9x_softc *sc; 237 { 238 struct asc_softc *esc = (struct asc_softc *)sc; 239 int count; 240 int stat; 241 void *addr; 242 u_int32_t tc; 243 244 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 245 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 246 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 247 addr = (void *) 248 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 249 250 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 251 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 252 count, addr, stat, tc, 253 asc_read_reg(sc, NCR_STAT), 254 asc_read_reg(sc, NCR_FFLAG)); 255 } 256 257 static __inline void 258 check_fifo(esc) 259 struct asc_softc *esc; 260 { 261 register int i=16; 262 263 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 264 RAMBO_MODE) & RB_FIFO_EMPTY)) { 265 DELAY(1); i--; 266 } 267 268 if (!i) { 269 dma_status((void *)esc); 270 panic("fifo didn't flush"); 271 } 272 } 273 274 int 275 asc_dma_isintr(sc) 276 struct ncr53c9x_softc *sc; 277 { 278 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 279 } 280 281 void 282 asc_dma_reset(sc) 283 struct ncr53c9x_softc *sc; 284 { 285 struct asc_softc *esc = (struct asc_softc *)sc; 286 287 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 288 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 289 RB_CLRFIFO|RB_CLRERROR); 290 DELAY(10); 291 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 292 293 if (esc->sc_flags & DMA_MAPLOADED) 294 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 295 296 esc->sc_flags = DMA_IDLE; 297 } 298 299 /* 300 * Setup a DMA transfer 301 */ 302 303 static int 304 asc_dma_setup(sc, addr, len, datain, dmasize) 305 struct ncr53c9x_softc *sc; 306 caddr_t *addr; 307 size_t *len; 308 int datain; 309 size_t *dmasize; 310 { 311 struct asc_softc *esc = (struct asc_softc *)sc; 312 paddr_t paddr; 313 size_t count, blocks; 314 int prime, err; 315 316 #ifdef DIAGNOSTIC 317 if (esc->sc_flags & DMA_ACTIVE) { 318 dma_status(sc); 319 panic("DMA active"); 320 } 321 #endif 322 323 /* Flush FIFO from previous operation */ 324 325 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 326 RB_CLRFIFO|RB_CLRERROR); 327 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 328 329 esc->sc_dmaaddr = addr; 330 esc->sc_dmalen = len; 331 esc->sc_dmasize = *dmasize; 332 esc->sc_flags = datain ? DMA_PULLUP : 0; 333 334 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 335 *addr, *len, datain, esc->sc_dmasize)); 336 337 /* have dmamap for the transfering addresses */ 338 if (err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 339 *esc->sc_dmaaddr, esc->sc_dmasize, 340 NULL /* kernel address */, 341 BUS_DMA_NOWAIT)) 342 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 343 344 esc->sc_flags |= DMA_MAPLOADED; 345 346 /* No cache flush required for R3000 processors */ 347 348 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 349 count = esc->sc_dmamap->dm_segs[0].ds_len; 350 blocks = (((u_int32_t)*addr & 0x3f) + count + 63) >> 6; 351 352 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD) | RB_DMA_ENABLE; 353 if (esc->sc_dmamap->dm_nsegs > 1) 354 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 355 356 /* Load DMA transfer address */ 357 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 358 paddr & ~0x3f); 359 360 /* Set count to zero bytes as this will prevent DMA from starting */ 361 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 362 363 /* Set transfer direction and enable DMA FIFO */ 364 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 365 366 /* If non block-aligned transfer prime FIFO manually */ 367 prime = (u_int32_t)*esc->sc_dmaaddr & 0x3f; 368 if (prime) { 369 if (esc->sc_flags & DMA_PULLUP) { 370 u_int16_t *p; 371 372 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 373 /* Read from NCR 53c94 controller*/ 374 while (prime > 0) { 375 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 376 RAMBO_FIFO, *p++); 377 prime -= 2; 378 } 379 } else { 380 /* Fetch the first block */ 381 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 382 RAMBO_BLKCNT, 1); 383 while (prime > 0) { 384 (void)bus_space_read_2(esc->sc_bst, 385 esc->dm_bsh, 386 RAMBO_FIFO); 387 prime -= 2; 388 } 389 blocks--; /* 1 block has been prefetched */ 390 } 391 } 392 esc->sc_blkcnt = blocks; 393 esc->dm_curseg = 0; 394 return 0; 395 } 396 397 void 398 asc_dma_go(sc) 399 struct ncr53c9x_softc *sc; 400 { 401 struct asc_softc *esc = (struct asc_softc *)sc; 402 403 /* Load block count to start transfer */ 404 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 405 RAMBO_BLKCNT, esc->sc_blkcnt); 406 esc->sc_flags |= DMA_ACTIVE; 407 } 408 409 int 410 asc_dma_intr(sc) 411 struct ncr53c9x_softc *sc; 412 { 413 struct asc_softc *esc = (struct asc_softc *)sc; 414 415 size_t resid, len; 416 int trans; 417 u_int32_t status; 418 u_int tcl, tcm; 419 420 #ifdef DIAGNOSTIC 421 if (!(esc->sc_flags & DMA_ACTIVE)) { 422 dma_status(sc); 423 panic("DMA not active"); 424 } 425 #endif 426 427 if ((resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 428 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 429 DELAY(10); 430 } 431 432 resid = (tcl = NCR_READ_REG(sc, NCR_TCL)) + 433 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 434 trans = esc->sc_dmasize - resid; 435 if (trans < 0) { /* transferred < 0 ? */ 436 printf("asc_intr: xfer (%d) > req (%d)\n", 437 trans, esc->sc_dmasize); 438 trans = esc->sc_dmasize; 439 } 440 441 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 442 tcl, tcm, trans, resid)); 443 444 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 445 446 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 447 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 448 paddr_t ptr; 449 u_int16_t *p; 450 451 resid = status & 0x1f; 452 453 /* take the address of block to fixed up */ 454 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 455 RAMBO_CADDR); 456 /* find the starting address of fractional data */ 457 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 458 459 /* XXX - disable DMA xfer before flushing FIFO ? */ 460 len = RB_BLK_CNT - resid; 461 while (len--) { 462 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 463 RAMBO_FIFO, *p++); 464 } 465 check_fifo(esc); 466 } else { /* SCSI Write */ 467 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 468 RAMBO_MODE, 0); 469 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 470 RAMBO_MODE, RB_CLRFIFO); 471 } 472 } 473 474 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 475 476 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 477 478 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 479 0, esc->sc_dmasize, 480 (esc->sc_flags & DMA_PULLUP) 481 ? BUS_DMASYNC_POSTREAD 482 : BUS_DMASYNC_POSTWRITE); 483 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 484 485 *esc->sc_dmaaddr += trans; 486 *esc->sc_dmalen -= trans; 487 488 esc->sc_flags = DMA_IDLE; 489 490 return 0; 491 } 492 493 494 void 495 asc_dma_stop(sc) 496 struct ncr53c9x_softc *sc; 497 { 498 struct asc_softc *esc = (struct asc_softc *)sc; 499 500 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 501 if (esc->sc_flags & DMA_MAPLOADED) 502 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 503 esc->sc_flags = DMA_IDLE; 504 } 505 506 int 507 asc_dma_isactive(sc) 508 struct ncr53c9x_softc *sc; 509 { 510 struct asc_softc *esc = (struct asc_softc *)sc; 511 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 512 } 513 514 void 515 rambo_dma_chain(esc) 516 struct asc_softc *esc; 517 { 518 int seg; 519 size_t count, blocks; 520 paddr_t paddr; 521 522 seg = ++esc->dm_curseg; 523 524 if (!(esc->sc_flags & DMA_PULLUP)) /* Wait for FIFO during write */ 525 check_fifo(esc); 526 527 #ifdef DIAGNOSTIC 528 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 529 panic("Unexpected DMA chaining intr"); 530 531 /* Interrupt can only occur at terminal count, but double check */ 532 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 533 dma_status((void *)esc); 534 panic("rambo blkcnt != 0"); 535 } 536 #endif 537 538 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 539 count = esc->sc_dmamap->dm_segs[seg].ds_len; 540 blocks = (count + 63) >> 6; 541 542 /* Disable DMA interrupt if last segment */ 543 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 544 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 545 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 546 } 547 548 /* Load transfer address for next DMA chain */ 549 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 550 551 /* DMA restarts when we enter a new block count */ 552 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 553 } 554 555 int 556 asc_intr(arg) 557 void *arg; 558 { 559 register u_int32_t dma_stat; 560 struct asc_softc *esc = arg; 561 struct ncr53c9x_softc *sc = arg; 562 563 esc->sc_intrcnt.ev_count++; 564 565 /* Check for RAMBO DMA Interrupt */ 566 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 567 if (dma_stat & RB_INTR_PEND) { 568 rambo_dma_chain(esc); 569 } 570 /* Check for NCR 53c94 interrupt */ 571 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 572 ncr53c9x_intr(sc); 573 } 574 return 0; 575 } 576
Indexes created Thu Oct 02 01:09:59 GMT 2025