asc.c revision 1.6
1 /* $NetBSD: asc.c,v 1.6 2000/12/03 04:51:05 matt Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 size_t sc_blkcnt; 74 int sc_flags; 75 #define DMA_IDLE 0x0 76 #define DMA_PULLUP 0x1 77 #define DMA_ACTIVE 0x2 78 #define DMA_MAPLOADED 0x4 79 u_int32_t dm_mode; 80 int dm_curseg; 81 }; 82 83 static int ascmatch (struct device *, struct cfdata *, void *); 84 static void ascattach (struct device *, struct device *, void *); 85 86 struct cfattach asc_ca = { 87 sizeof(struct asc_softc), ascmatch, ascattach 88 }; 89 90 /* 91 * Functions and the switch for the MI code. 92 */ 93 static u_char asc_read_reg (struct ncr53c9x_softc *, int); 94 static void asc_write_reg (struct ncr53c9x_softc *, int, u_char); 95 static int asc_dma_isintr (struct ncr53c9x_softc *); 96 static void asc_dma_reset (struct ncr53c9x_softc *); 97 static int asc_dma_intr (struct ncr53c9x_softc *); 98 static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *, 99 size_t *, int, size_t *); 100 static void asc_dma_go (struct ncr53c9x_softc *); 101 static void asc_dma_stop (struct ncr53c9x_softc *); 102 static int asc_dma_isactive (struct ncr53c9x_softc *); 103 104 static struct ncr53c9x_glue asc_glue = { 105 asc_read_reg, 106 asc_write_reg, 107 asc_dma_isintr, 108 asc_dma_reset, 109 asc_dma_intr, 110 asc_dma_setup, 111 asc_dma_go, 112 asc_dma_stop, 113 asc_dma_isactive, 114 NULL, /* gl_clear_latched_intr */ 115 }; 116 117 static int asc_intr (void *); 118 119 #define MAX_SCSI_XFER (64*1024) 120 #define MAX_DMA_SZ MAX_SCSI_XFER 121 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 122 123 static int 124 ascmatch(struct device *parent, struct cfdata *cf, void *aux) 125 { 126 return 1; 127 } 128 129 static void 130 ascattach(struct device *parent, struct device *self, void *aux) 131 { 132 struct confargs *ca = aux; 133 struct asc_softc *esc = (void *)self; 134 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 135 136 /* 137 * Set up glue for MI code early; we use some of it here. 138 */ 139 sc->sc_glue = &asc_glue; 140 141 esc->sc_bst = ca->ca_bustag; 142 esc->sc_dmat = ca->ca_dmatag; 143 144 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 145 16*4, /* sizeof (ncr53c9xreg) */ 146 BUS_SPACE_MAP_LINEAR, 147 &esc->sc_bsh) != 0) { 148 printf(": cannot map registers\n"); 149 return; 150 } 151 152 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 153 BUS_SPACE_MAP_LINEAR, 154 &esc->dm_bsh) != 0) { 155 printf(": cannot map dma registers\n"); 156 return; 157 } 158 159 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 160 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 161 BUS_DMA_WAITOK, 162 &esc->sc_dmamap) != 0) { 163 printf(": failed to create dmamap\n"); 164 return; 165 } 166 167 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 168 self->dv_xname, "intr"); 169 170 esc->sc_flags = DMA_IDLE; 171 asc_dma_reset(sc); 172 173 /* Other settings */ 174 sc->sc_id = 7; 175 sc->sc_freq = 24; /* 24 MHz clock */ 176 177 /* 178 * Setup for genuine NCR 53C94 SCSI Controller 179 */ 180 181 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 182 sc->sc_cfg2 = NCRCFG2_SCSI2; /* | NCRCFG2_FE */ 183 sc->sc_cfg3 = 0; /* NCRCFG3_CDB; */ 184 sc->sc_rev = NCR_VARIANT_NCR53C94; 185 186 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 187 sc->sc_maxxfer = MAX_SCSI_XFER; 188 189 #ifdef OLDNCR 190 if (!NCR_READ_REG(sc, NCR_CFG3)) { 191 printf(" [old revision]"); 192 sc->sc_cfg2 = 0; 193 sc->sc_cfg3 = 0; 194 sc->sc_minsync = 0; 195 } 196 #endif 197 198 ncr53c9x_dmaselect = 0; 199 ncr53c9x_attach(sc, NULL, NULL); 200 201 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 202 } 203 204 /* 205 * Glue functions. 206 */ 207 208 static u_char 209 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 210 { 211 struct asc_softc *esc = (struct asc_softc *)sc; 212 213 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 214 } 215 216 static void 217 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 218 { 219 struct asc_softc *esc = (struct asc_softc *)sc; 220 221 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 222 } 223 224 static void 225 dma_status(struct ncr53c9x_softc *sc) 226 { 227 struct asc_softc *esc = (struct asc_softc *)sc; 228 int count; 229 int stat; 230 void *addr; 231 u_int32_t tc; 232 233 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 234 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 235 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 236 addr = (void *) 237 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 238 239 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 240 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 241 count, addr, stat, tc, 242 asc_read_reg(sc, NCR_STAT), 243 asc_read_reg(sc, NCR_FFLAG)); 244 } 245 246 static __inline void 247 check_fifo(struct asc_softc *esc) 248 { 249 register int i=100; 250 251 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 252 RAMBO_MODE) & RB_FIFO_EMPTY)) { 253 DELAY(1); i--; 254 } 255 256 if (!i) { 257 dma_status((void *)esc); 258 panic("fifo didn't flush"); 259 } 260 } 261 262 static int 263 asc_dma_isintr(struct ncr53c9x_softc *sc) 264 { 265 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 266 } 267 268 static void 269 asc_dma_reset(struct ncr53c9x_softc *sc) 270 { 271 struct asc_softc *esc = (struct asc_softc *)sc; 272 273 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 274 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 275 RB_CLRFIFO|RB_CLRERROR); 276 DELAY(10); 277 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 278 279 if (esc->sc_flags & DMA_MAPLOADED) 280 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 281 282 esc->sc_flags = DMA_IDLE; 283 } 284 285 /* 286 * Setup a DMA transfer 287 */ 288 289 static int 290 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 291 int datain, size_t *dmasize) 292 { 293 struct asc_softc *esc = (struct asc_softc *)sc; 294 paddr_t paddr; 295 size_t count, blocks; 296 int prime, err; 297 298 #ifdef DIAGNOSTIC 299 if (esc->sc_flags & DMA_ACTIVE) { 300 dma_status(sc); 301 panic("DMA active"); 302 } 303 #endif 304 305 esc->sc_dmaaddr = addr; 306 esc->sc_dmalen = len; 307 esc->sc_dmasize = *dmasize; 308 esc->sc_flags = datain ? DMA_PULLUP : 0; 309 310 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 311 *addr, *len, datain, esc->sc_dmasize)); 312 313 if (esc->sc_dmasize == 0) 314 return 0; 315 316 /* have dmamap for the transfering addresses */ 317 if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 318 *esc->sc_dmaaddr, esc->sc_dmasize, 319 NULL /* kernel address */, 320 BUS_DMA_NOWAIT)) != 0) 321 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 322 323 esc->sc_flags |= DMA_MAPLOADED; 324 325 /* No cache flush required for R3000 processors */ 326 327 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 328 count = esc->sc_dmamap->dm_segs[0].ds_len; 329 blocks = (((u_int32_t)*addr & 0x3f) + count + 63) >> 6; 330 331 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD) | RB_DMA_ENABLE; 332 if (esc->sc_dmamap->dm_nsegs > 1) 333 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 334 335 /* Load DMA transfer address */ 336 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 337 paddr & ~0x3f); 338 339 /* Set count to zero bytes as this will prevent DMA from starting */ 340 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 341 342 /* Set transfer direction and enable DMA FIFO */ 343 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 344 345 /* If non block-aligned transfer prime FIFO manually */ 346 prime = (u_int32_t)*esc->sc_dmaaddr & 0x3f; 347 if (prime) { 348 if (esc->sc_flags & DMA_PULLUP) { 349 /* Read from NCR 53c94 controller*/ 350 u_int16_t *p; 351 352 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 353 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 354 RAMBO_FIFO, p, prime>>1); 355 } else { 356 /* Fetch the first block */ 357 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 358 RAMBO_BLKCNT, 1); 359 while (prime > 0) { 360 (void)bus_space_read_2(esc->sc_bst, 361 esc->dm_bsh, 362 RAMBO_FIFO); 363 prime -= 2; 364 } 365 blocks--; /* 1 block has been prefetched */ 366 } 367 } 368 esc->sc_blkcnt = blocks; 369 esc->dm_curseg = 0; 370 return 0; 371 } 372 373 static void 374 asc_dma_go(struct ncr53c9x_softc *sc) 375 { 376 struct asc_softc *esc = (struct asc_softc *)sc; 377 378 /* Load block count to start transfer */ 379 bus_space_write_2(esc->sc_bst, esc->dm_bsh, 380 RAMBO_BLKCNT, esc->sc_blkcnt); 381 esc->sc_flags |= DMA_ACTIVE; 382 } 383 384 static int 385 asc_dma_intr(struct ncr53c9x_softc *sc) 386 { 387 struct asc_softc *esc = (struct asc_softc *)sc; 388 389 size_t resid, len; 390 int trans; 391 u_int32_t status; 392 u_int tcl, tcm; 393 394 #ifdef DIAGNOSTIC 395 if (!(esc->sc_flags & DMA_ACTIVE)) { 396 dma_status(sc); 397 panic("DMA not active"); 398 } 399 #endif 400 401 resid = 0; 402 if (!(esc->sc_flags & DMA_PULLUP) && 403 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 404 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 405 DELAY(10); 406 } 407 408 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 409 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 410 411 if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 412 NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 413 return 0; 414 } 415 416 trans = esc->sc_dmasize - resid; 417 if (trans < 0) { /* transferred < 0 ? */ 418 printf("asc_intr: xfer (%d) > req (%d)\n", 419 trans, esc->sc_dmasize); 420 trans = esc->sc_dmasize; 421 } 422 423 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 424 tcl, tcm, trans, resid)); 425 426 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 427 428 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 429 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 430 paddr_t ptr; 431 u_int16_t *p; 432 433 resid = status & 0x1f; 434 435 /* take the address of block to fixed up */ 436 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 437 RAMBO_CADDR); 438 /* find the starting address of fractional data */ 439 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 440 441 /* duplicate trailing data to FIFO for force flush */ 442 len = RB_BLK_CNT - resid; 443 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 444 RAMBO_FIFO, p, len); 445 check_fifo(esc); 446 } else { /* SCSI Write */ 447 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 448 RAMBO_MODE, 0); 449 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 450 RAMBO_MODE, RB_CLRFIFO); 451 } 452 } 453 454 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 455 456 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 457 458 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 459 0, esc->sc_dmasize, 460 (esc->sc_flags & DMA_PULLUP) 461 ? BUS_DMASYNC_POSTREAD 462 : BUS_DMASYNC_POSTWRITE); 463 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 464 465 *esc->sc_dmaaddr += trans; 466 *esc->sc_dmalen -= trans; 467 468 esc->sc_flags = DMA_IDLE; 469 470 return 0; 471 } 472 473 474 static void 475 asc_dma_stop(struct ncr53c9x_softc *sc) 476 { 477 struct asc_softc *esc = (struct asc_softc *)sc; 478 479 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 480 if (esc->sc_flags & DMA_MAPLOADED) 481 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 482 esc->sc_flags = DMA_IDLE; 483 } 484 485 static int 486 asc_dma_isactive(struct ncr53c9x_softc *sc) 487 { 488 struct asc_softc *esc = (struct asc_softc *)sc; 489 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 490 } 491 492 static void 493 rambo_dma_chain(struct asc_softc *esc) 494 { 495 int seg; 496 size_t count, blocks; 497 paddr_t paddr; 498 499 seg = ++esc->dm_curseg; 500 501 #ifdef DIAGNOSTIC 502 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 503 panic("Unexpected DMA chaining intr"); 504 505 /* Interrupt can only occur at terminal count, but double check */ 506 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 507 dma_status((void *)esc); 508 panic("rambo blkcnt != 0"); 509 } 510 #endif 511 512 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 513 count = esc->sc_dmamap->dm_segs[seg].ds_len; 514 blocks = (count + 63) >> 6; 515 516 /* Disable DMA interrupt if last segment */ 517 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 518 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 519 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 520 } 521 522 /* Load transfer address for next DMA chain */ 523 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 524 525 /* DMA restarts when we enter a new block count */ 526 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 527 } 528 529 static int 530 asc_intr(void *arg) 531 { 532 register u_int32_t dma_stat; 533 struct asc_softc *esc = arg; 534 struct ncr53c9x_softc *sc = arg; 535 536 esc->sc_intrcnt.ev_count++; 537 538 /* Check for RAMBO DMA Interrupt */ 539 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 540 if (dma_stat & RB_INTR_PEND) { 541 rambo_dma_chain(esc); 542 } 543 /* Check for NCR 53c94 interrupt */ 544 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 545 ncr53c9x_intr(sc); 546 } 547 return 0; 548 } 549
Indexes created Thu Oct 02 01:09:59 GMT 2025