asc.c revision 1.7
1 /* $NetBSD: asc.c,v 1.7 2001/03/05 05:04:29 wdk Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 int sc_flags; 74 #define DMA_IDLE 0x0 75 #define DMA_PULLUP 0x1 76 #define DMA_ACTIVE 0x2 77 #define DMA_MAPLOADED 0x4 78 u_int32_t dm_mode; 79 int dm_curseg; 80 }; 81 82 static int ascmatch (struct device *, struct cfdata *, void *); 83 static void ascattach (struct device *, struct device *, void *); 84 85 struct cfattach asc_ca = { 86 sizeof(struct asc_softc), ascmatch, ascattach 87 }; 88 89 /* 90 * Functions and the switch for the MI code. 91 */ 92 static u_char asc_read_reg (struct ncr53c9x_softc *, int); 93 static void asc_write_reg (struct ncr53c9x_softc *, int, u_char); 94 static int asc_dma_isintr (struct ncr53c9x_softc *); 95 static void asc_dma_reset (struct ncr53c9x_softc *); 96 static int asc_dma_intr (struct ncr53c9x_softc *); 97 static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *, 98 size_t *, int, size_t *); 99 static void asc_dma_go (struct ncr53c9x_softc *); 100 static void asc_dma_stop (struct ncr53c9x_softc *); 101 static int asc_dma_isactive (struct ncr53c9x_softc *); 102 103 static struct ncr53c9x_glue asc_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 asc_dma_isintr, 107 asc_dma_reset, 108 asc_dma_intr, 109 asc_dma_setup, 110 asc_dma_go, 111 asc_dma_stop, 112 asc_dma_isactive, 113 NULL, /* gl_clear_latched_intr */ 114 }; 115 116 static int asc_intr (void *); 117 118 #define MAX_SCSI_XFER (64*1024) 119 #define MAX_DMA_SZ MAX_SCSI_XFER 120 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 121 122 static int 123 ascmatch(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 return 1; 126 } 127 128 static void 129 ascattach(struct device *parent, struct device *self, void *aux) 130 { 131 struct confargs *ca = aux; 132 struct asc_softc *esc = (void *)self; 133 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 134 135 /* 136 * Set up glue for MI code early; we use some of it here. 137 */ 138 sc->sc_glue = &asc_glue; 139 140 esc->sc_bst = ca->ca_bustag; 141 esc->sc_dmat = ca->ca_dmatag; 142 143 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 144 16*4, /* sizeof (ncr53c9xreg) */ 145 BUS_SPACE_MAP_LINEAR, 146 &esc->sc_bsh) != 0) { 147 printf(": cannot map registers\n"); 148 return; 149 } 150 151 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 152 BUS_SPACE_MAP_LINEAR, 153 &esc->dm_bsh) != 0) { 154 printf(": cannot map dma registers\n"); 155 return; 156 } 157 158 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 159 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 160 BUS_DMA_WAITOK, 161 &esc->sc_dmamap) != 0) { 162 printf(": failed to create dmamap\n"); 163 return; 164 } 165 166 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 167 self->dv_xname, "intr"); 168 169 esc->sc_flags = DMA_IDLE; 170 asc_dma_reset(sc); 171 172 /* Other settings */ 173 sc->sc_id = 7; 174 sc->sc_freq = 24; /* 24 MHz clock */ 175 176 /* 177 * Setup for genuine NCR 53C94 SCSI Controller 178 */ 179 180 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 181 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 182 sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI; 183 sc->sc_rev = NCR_VARIANT_NCR53C94; 184 185 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 186 sc->sc_maxxfer = MAX_SCSI_XFER; 187 188 #ifdef OLDNCR 189 if (!NCR_READ_REG(sc, NCR_CFG3)) { 190 printf(" [old revision]"); 191 sc->sc_cfg2 = 0; 192 sc->sc_cfg3 = 0; 193 sc->sc_minsync = 0; 194 } 195 #endif 196 197 ncr53c9x_dmaselect = 0; 198 ncr53c9x_attach(sc, NULL, NULL); 199 200 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 201 } 202 203 /* 204 * Glue functions. 205 */ 206 207 static u_char 208 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 209 { 210 struct asc_softc *esc = (struct asc_softc *)sc; 211 212 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 213 } 214 215 static void 216 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 217 { 218 struct asc_softc *esc = (struct asc_softc *)sc; 219 220 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 221 } 222 223 static void 224 dma_status(struct ncr53c9x_softc *sc) 225 { 226 struct asc_softc *esc = (struct asc_softc *)sc; 227 int count; 228 int stat; 229 void *addr; 230 u_int32_t tc; 231 232 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 233 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 234 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 235 addr = (void *) 236 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 237 238 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 239 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 240 count, addr, stat, tc, 241 asc_read_reg(sc, NCR_STAT), 242 asc_read_reg(sc, NCR_FFLAG)); 243 } 244 245 static __inline void 246 check_fifo(struct asc_softc *esc) 247 { 248 register int i=100; 249 250 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 251 RAMBO_MODE) & RB_FIFO_EMPTY)) { 252 DELAY(1); i--; 253 } 254 255 if (!i) { 256 dma_status((void *)esc); 257 panic("fifo didn't flush"); 258 } 259 } 260 261 static int 262 asc_dma_isintr(struct ncr53c9x_softc *sc) 263 { 264 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 265 } 266 267 static void 268 asc_dma_reset(struct ncr53c9x_softc *sc) 269 { 270 struct asc_softc *esc = (struct asc_softc *)sc; 271 272 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 273 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 274 RB_CLRFIFO|RB_CLRERROR); 275 DELAY(10); 276 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 277 278 if (esc->sc_flags & DMA_MAPLOADED) 279 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 280 281 esc->sc_flags = DMA_IDLE; 282 } 283 284 /* 285 * Setup a DMA transfer 286 */ 287 288 static int 289 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 290 int datain, size_t *dmasize) 291 { 292 struct asc_softc *esc = (struct asc_softc *)sc; 293 paddr_t paddr; 294 size_t count, blocks; 295 int prime, err; 296 297 #ifdef DIAGNOSTIC 298 if (esc->sc_flags & DMA_ACTIVE) { 299 dma_status(sc); 300 panic("DMA active"); 301 } 302 #endif 303 304 esc->sc_dmaaddr = addr; 305 esc->sc_dmalen = len; 306 esc->sc_dmasize = *dmasize; 307 esc->sc_flags = datain ? DMA_PULLUP : 0; 308 309 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 310 *addr, *len, datain, esc->sc_dmasize)); 311 312 if (esc->sc_dmasize == 0) 313 return 0; 314 315 /* have dmamap for the transfering addresses */ 316 if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 317 *esc->sc_dmaaddr, esc->sc_dmasize, 318 NULL /* kernel address */, 319 BUS_DMA_NOWAIT)) != 0) 320 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 321 322 esc->sc_flags |= DMA_MAPLOADED; 323 324 /* No cache flush required for R3000 processors */ 325 326 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 327 count = esc->sc_dmamap->dm_segs[0].ds_len; 328 prime = (u_int32_t)paddr & 0x3f; 329 blocks = (prime + count + 63) >> 6; 330 331 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD); 332 333 /* Set transfer direction and disable DMA */ 334 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 335 336 /* Load DMA transfer address */ 337 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 338 paddr & ~0x3f); 339 340 /* Load number of blocks to DMA (1 block = 64 bytes) */ 341 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 342 343 /* If non block-aligned transfer prime FIFO manually */ 344 if (prime) { 345 /* Enable DMA to prime the FIFO buffer */ 346 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 347 RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE); 348 349 if (esc->sc_flags & DMA_PULLUP) { 350 /* Read from NCR 53c94 controller*/ 351 u_int16_t *p; 352 353 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 354 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 355 RAMBO_FIFO, p, prime>>1); 356 } else 357 /* Write to NCR 53C94 controller */ 358 while (prime > 0) { 359 (void)bus_space_read_2(esc->sc_bst, 360 esc->dm_bsh, 361 RAMBO_FIFO); 362 prime -= 2; 363 } 364 /* Leave DMA disabled while we setup NCR controller */ 365 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 366 esc->dm_mode); 367 } 368 369 esc->dm_curseg = 0; 370 esc->dm_mode |= RB_DMA_ENABLE; 371 if (esc->sc_dmamap->dm_nsegs > 1) 372 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 373 374 return 0; 375 } 376 377 static void 378 asc_dma_go(struct ncr53c9x_softc *sc) 379 { 380 struct asc_softc *esc = (struct asc_softc *)sc; 381 382 /* Start DMA */ 383 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 384 385 esc->sc_flags |= DMA_ACTIVE; 386 } 387 388 static int 389 asc_dma_intr(struct ncr53c9x_softc *sc) 390 { 391 struct asc_softc *esc = (struct asc_softc *)sc; 392 393 size_t resid, len; 394 int trans; 395 u_int32_t status; 396 u_int tcl, tcm; 397 398 #ifdef DIAGNOSTIC 399 if (!(esc->sc_flags & DMA_ACTIVE)) { 400 dma_status(sc); 401 panic("DMA not active"); 402 } 403 #endif 404 405 resid = 0; 406 if (!(esc->sc_flags & DMA_PULLUP) && 407 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 408 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 409 DELAY(10); 410 } 411 412 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 413 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 414 415 if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 416 NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 417 return 0; 418 } 419 420 trans = esc->sc_dmasize - resid; 421 if (trans < 0) { /* transferred < 0 ? */ 422 printf("asc_intr: xfer (%d) > req (%d)\n", 423 trans, esc->sc_dmasize); 424 trans = esc->sc_dmasize; 425 } 426 427 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 428 tcl, tcm, trans, resid)); 429 430 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 431 432 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 433 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 434 paddr_t ptr; 435 u_int16_t *p; 436 437 resid = status & 0x1f; 438 439 /* take the address of block to fixed up */ 440 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 441 RAMBO_CADDR); 442 /* find the starting address of fractional data */ 443 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 444 445 /* duplicate trailing data to FIFO for force flush */ 446 len = RB_BLK_CNT - resid; 447 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 448 RAMBO_FIFO, p, len); 449 check_fifo(esc); 450 } else { /* SCSI Write */ 451 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 452 RAMBO_MODE, 0); 453 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 454 RAMBO_MODE, RB_CLRFIFO); 455 } 456 } 457 458 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 459 460 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 461 462 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 463 0, esc->sc_dmasize, 464 (esc->sc_flags & DMA_PULLUP) 465 ? BUS_DMASYNC_POSTREAD 466 : BUS_DMASYNC_POSTWRITE); 467 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 468 469 *esc->sc_dmaaddr += trans; 470 *esc->sc_dmalen -= trans; 471 472 esc->sc_flags = DMA_IDLE; 473 474 return 0; 475 } 476 477 478 static void 479 asc_dma_stop(struct ncr53c9x_softc *sc) 480 { 481 struct asc_softc *esc = (struct asc_softc *)sc; 482 483 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 484 if (esc->sc_flags & DMA_MAPLOADED) 485 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 486 esc->sc_flags = DMA_IDLE; 487 } 488 489 static int 490 asc_dma_isactive(struct ncr53c9x_softc *sc) 491 { 492 struct asc_softc *esc = (struct asc_softc *)sc; 493 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 494 } 495 496 static void 497 rambo_dma_chain(struct asc_softc *esc) 498 { 499 int seg; 500 size_t count, blocks; 501 paddr_t paddr; 502 503 seg = ++esc->dm_curseg; 504 505 #ifdef DIAGNOSTIC 506 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 507 panic("Unexpected DMA chaining intr"); 508 509 /* Interrupt can only occur at terminal count, but double check */ 510 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 511 dma_status((void *)esc); 512 panic("rambo blkcnt != 0"); 513 } 514 #endif 515 516 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 517 count = esc->sc_dmamap->dm_segs[seg].ds_len; 518 blocks = (count + 63) >> 6; 519 520 /* Disable DMA interrupt if last segment */ 521 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 522 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 523 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 524 } 525 526 /* Load transfer address for next DMA chain */ 527 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 528 529 /* DMA restarts when we enter a new block count */ 530 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 531 } 532 533 static int 534 asc_intr(void *arg) 535 { 536 register u_int32_t dma_stat; 537 struct asc_softc *esc = arg; 538 struct ncr53c9x_softc *sc = arg; 539 540 esc->sc_intrcnt.ev_count++; 541 542 /* Check for RAMBO DMA Interrupt */ 543 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 544 if (dma_stat & RB_INTR_PEND) { 545 rambo_dma_chain(esc); 546 } 547 /* Check for NCR 53c94 interrupt */ 548 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 549 ncr53c9x_intr(sc); 550 } 551 return 0; 552 } 553
Indexes created Thu Oct 02 01:09:59 GMT 2025