asc.c revision 1.8
1 /* $NetBSD: asc.c,v 1.8 2001/03/30 07:49:07 wdk Exp $ */ 2 /*- 3 * Copyright (c) 2000 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Wayne Knowles 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/buf.h> 45 #include <sys/malloc.h> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsiconf.h> 50 #include <dev/scsipi/scsi_message.h> 51 52 #include <machine/cpu.h> 53 #include <machine/autoconf.h> 54 #include <machine/mainboard.h> 55 #include <machine/bus.h> 56 57 #include <mipsco/obio/rambo.h> 58 59 #include <dev/ic/ncr53c9xreg.h> 60 #include <dev/ic/ncr53c9xvar.h> 61 62 struct asc_softc { 63 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 64 struct evcnt sc_intrcnt; /* Interrupt counter */ 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; /* NCR 53c94 registers */ 67 bus_space_handle_t dm_bsh; /* RAMBO registers */ 68 bus_dma_tag_t sc_dmat; 69 bus_dmamap_t sc_dmamap; 70 caddr_t *sc_dmaaddr; 71 size_t *sc_dmalen; 72 size_t sc_dmasize; 73 int sc_flags; 74 #define DMA_IDLE 0x0 75 #define DMA_PULLUP 0x1 76 #define DMA_ACTIVE 0x2 77 #define DMA_MAPLOADED 0x4 78 u_int32_t dm_mode; 79 int dm_curseg; 80 }; 81 82 static int ascmatch (struct device *, struct cfdata *, void *); 83 static void ascattach (struct device *, struct device *, void *); 84 85 struct cfattach asc_ca = { 86 sizeof(struct asc_softc), ascmatch, ascattach 87 }; 88 89 /* 90 * Functions and the switch for the MI code. 91 */ 92 static u_char asc_read_reg (struct ncr53c9x_softc *, int); 93 static void asc_write_reg (struct ncr53c9x_softc *, int, u_char); 94 static int asc_dma_isintr (struct ncr53c9x_softc *); 95 static void asc_dma_reset (struct ncr53c9x_softc *); 96 static int asc_dma_intr (struct ncr53c9x_softc *); 97 static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *, 98 size_t *, int, size_t *); 99 static void asc_dma_go (struct ncr53c9x_softc *); 100 static void asc_dma_stop (struct ncr53c9x_softc *); 101 static int asc_dma_isactive (struct ncr53c9x_softc *); 102 103 static struct ncr53c9x_glue asc_glue = { 104 asc_read_reg, 105 asc_write_reg, 106 asc_dma_isintr, 107 asc_dma_reset, 108 asc_dma_intr, 109 asc_dma_setup, 110 asc_dma_go, 111 asc_dma_stop, 112 asc_dma_isactive, 113 NULL, /* gl_clear_latched_intr */ 114 }; 115 116 static int asc_intr (void *); 117 118 #define MAX_SCSI_XFER (64*1024) 119 #define MAX_DMA_SZ MAX_SCSI_XFER 120 #define DMA_SEGS (MAX_DMA_SZ/NBPG) 121 122 static int 123 ascmatch(struct device *parent, struct cfdata *cf, void *aux) 124 { 125 return 1; 126 } 127 128 static void 129 ascattach(struct device *parent, struct device *self, void *aux) 130 { 131 struct confargs *ca = aux; 132 struct asc_softc *esc = (void *)self; 133 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 134 135 /* 136 * Set up glue for MI code early; we use some of it here. 137 */ 138 sc->sc_glue = &asc_glue; 139 140 esc->sc_bst = ca->ca_bustag; 141 esc->sc_dmat = ca->ca_dmatag; 142 143 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 144 16*4, /* sizeof (ncr53c9xreg) */ 145 BUS_SPACE_MAP_LINEAR, 146 &esc->sc_bsh) != 0) { 147 printf(": cannot map registers\n"); 148 return; 149 } 150 151 if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch), 152 BUS_SPACE_MAP_LINEAR, 153 &esc->dm_bsh) != 0) { 154 printf(": cannot map dma registers\n"); 155 return; 156 } 157 158 if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ, 159 DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY, 160 BUS_DMA_WAITOK, 161 &esc->sc_dmamap) != 0) { 162 printf(": failed to create dmamap\n"); 163 return; 164 } 165 166 evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL, 167 self->dv_xname, "intr"); 168 169 esc->sc_flags = DMA_IDLE; 170 asc_dma_reset(sc); 171 172 /* Other settings */ 173 sc->sc_id = 7; 174 sc->sc_freq = 24; /* 24 MHz clock */ 175 176 /* 177 * Setup for genuine NCR 53C94 SCSI Controller 178 */ 179 180 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 181 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 182 sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI; 183 sc->sc_rev = NCR_VARIANT_NCR53C94; 184 185 sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4; 186 sc->sc_maxxfer = MAX_SCSI_XFER; 187 188 #ifdef OLDNCR 189 if (!NCR_READ_REG(sc, NCR_CFG3)) { 190 printf(" [old revision]"); 191 sc->sc_cfg2 = 0; 192 sc->sc_cfg3 = 0; 193 sc->sc_minsync = 0; 194 } 195 #endif 196 197 ncr53c9x_attach(sc, NULL, NULL); 198 199 bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc); 200 } 201 202 /* 203 * Glue functions. 204 */ 205 206 static u_char 207 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 208 { 209 struct asc_softc *esc = (struct asc_softc *)sc; 210 211 return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3); 212 } 213 214 static void 215 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 216 { 217 struct asc_softc *esc = (struct asc_softc *)sc; 218 219 bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val); 220 } 221 222 static void 223 dma_status(struct ncr53c9x_softc *sc) 224 { 225 struct asc_softc *esc = (struct asc_softc *)sc; 226 int count; 227 int stat; 228 void *addr; 229 u_int32_t tc; 230 231 tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL); 232 count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT); 233 stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 234 addr = (void *) 235 bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR); 236 237 printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x " 238 "ncr_stat=0x%02x ncr_fifo=0x%02x\n", 239 count, addr, stat, tc, 240 asc_read_reg(sc, NCR_STAT), 241 asc_read_reg(sc, NCR_FFLAG)); 242 } 243 244 static __inline void 245 check_fifo(struct asc_softc *esc) 246 { 247 register int i=100; 248 249 while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh, 250 RAMBO_MODE) & RB_FIFO_EMPTY)) { 251 DELAY(1); i--; 252 } 253 254 if (!i) { 255 dma_status((void *)esc); 256 panic("fifo didn't flush"); 257 } 258 } 259 260 static int 261 asc_dma_isintr(struct ncr53c9x_softc *sc) 262 { 263 return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT; 264 } 265 266 static void 267 asc_dma_reset(struct ncr53c9x_softc *sc) 268 { 269 struct asc_softc *esc = (struct asc_softc *)sc; 270 271 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 272 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 273 RB_CLRFIFO|RB_CLRERROR); 274 DELAY(10); 275 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 276 277 if (esc->sc_flags & DMA_MAPLOADED) 278 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 279 280 esc->sc_flags = DMA_IDLE; 281 } 282 283 /* 284 * Setup a DMA transfer 285 */ 286 287 static int 288 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 289 int datain, size_t *dmasize) 290 { 291 struct asc_softc *esc = (struct asc_softc *)sc; 292 paddr_t paddr; 293 size_t count, blocks; 294 int prime, err; 295 296 #ifdef DIAGNOSTIC 297 if (esc->sc_flags & DMA_ACTIVE) { 298 dma_status(sc); 299 panic("DMA active"); 300 } 301 #endif 302 303 esc->sc_dmaaddr = addr; 304 esc->sc_dmalen = len; 305 esc->sc_dmasize = *dmasize; 306 esc->sc_flags = datain ? DMA_PULLUP : 0; 307 308 NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n", 309 *addr, *len, datain, esc->sc_dmasize)); 310 311 if (esc->sc_dmasize == 0) 312 return 0; 313 314 /* have dmamap for the transfering addresses */ 315 if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap, 316 *esc->sc_dmaaddr, esc->sc_dmasize, 317 NULL /* kernel address */, 318 BUS_DMA_NOWAIT)) != 0) 319 panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err); 320 321 esc->sc_flags |= DMA_MAPLOADED; 322 323 /* No cache flush required for R3000 processors */ 324 325 paddr = esc->sc_dmamap->dm_segs[0].ds_addr; 326 count = esc->sc_dmamap->dm_segs[0].ds_len; 327 prime = (u_int32_t)paddr & 0x3f; 328 blocks = (prime + count + 63) >> 6; 329 330 esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD); 331 332 /* Set transfer direction and disable DMA */ 333 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 334 335 /* Load DMA transfer address */ 336 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, 337 paddr & ~0x3f); 338 339 /* Load number of blocks to DMA (1 block = 64 bytes) */ 340 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 341 342 /* If non block-aligned transfer prime FIFO manually */ 343 if (prime) { 344 /* Enable DMA to prime the FIFO buffer */ 345 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 346 RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE); 347 348 if (esc->sc_flags & DMA_PULLUP) { 349 /* Read from NCR 53c94 controller*/ 350 u_int16_t *p; 351 352 p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f); 353 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 354 RAMBO_FIFO, p, prime>>1); 355 } else 356 /* Write to NCR 53C94 controller */ 357 while (prime > 0) { 358 (void)bus_space_read_2(esc->sc_bst, 359 esc->dm_bsh, 360 RAMBO_FIFO); 361 prime -= 2; 362 } 363 /* Leave DMA disabled while we setup NCR controller */ 364 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 365 esc->dm_mode); 366 } 367 368 esc->dm_curseg = 0; 369 esc->dm_mode |= RB_DMA_ENABLE; 370 if (esc->sc_dmamap->dm_nsegs > 1) 371 esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */ 372 373 return 0; 374 } 375 376 static void 377 asc_dma_go(struct ncr53c9x_softc *sc) 378 { 379 struct asc_softc *esc = (struct asc_softc *)sc; 380 381 /* Start DMA */ 382 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode); 383 384 esc->sc_flags |= DMA_ACTIVE; 385 } 386 387 static int 388 asc_dma_intr(struct ncr53c9x_softc *sc) 389 { 390 struct asc_softc *esc = (struct asc_softc *)sc; 391 392 size_t resid, len; 393 int trans; 394 u_int32_t status; 395 u_int tcl, tcm; 396 397 #ifdef DIAGNOSTIC 398 if (!(esc->sc_flags & DMA_ACTIVE)) { 399 dma_status(sc); 400 panic("DMA not active"); 401 } 402 #endif 403 404 resid = 0; 405 if (!(esc->sc_flags & DMA_PULLUP) && 406 (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 407 NCR_DMA(("asc_intr: empty FIFO of %d ", resid)); 408 DELAY(10); 409 } 410 411 resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) + 412 ((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8); 413 414 if (esc->sc_dmasize == 0) { /* Transfer pad operation */ 415 NCR_DMA(("asc_intr: discard %d bytes\n", resid)); 416 return 0; 417 } 418 419 trans = esc->sc_dmasize - resid; 420 if (trans < 0) { /* transferred < 0 ? */ 421 printf("asc_intr: xfer (%d) > req (%d)\n", 422 trans, esc->sc_dmasize); 423 trans = esc->sc_dmasize; 424 } 425 426 NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n", 427 tcl, tcm, trans, resid)); 428 429 status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 430 431 if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */ 432 if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */ 433 paddr_t ptr; 434 u_int16_t *p; 435 436 resid = status & 0x1f; 437 438 /* take the address of block to fixed up */ 439 ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh, 440 RAMBO_CADDR); 441 /* find the starting address of fractional data */ 442 p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1)); 443 444 /* duplicate trailing data to FIFO for force flush */ 445 len = RB_BLK_CNT - resid; 446 bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh, 447 RAMBO_FIFO, p, len); 448 check_fifo(esc); 449 } else { /* SCSI Write */ 450 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 451 RAMBO_MODE, 0); 452 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 453 RAMBO_MODE, RB_CLRFIFO); 454 } 455 } 456 457 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0); 458 459 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 460 461 bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 462 0, esc->sc_dmasize, 463 (esc->sc_flags & DMA_PULLUP) 464 ? BUS_DMASYNC_POSTREAD 465 : BUS_DMASYNC_POSTWRITE); 466 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 467 468 *esc->sc_dmaaddr += trans; 469 *esc->sc_dmalen -= trans; 470 471 esc->sc_flags = DMA_IDLE; 472 473 return 0; 474 } 475 476 477 static void 478 asc_dma_stop(struct ncr53c9x_softc *sc) 479 { 480 struct asc_softc *esc = (struct asc_softc *)sc; 481 482 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0); 483 if (esc->sc_flags & DMA_MAPLOADED) 484 bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap); 485 esc->sc_flags = DMA_IDLE; 486 } 487 488 static int 489 asc_dma_isactive(struct ncr53c9x_softc *sc) 490 { 491 struct asc_softc *esc = (struct asc_softc *)sc; 492 return (esc->sc_flags & DMA_ACTIVE)? 1 : 0; 493 } 494 495 static void 496 rambo_dma_chain(struct asc_softc *esc) 497 { 498 int seg; 499 size_t count, blocks; 500 paddr_t paddr; 501 502 seg = ++esc->dm_curseg; 503 504 #ifdef DIAGNOSTIC 505 if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs) 506 panic("Unexpected DMA chaining intr"); 507 508 /* Interrupt can only occur at terminal count, but double check */ 509 if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) { 510 dma_status((void *)esc); 511 panic("rambo blkcnt != 0"); 512 } 513 #endif 514 515 paddr = esc->sc_dmamap->dm_segs[seg].ds_addr; 516 count = esc->sc_dmamap->dm_segs[seg].ds_len; 517 blocks = (count + 63) >> 6; 518 519 /* Disable DMA interrupt if last segment */ 520 if (seg+1 > esc->sc_dmamap->dm_nsegs) { 521 bus_space_write_4(esc->sc_bst, esc->dm_bsh, 522 RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE); 523 } 524 525 /* Load transfer address for next DMA chain */ 526 bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr); 527 528 /* DMA restarts when we enter a new block count */ 529 bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks); 530 } 531 532 static int 533 asc_intr(void *arg) 534 { 535 register u_int32_t dma_stat; 536 struct asc_softc *esc = arg; 537 struct ncr53c9x_softc *sc = arg; 538 539 esc->sc_intrcnt.ev_count++; 540 541 /* Check for RAMBO DMA Interrupt */ 542 dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE); 543 if (dma_stat & RB_INTR_PEND) { 544 rambo_dma_chain(esc); 545 } 546 /* Check for NCR 53c94 interrupt */ 547 if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) { 548 ncr53c9x_intr(sc); 549 } 550 return 0; 551 } 552
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