zs.c revision 1.1
1 /* $NetBSD: zs.c,v 1.1 2000/08/12 22:58:59 wdk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <machine/cpu.h> 61 #include <machine/mainboard.h> 62 #include <machine/autoconf.h> 63 #include <machine/z8530var.h> 64 65 #include <dev/cons.h> 66 #include <dev/ic/z8530reg.h> 67 68 #include "zsc.h" /* NZSC */ 69 #define NZS NZSC 70 71 /* Make life easier for the initialized arrays here. */ 72 #if NZS < 2 73 #undef NZS 74 #define NZS 2 75 #endif 76 77 extern void Debugger __P((void)); 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 int zs_major = 1; 86 87 /* 88 * 10MHz PCLK 89 */ 90 #define PCLK 10000000 /* PCLK pin input clock rate */ 91 92 /* 93 * Define interrupt levels. 94 */ 95 #define ZSHARD_PRI 64 96 97 #define ZS_DELAY() delay(2); 98 99 /* The layout of this is hardware-dependent (padding, order). */ 100 struct zschan { 101 u_char pad1[3]; 102 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 103 u_char pad2[3]; 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 /* Flags from cninit() */ 113 static int zs_hwflags[NZS][2]; 114 115 /* Default speed for all channels */ 116 static int zs_defspeed = 9600; 117 118 static u_char zs_init_reg[16] = { 119 0, /* 0: CMD (reset, etc.) */ 120 0, /* 1: No interrupts yet. */ 121 ZSHARD_PRI, /* IVECT */ 122 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 123 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 124 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 125 0, /* 6: TXSYNC/SYNCLO */ 126 0, /* 7: RXSYNC/SYNCHI */ 127 0, /* 8: alias for data port */ 128 ZSWR9_MASTER_IE, 129 0, /*10: Misc. TX/RX control bits */ 130 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 131 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 132 0, /*13: BAUDHI (default=9600) */ 133 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 134 ZSWR15_BREAK_IE, 135 }; 136 137 138 struct zschan * 139 zs_get_chan_addr(zs_unit, channel) 140 int zs_unit, channel; 141 { 142 struct zsdevice *addr; 143 struct zschan *zc; 144 145 if (zs_unit >= NZS) 146 return NULL; 147 148 addr = (struct zsdevice *) ZS0_ADDR; 149 150 if (channel == 0) { 151 zc = &addr->zs_chan_a; 152 } else { 153 zc = &addr->zs_chan_b; 154 } 155 return (zc); 156 } 157 158 159 /**************************************************************** 160 * Autoconfig 161 ****************************************************************/ 162 163 /* Definition of the driver for autoconfig. */ 164 static int zs_match __P((struct device *, struct cfdata *, void *)); 165 static void zs_attach __P((struct device *, struct device *, void *)); 166 static int zs_print __P((void *, const char *name)); 167 168 struct cfattach zsc_ca = { 169 sizeof(struct zsc_softc), zs_match, zs_attach 170 }; 171 172 extern struct cfdriver zsc_cd; 173 174 static void zshard __P((void *)); 175 static void zssoft __P((void *)); 176 static int zs_get_speed __P((struct zs_chanstate *)); 177 178 179 /* 180 * Is the zs chip present? 181 */ 182 static int 183 zs_match(parent, cf, aux) 184 struct device *parent; 185 struct cfdata *cf; 186 void *aux; 187 { 188 struct confargs *ca = aux; 189 void *va; 190 191 if (strcmp(ca->ca_name, "zsc")) 192 return 0; 193 194 va = (void *)cf->cf_addr; 195 196 /* This returns -1 on a fault (bus error). */ 197 if (badaddr(va, 1)) 198 return 0; 199 return 1; 200 } 201 202 /* 203 * Attach a found zs. 204 * 205 * Match slave number to zs unit number, so that misconfiguration will 206 * not set up the keyboard as ttya, etc. 207 */ 208 static void 209 zs_attach(parent, self, aux) 210 struct device *parent; 211 struct device *self; 212 void *aux; 213 { 214 struct zsc_softc *zsc = (void *) self; 215 struct confargs *ca = aux; 216 struct zsc_attach_args zsc_args; 217 struct zsdevice *zsd; 218 struct zschan *zc; 219 struct zs_chanstate *cs; 220 int s, zs_unit, channel; 221 static int didintr; 222 223 zsc->zsc_bustag = ca->ca_bustag; 224 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 225 sizeof(struct zsdevice), 226 BUS_SPACE_MAP_LINEAR, 227 &zsc->zsc_base) != 0) { 228 printf(": cannot map registers\n"); 229 return; 230 } 231 zsd = (struct zsdevice *)zsc->zsc_base; 232 233 zs_unit = zsc->zsc_dev.dv_unit; 234 printf("\n"); 235 236 /* 237 * Initialize software state for each channel. 238 */ 239 for (channel = 0; channel < 2; channel++) { 240 zsc_args.channel = channel; 241 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 242 cs = &zsc->zsc_cs_store[channel]; 243 zsc->zsc_cs[channel] = cs; 244 245 cs->cs_channel = channel; 246 cs->cs_private = NULL; 247 cs->cs_ops = &zsops_null; 248 cs->cs_brg_clk = PCLK / 16; 249 250 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 251 252 cs->cs_reg_csr = &zc->zc_csr; 253 cs->cs_reg_data = &zc->zc_data; 254 255 bcopy(zs_init_reg, cs->cs_creg, 16); 256 bcopy(zs_init_reg, cs->cs_preg, 16); 257 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 zs_write_reg(cs, 9, 0); 277 } 278 /* 279 * Look for a child driver for this channel. 280 * The child attach will setup the hardware. 281 */ 282 if (!config_found(self, (void *)&zsc_args, zs_print)) { 283 /* No sub-driver. Just reset it. */ 284 u_char reset = (channel == 0) ? 285 ZSWR9_A_RESET : ZSWR9_B_RESET; 286 287 s = splhigh(); 288 zs_write_reg(cs, 9, reset); 289 splx(s); 290 } 291 } 292 293 /* 294 * Now safe to install interrupt handlers. Note the arguments 295 * to the interrupt handlers aren't used. Note, we only do this 296 * once since both SCCs interrupt at the same level and vector. 297 */ 298 if (!didintr) { 299 didintr = 1; 300 #if 0 301 isr_add_autovect(zssoft, NULL, ZSSOFT_PRI); 302 isr_add_autovect(zshard, NULL, ca->ca_intpri); 303 #endif 304 } 305 306 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 307 self->dv_xname, "intr"); 308 309 /* 310 * Set the master interrupt enable and interrupt vector. 311 * (common to both channels, do it on A) 312 */ 313 cs = zsc->zsc_cs[0]; 314 s = splhigh(); 315 /* interrupt vector */ 316 zs_write_reg(cs, 2, zs_init_reg[2]); 317 /* master interrupt control (enable) */ 318 zs_write_reg(cs, 9, zs_init_reg[9]); 319 splx(s); 320 } 321 322 static int 323 zs_print(aux, name) 324 void *aux; 325 const char *name; 326 { 327 struct zsc_attach_args *args = aux; 328 329 if (name != NULL) 330 printf("%s: ", name); 331 332 if (args->channel != -1) 333 printf(" channel %d", args->channel); 334 335 return UNCONF; 336 } 337 338 static volatile int zssoftpending; 339 340 /* 341 * Our ZS chips all share a common, autovectored interrupt, 342 * so we have to look at all of them on each interrupt. 343 */ 344 static void 345 zshard(arg) 346 void *arg; 347 { 348 register struct zsc_softc *zsc; 349 register int unit, rval, softreq; 350 351 rval = softreq = 0; 352 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 353 zsc = zsc_cd.cd_devs[unit]; 354 if (zsc == NULL) 355 continue; 356 rval |= zsc_intr_hard(zsc); 357 softreq |= zsc->zsc_cs[0]->cs_softreq; 358 softreq |= zsc->zsc_cs[1]->cs_softreq; 359 zsc->zs_intrcnt.ev_count++; 360 } 361 362 /* We are at splzs here, so no need to lock. */ 363 if (softreq && (zssoftpending == 0)) { 364 zssoftpending = 1; 365 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 366 } 367 return; 368 } 369 370 /* 371 * Similar scheme as for zshard (look at all of them) 372 */ 373 static void 374 zssoft(arg) 375 void *arg; 376 { 377 register struct zsc_softc *zsc; 378 register int s, unit; 379 380 /* This is not the only ISR on this IPL. */ 381 if (zssoftpending == 0) 382 return; 383 384 /* 385 * The soft intr. bit will be set by zshard only if 386 * the variable zssoftpending is zero. The order of 387 * these next two statements prevents our clearing 388 * the soft intr bit just after zshard has set it. 389 */ 390 /*isr_soft_clear(ZSSOFT_PRI);*/ 391 /*zssoftpending = 0;*/ 392 393 /* Make sure we call the tty layer at spltty. */ 394 s = spltty(); 395 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 396 zsc = zsc_cd.cd_devs[unit]; 397 if (zsc == NULL) 398 continue; 399 (void) zsc_intr_soft(zsc); 400 } 401 splx(s); 402 zssoftpending = 0; 403 return; 404 } 405 406 407 /* 408 * Compute the current baud rate given a ZS channel. 409 */ 410 static int 411 zs_get_speed(cs) 412 struct zs_chanstate *cs; 413 { 414 int tconst; 415 416 tconst = zs_read_reg(cs, 12); 417 tconst |= zs_read_reg(cs, 13) << 8; 418 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 419 } 420 421 /* 422 * MD functions for setting the baud rate and control modes. 423 */ 424 int 425 zs_set_speed(cs, bps) 426 struct zs_chanstate *cs; 427 int bps; /* bits per second */ 428 { 429 int tconst, real_bps; 430 431 if (bps == 0) 432 return (0); 433 434 #ifdef DIAGNOSTIC 435 if (cs->cs_brg_clk == 0) 436 panic("zs_set_speed"); 437 #endif 438 439 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 440 if (tconst < 0) 441 return (EINVAL); 442 443 /* Convert back to make sure we can do it. */ 444 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 445 446 /* XXX - Allow some tolerance here? */ 447 #if 0 448 if (real_bps != bps) 449 return (EINVAL); 450 #endif 451 452 cs->cs_preg[12] = tconst; 453 cs->cs_preg[13] = tconst >> 8; 454 455 /* Caller will stuff the pending registers. */ 456 return (0); 457 } 458 459 int 460 zs_set_modes(cs, cflag) 461 struct zs_chanstate *cs; 462 int cflag; /* bits per second */ 463 { 464 int s; 465 466 /* 467 * Output hardware flow control on the chip is horrendous: 468 * if carrier detect drops, the receiver is disabled, and if 469 * CTS drops, the transmitter is stoped IN MID CHARACTER! 470 * Therefore, NEVER set the HFC bit, and instead use the 471 * status interrupt to detect CTS changes. 472 */ 473 s = splzs(); 474 cs->cs_rr0_pps = 0; 475 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 476 cs->cs_rr0_dcd = 0; 477 if ((cflag & MDMBUF) == 0) 478 cs->cs_rr0_pps = ZSRR0_DCD; 479 } else 480 cs->cs_rr0_dcd = ZSRR0_DCD; 481 if ((cflag & CRTSCTS) != 0) { 482 cs->cs_wr5_dtr = ZSWR5_DTR; 483 cs->cs_wr5_rts = ZSWR5_RTS; 484 cs->cs_rr0_cts = ZSRR0_CTS; 485 } else if ((cflag & MDMBUF) != 0) { 486 cs->cs_wr5_dtr = 0; 487 cs->cs_wr5_rts = ZSWR5_DTR; 488 cs->cs_rr0_cts = ZSRR0_DCD; 489 } else { 490 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 491 cs->cs_wr5_rts = 0; 492 cs->cs_rr0_cts = 0; 493 } 494 splx(s); 495 496 /* Caller will stuff the pending registers. */ 497 return (0); 498 } 499 500 501 /* 502 * Read or write the chip with suitable delays. 503 */ 504 505 u_char 506 zs_read_reg(cs, reg) 507 struct zs_chanstate *cs; 508 u_char reg; 509 { 510 u_char val; 511 512 *cs->cs_reg_csr = reg; 513 ZS_DELAY(); 514 val = *cs->cs_reg_csr; 515 ZS_DELAY(); 516 return val; 517 } 518 519 void 520 zs_write_reg(cs, reg, val) 521 struct zs_chanstate *cs; 522 u_char reg, val; 523 { 524 *cs->cs_reg_csr = reg; 525 ZS_DELAY(); 526 *cs->cs_reg_csr = val; 527 ZS_DELAY(); 528 } 529 530 u_char zs_read_csr(cs) 531 struct zs_chanstate *cs; 532 { 533 register u_char val; 534 535 val = *cs->cs_reg_csr; 536 ZS_DELAY(); 537 return val; 538 } 539 540 void zs_write_csr(cs, val) 541 struct zs_chanstate *cs; 542 u_char val; 543 { 544 *cs->cs_reg_csr = val; 545 ZS_DELAY(); 546 } 547 548 u_char zs_read_data(cs) 549 struct zs_chanstate *cs; 550 { 551 register u_char val; 552 553 val = *cs->cs_reg_data; 554 ZS_DELAY(); 555 return val; 556 } 557 558 void zs_write_data(cs, val) 559 struct zs_chanstate *cs; 560 u_char val; 561 { 562 *cs->cs_reg_data = val; 563 ZS_DELAY(); 564 } 565 566 void 567 zs_abort(cs) 568 struct zs_chanstate *cs; 569 { 570 #ifdef DDB 571 Debugger(); 572 #endif 573 } 574 575 /* 576 * Polled input char. 577 */ 578 int 579 zs_getc(arg) 580 void *arg; 581 { 582 register volatile struct zschan *zc = arg; 583 register int s, c, rr0; 584 585 s = splhigh(); 586 /* Wait for a character to arrive. */ 587 do { 588 rr0 = zc->zc_csr; 589 ZS_DELAY(); 590 } while ((rr0 & ZSRR0_RX_READY) == 0); 591 592 c = zc->zc_data; 593 ZS_DELAY(); 594 splx(s); 595 596 /* 597 * This is used by the kd driver to read scan codes, 598 * so don't translate '\r' ==> '\n' here... 599 */ 600 return (c); 601 } 602 603 /* 604 * Polled output char. 605 */ 606 void 607 zs_putc(arg, c) 608 void *arg; 609 int c; 610 { 611 register volatile struct zschan *zc = arg; 612 register int s, rr0; 613 614 s = splhigh(); 615 /* Wait for transmitter to become ready. */ 616 do { 617 rr0 = zc->zc_csr; 618 ZS_DELAY(); 619 } while ((rr0 & ZSRR0_TX_READY) == 0); 620 621 zc->zc_data = c; 622 ZS_DELAY(); 623 splx(s); 624 } 625 626 /*****************************************************************/ 627 628 static void zscnprobe __P((struct consdev *)); 629 static void zscninit __P((struct consdev *)); 630 static int zscngetc __P((dev_t)); 631 static void zscnputc __P((dev_t, int)); 632 static void zscnpollc __P((dev_t, int)); 633 634 static int cons_port = 1; 635 636 struct consdev consdev_zs = { 637 zscnprobe, 638 zscninit, 639 zscngetc, 640 zscnputc, 641 zscnpollc 642 }; 643 644 void 645 zscnprobe(cn) 646 struct consdev *cn; 647 { 648 } 649 650 void 651 zscninit(cn) 652 struct consdev *cn; 653 { 654 cn->cn_dev = makedev(zs_major, cons_port); 655 cn->cn_pri = CN_REMOTE; 656 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 657 } 658 659 int 660 zscngetc(dev) 661 dev_t dev; 662 { 663 struct zschan *zs; 664 665 zs = zs_get_chan_addr(0, cons_port); 666 return zs_getc(zs); 667 } 668 669 void 670 zscnputc(dev, c) 671 dev_t dev; 672 int c; 673 { 674 struct zschan *zs; 675 676 zs = zs_get_chan_addr(0, cons_port); 677 zs_putc(zs, c); 678 } 679 680 void 681 zscnpollc(dev, on) 682 dev_t dev; 683 int on; 684 { 685 } 686 687 /* 688 * ZS vector interrupt service routine. 689 */ 690 void 691 zs_intr() 692 { 693 int vec; 694 695 /* 696 * TODO: We can read the interrupt vector from the SCC 697 * registers. 698 */ 699 zshard((void *)vec); /* XXX vec is not used */ 700 } 701
Indexes created Tue Sep 30 11:09:46 GMT 2025