zs.c revision 1.2
1 /* $NetBSD: zs.c,v 1.2 2000/08/15 04:56:47 wdk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <machine/cpu.h> 61 #include <machine/mainboard.h> 62 #include <machine/autoconf.h> 63 #include <machine/z8530var.h> 64 65 #include <dev/cons.h> 66 #include <dev/ic/z8530reg.h> 67 68 #include "zsc.h" /* NZSC */ 69 #define NZS NZSC 70 71 /* Make life easier for the initialized arrays here. */ 72 #if NZS < 2 73 #undef NZS 74 #define NZS 2 75 #endif 76 77 extern void Debugger __P((void)); 78 79 /* 80 * Some warts needed by z8530tty.c - 81 * The default parity REALLY needs to be the same as the PROM uses, 82 * or you can not see messages done with printf during boot-up... 83 */ 84 int zs_def_cflag = (CREAD | CS8 | HUPCL); 85 int zs_major = 1; 86 87 /* 88 * 10MHz PCLK 89 */ 90 #define PCLK 10000000 /* PCLK pin input clock rate */ 91 92 /* 93 * Define interrupt levels. 94 */ 95 #define ZSHARD_PRI 64 96 97 #define ZS_DELAY() delay(2); 98 99 /* The layout of this is hardware-dependent (padding, order). */ 100 struct zschan { 101 u_char pad1[3]; 102 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 103 u_char pad2[3]; 104 volatile u_char zc_data; /* data */ 105 }; 106 struct zsdevice { 107 /* Yes, they are backwards. */ 108 struct zschan zs_chan_b; 109 struct zschan zs_chan_a; 110 }; 111 112 /* Flags from cninit() */ 113 static int zs_hwflags[NZS][2]; 114 115 /* Default speed for all channels */ 116 static int zs_defspeed = 9600; 117 118 static u_char zs_init_reg[16] = { 119 0, /* 0: CMD (reset, etc.) */ 120 0, /* 1: No interrupts yet. */ 121 ZSHARD_PRI, /* IVECT */ 122 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 123 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 124 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 125 0, /* 6: TXSYNC/SYNCLO */ 126 0, /* 7: RXSYNC/SYNCHI */ 127 0, /* 8: alias for data port */ 128 ZSWR9_MASTER_IE, 129 0, /*10: Misc. TX/RX control bits */ 130 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 131 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 132 0, /*13: BAUDHI (default=9600) */ 133 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 134 ZSWR15_BREAK_IE, 135 }; 136 137 138 struct zschan * 139 zs_get_chan_addr(zs_unit, channel) 140 int zs_unit, channel; 141 { 142 struct zsdevice *addr; 143 struct zschan *zc; 144 145 if (zs_unit >= NZS) 146 return NULL; 147 148 addr = (struct zsdevice *) ZS0_ADDR; 149 150 if (channel == 0) { 151 zc = &addr->zs_chan_a; 152 } else { 153 zc = &addr->zs_chan_b; 154 } 155 return (zc); 156 } 157 158 159 /**************************************************************** 160 * Autoconfig 161 ****************************************************************/ 162 163 /* Definition of the driver for autoconfig. */ 164 static int zs_match __P((struct device *, struct cfdata *, void *)); 165 static void zs_attach __P((struct device *, struct device *, void *)); 166 static int zs_print __P((void *, const char *name)); 167 168 struct cfattach zsc_ca = { 169 sizeof(struct zsc_softc), zs_match, zs_attach 170 }; 171 172 extern struct cfdriver zsc_cd; 173 174 static int zshard __P((void *)); 175 static void zssoft __P((void *)); 176 static int zs_get_speed __P((struct zs_chanstate *)); 177 178 179 /* 180 * Is the zs chip present? 181 */ 182 static int 183 zs_match(parent, cf, aux) 184 struct device *parent; 185 struct cfdata *cf; 186 void *aux; 187 { 188 struct confargs *ca = aux; 189 void *va; 190 191 if (strcmp(ca->ca_name, "zsc")) 192 return 0; 193 194 va = (void *)cf->cf_addr; 195 196 /* This returns -1 on a fault (bus error). */ 197 if (badaddr(va, 1)) 198 return 0; 199 return 1; 200 } 201 202 /* 203 * Attach a found zs. 204 * 205 * Match slave number to zs unit number, so that misconfiguration will 206 * not set up the keyboard as ttya, etc. 207 */ 208 static void 209 zs_attach(parent, self, aux) 210 struct device *parent; 211 struct device *self; 212 void *aux; 213 { 214 struct zsc_softc *zsc = (void *) self; 215 struct confargs *ca = aux; 216 struct zsc_attach_args zsc_args; 217 struct zsdevice *zsd; 218 struct zschan *zc; 219 struct zs_chanstate *cs; 220 int s, zs_unit, channel; 221 222 zsc->zsc_bustag = ca->ca_bustag; 223 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 224 sizeof(struct zsdevice), 225 BUS_SPACE_MAP_LINEAR, 226 &zsc->zsc_base) != 0) { 227 printf(": cannot map registers\n"); 228 return; 229 } 230 zsd = (struct zsdevice *)zsc->zsc_base; 231 232 zs_unit = zsc->zsc_dev.dv_unit; 233 printf("\n"); 234 235 /* 236 * Initialize software state for each channel. 237 */ 238 for (channel = 0; channel < 2; channel++) { 239 zsc_args.channel = channel; 240 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 241 cs = &zsc->zsc_cs_store[channel]; 242 zsc->zsc_cs[channel] = cs; 243 244 cs->cs_channel = channel; 245 cs->cs_private = NULL; 246 cs->cs_ops = &zsops_null; 247 cs->cs_brg_clk = PCLK / 16; 248 249 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 250 251 cs->cs_reg_csr = &zc->zc_csr; 252 cs->cs_reg_data = &zc->zc_data; 253 254 bcopy(zs_init_reg, cs->cs_creg, 16); 255 bcopy(zs_init_reg, cs->cs_preg, 16); 256 257 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 258 cs->cs_defspeed = zs_get_speed(cs); 259 else 260 cs->cs_defspeed = zs_defspeed; 261 cs->cs_defcflag = zs_def_cflag; 262 263 /* Make these correspond to cs_defcflag (-crtscts) */ 264 cs->cs_rr0_dcd = ZSRR0_DCD; 265 cs->cs_rr0_cts = 0; 266 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 267 cs->cs_wr5_rts = 0; 268 269 /* 270 * Clear the master interrupt enable. 271 * The INTENA is common to both channels, 272 * so just do it on the A channel. 273 */ 274 if (channel == 0) { 275 zs_write_reg(cs, 9, 0); 276 } 277 /* 278 * Look for a child driver for this channel. 279 * The child attach will setup the hardware. 280 */ 281 if (!config_found(self, (void *)&zsc_args, zs_print)) { 282 /* No sub-driver. Just reset it. */ 283 u_char reset = (channel == 0) ? 284 ZSWR9_A_RESET : ZSWR9_B_RESET; 285 286 s = splhigh(); 287 zs_write_reg(cs, 9, reset); 288 splx(s); 289 } 290 } 291 292 /* bus_intr_establish(zssoft, NULL, ZSSOFT_PRI); */ 293 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 294 295 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 296 self->dv_xname, "intr"); 297 298 /* 299 * Set the master interrupt enable and interrupt vector. 300 * (common to both channels, do it on A) 301 */ 302 cs = zsc->zsc_cs[0]; 303 s = splhigh(); 304 /* interrupt vector */ 305 zs_write_reg(cs, 2, zs_init_reg[2]); 306 /* master interrupt control (enable) */ 307 zs_write_reg(cs, 9, zs_init_reg[9]); 308 splx(s); 309 } 310 311 static int 312 zs_print(aux, name) 313 void *aux; 314 const char *name; 315 { 316 struct zsc_attach_args *args = aux; 317 318 if (name != NULL) 319 printf("%s: ", name); 320 321 if (args->channel != -1) 322 printf(" channel %d", args->channel); 323 324 return UNCONF; 325 } 326 327 static volatile int zssoftpending; 328 329 /* 330 * Our ZS chips all share a common, autovectored interrupt, 331 * so we have to look at all of them on each interrupt. 332 */ 333 static int 334 zshard(arg) 335 void *arg; 336 { 337 register struct zsc_softc *zsc; 338 register int unit, rval, softreq; 339 340 rval = softreq = 0; 341 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 342 zsc = zsc_cd.cd_devs[unit]; 343 if (zsc == NULL) 344 continue; 345 rval |= zsc_intr_hard(zsc); 346 softreq |= zsc->zsc_cs[0]->cs_softreq; 347 softreq |= zsc->zsc_cs[1]->cs_softreq; 348 zsc->zs_intrcnt.ev_count++; 349 } 350 351 /* We are at splzs here, so no need to lock. */ 352 if (softreq && (zssoftpending == 0)) { 353 zssoftpending = 1; 354 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 355 } 356 return 0; 357 } 358 359 /* 360 * Similar scheme as for zshard (look at all of them) 361 */ 362 static void 363 zssoft(arg) 364 void *arg; 365 { 366 register struct zsc_softc *zsc; 367 register int s, unit; 368 369 /* This is not the only ISR on this IPL. */ 370 if (zssoftpending == 0) 371 return; 372 373 /* 374 * The soft intr. bit will be set by zshard only if 375 * the variable zssoftpending is zero. The order of 376 * these next two statements prevents our clearing 377 * the soft intr bit just after zshard has set it. 378 */ 379 /*isr_soft_clear(ZSSOFT_PRI);*/ 380 /*zssoftpending = 0;*/ 381 382 /* Make sure we call the tty layer at spltty. */ 383 s = spltty(); 384 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 385 zsc = zsc_cd.cd_devs[unit]; 386 if (zsc == NULL) 387 continue; 388 (void) zsc_intr_soft(zsc); 389 } 390 splx(s); 391 zssoftpending = 0; 392 return; 393 } 394 395 396 /* 397 * Compute the current baud rate given a ZS channel. 398 */ 399 static int 400 zs_get_speed(cs) 401 struct zs_chanstate *cs; 402 { 403 int tconst; 404 405 tconst = zs_read_reg(cs, 12); 406 tconst |= zs_read_reg(cs, 13) << 8; 407 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 408 } 409 410 /* 411 * MD functions for setting the baud rate and control modes. 412 */ 413 int 414 zs_set_speed(cs, bps) 415 struct zs_chanstate *cs; 416 int bps; /* bits per second */ 417 { 418 int tconst, real_bps; 419 420 if (bps == 0) 421 return (0); 422 423 #ifdef DIAGNOSTIC 424 if (cs->cs_brg_clk == 0) 425 panic("zs_set_speed"); 426 #endif 427 428 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 429 if (tconst < 0) 430 return (EINVAL); 431 432 /* Convert back to make sure we can do it. */ 433 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 434 435 /* XXX - Allow some tolerance here? */ 436 #if 0 437 if (real_bps != bps) 438 return (EINVAL); 439 #endif 440 441 cs->cs_preg[12] = tconst; 442 cs->cs_preg[13] = tconst >> 8; 443 444 /* Caller will stuff the pending registers. */ 445 return (0); 446 } 447 448 int 449 zs_set_modes(cs, cflag) 450 struct zs_chanstate *cs; 451 int cflag; /* bits per second */ 452 { 453 int s; 454 455 /* 456 * Output hardware flow control on the chip is horrendous: 457 * if carrier detect drops, the receiver is disabled, and if 458 * CTS drops, the transmitter is stoped IN MID CHARACTER! 459 * Therefore, NEVER set the HFC bit, and instead use the 460 * status interrupt to detect CTS changes. 461 */ 462 s = splzs(); 463 cs->cs_rr0_pps = 0; 464 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 465 cs->cs_rr0_dcd = 0; 466 if ((cflag & MDMBUF) == 0) 467 cs->cs_rr0_pps = ZSRR0_DCD; 468 } else 469 cs->cs_rr0_dcd = ZSRR0_DCD; 470 if ((cflag & CRTSCTS) != 0) { 471 cs->cs_wr5_dtr = ZSWR5_DTR; 472 cs->cs_wr5_rts = ZSWR5_RTS; 473 cs->cs_rr0_cts = ZSRR0_CTS; 474 } else if ((cflag & MDMBUF) != 0) { 475 cs->cs_wr5_dtr = 0; 476 cs->cs_wr5_rts = ZSWR5_DTR; 477 cs->cs_rr0_cts = ZSRR0_DCD; 478 } else { 479 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 480 cs->cs_wr5_rts = 0; 481 cs->cs_rr0_cts = 0; 482 } 483 splx(s); 484 485 /* Caller will stuff the pending registers. */ 486 return (0); 487 } 488 489 490 /* 491 * Read or write the chip with suitable delays. 492 */ 493 494 u_char 495 zs_read_reg(cs, reg) 496 struct zs_chanstate *cs; 497 u_char reg; 498 { 499 u_char val; 500 501 *cs->cs_reg_csr = reg; 502 ZS_DELAY(); 503 val = *cs->cs_reg_csr; 504 ZS_DELAY(); 505 return val; 506 } 507 508 void 509 zs_write_reg(cs, reg, val) 510 struct zs_chanstate *cs; 511 u_char reg, val; 512 { 513 *cs->cs_reg_csr = reg; 514 ZS_DELAY(); 515 *cs->cs_reg_csr = val; 516 ZS_DELAY(); 517 } 518 519 u_char zs_read_csr(cs) 520 struct zs_chanstate *cs; 521 { 522 register u_char val; 523 524 val = *cs->cs_reg_csr; 525 ZS_DELAY(); 526 return val; 527 } 528 529 void zs_write_csr(cs, val) 530 struct zs_chanstate *cs; 531 u_char val; 532 { 533 *cs->cs_reg_csr = val; 534 ZS_DELAY(); 535 } 536 537 u_char zs_read_data(cs) 538 struct zs_chanstate *cs; 539 { 540 register u_char val; 541 542 val = *cs->cs_reg_data; 543 ZS_DELAY(); 544 return val; 545 } 546 547 void zs_write_data(cs, val) 548 struct zs_chanstate *cs; 549 u_char val; 550 { 551 *cs->cs_reg_data = val; 552 ZS_DELAY(); 553 } 554 555 void 556 zs_abort(cs) 557 struct zs_chanstate *cs; 558 { 559 #ifdef DDB 560 Debugger(); 561 #endif 562 } 563 564 /* 565 * Polled input char. 566 */ 567 int 568 zs_getc(arg) 569 void *arg; 570 { 571 register volatile struct zschan *zc = arg; 572 register int s, c, rr0; 573 574 s = splhigh(); 575 /* Wait for a character to arrive. */ 576 do { 577 rr0 = zc->zc_csr; 578 ZS_DELAY(); 579 } while ((rr0 & ZSRR0_RX_READY) == 0); 580 581 c = zc->zc_data; 582 ZS_DELAY(); 583 splx(s); 584 585 /* 586 * This is used by the kd driver to read scan codes, 587 * so don't translate '\r' ==> '\n' here... 588 */ 589 return (c); 590 } 591 592 /* 593 * Polled output char. 594 */ 595 void 596 zs_putc(arg, c) 597 void *arg; 598 int c; 599 { 600 register volatile struct zschan *zc = arg; 601 register int s, rr0; 602 603 s = splhigh(); 604 /* Wait for transmitter to become ready. */ 605 do { 606 rr0 = zc->zc_csr; 607 ZS_DELAY(); 608 } while ((rr0 & ZSRR0_TX_READY) == 0); 609 610 zc->zc_data = c; 611 ZS_DELAY(); 612 splx(s); 613 } 614 615 /*****************************************************************/ 616 617 static void zscnprobe __P((struct consdev *)); 618 static void zscninit __P((struct consdev *)); 619 static int zscngetc __P((dev_t)); 620 static void zscnputc __P((dev_t, int)); 621 static void zscnpollc __P((dev_t, int)); 622 623 static int cons_port = 1; 624 625 struct consdev consdev_zs = { 626 zscnprobe, 627 zscninit, 628 zscngetc, 629 zscnputc, 630 zscnpollc 631 }; 632 633 void 634 zscnprobe(cn) 635 struct consdev *cn; 636 { 637 } 638 639 void 640 zscninit(cn) 641 struct consdev *cn; 642 { 643 cn->cn_dev = makedev(zs_major, cons_port); 644 cn->cn_pri = CN_REMOTE; 645 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 646 } 647 648 int 649 zscngetc(dev) 650 dev_t dev; 651 { 652 struct zschan *zs; 653 654 zs = zs_get_chan_addr(0, cons_port); 655 return zs_getc(zs); 656 } 657 658 void 659 zscnputc(dev, c) 660 dev_t dev; 661 int c; 662 { 663 struct zschan *zs; 664 665 zs = zs_get_chan_addr(0, cons_port); 666 zs_putc(zs, c); 667 } 668 669 void 670 zscnpollc(dev, on) 671 dev_t dev; 672 int on; 673 { 674 } 675
Indexes created Tue Sep 30 11:09:46 GMT 2025