zs.c revision 1.21
1 /* $NetBSD: zs.c,v 1.21 2007/11/26 23:29:36 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include <sys/cdefs.h> 47 __KERNEL_RCSID(0, "$NetBSD: zs.c,v 1.21 2007/11/26 23:29:36 ad Exp $"); 48 49 #include "opt_ddb.h" 50 #include "opt_kgdb.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/conf.h> 55 #include <sys/device.h> 56 #include <sys/file.h> 57 #include <sys/ioctl.h> 58 #include <sys/kernel.h> 59 #include <sys/proc.h> 60 #include <sys/tty.h> 61 #include <sys/time.h> 62 #include <sys/syslog.h> 63 #include <sys/cpu.h> 64 #include <sys/intr.h> 65 66 #include <machine/mainboard.h> 67 #include <machine/autoconf.h> 68 #include <machine/prom.h> 69 #include <machine/z8530var.h> 70 71 #include <dev/cons.h> 72 #include <dev/ic/z8530reg.h> 73 74 #include "zsc.h" /* NZSC */ 75 #define NZS NZSC 76 77 /* Make life easier for the initialized arrays here. */ 78 #if NZS < 2 79 #undef NZS 80 #define NZS 2 81 #endif 82 83 /* 84 * Some warts needed by z8530tty.c - 85 * The default parity REALLY needs to be the same as the PROM uses, 86 * or you can not see messages done with printf during boot-up... 87 */ 88 int zs_def_cflag = (CREAD | CS8 | HUPCL); 89 90 91 #define PCLK 10000000 /* PCLK pin input clock rate */ 92 93 #ifndef ZS_DEFSPEED 94 #define ZS_DEFSPEED 9600 95 #endif 96 97 /* 98 * Define interrupt levels. 99 */ 100 #define ZSHARD_PRI 64 101 102 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 103 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 104 #define ZS_DELAY() delay(ZS_RECOVERY) 105 106 /* The layout of this is hardware-dependent (padding, order). */ 107 struct zschan { 108 u_char pad1[3]; 109 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 110 u_char pad2[3]; 111 volatile u_char zc_data; /* data */ 112 }; 113 struct zsdevice { 114 /* Yes, they are backwards. */ 115 struct zschan zs_chan_b; 116 struct zschan zs_chan_a; 117 }; 118 119 /* Return the byte offset of element within a structure */ 120 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 121 122 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 123 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 124 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 125 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 126 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 127 128 /* Flags from cninit() */ 129 static int zs_hwflags[NZS][2]; 130 131 /* Default speed for all channels */ 132 static int zs_defspeed = ZS_DEFSPEED; 133 static volatile int zssoftpending; 134 135 static u_char zs_init_reg[16] = { 136 0, /* 0: CMD (reset, etc.) */ 137 0, /* 1: No interrupts yet. */ 138 ZSHARD_PRI, /* 2: IVECT */ 139 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 140 ZSWR4_CLK_X16 | ZSWR4_ONESB, 141 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 142 0, /* 6: TXSYNC/SYNCLO */ 143 0, /* 7: RXSYNC/SYNCHI */ 144 0, /* 8: alias for data port */ 145 ZSWR9_MASTER_IE, 146 0, /*10: Misc. TX/RX control bits */ 147 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 148 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 149 0, /*13: BAUDHI (default=9600) */ 150 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 151 ZSWR15_BREAK_IE, 152 }; 153 154 155 /**************************************************************** 156 * Autoconfig 157 ****************************************************************/ 158 159 /* Definition of the driver for autoconfig. */ 160 static int zs_match __P((struct device *, struct cfdata *, void *)); 161 static void zs_attach __P((struct device *, struct device *, void *)); 162 static int zs_print __P((void *, const char *name)); 163 164 CFATTACH_DECL(zsc, sizeof(struct zsc_softc), 165 zs_match, zs_attach, NULL, NULL); 166 167 extern struct cfdriver zsc_cd; 168 169 static int zshard __P((void *)); 170 void zssoft __P((void *)); 171 static int zs_get_speed __P((struct zs_chanstate *)); 172 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 173 int zs_getc __P((void *)); 174 void zs_putc __P((void *, int)); 175 176 /* 177 * Is the zs chip present? 178 */ 179 static int 180 zs_match(parent, cf, aux) 181 struct device *parent; 182 struct cfdata *cf; 183 void *aux; 184 { 185 struct confargs *ca = aux; 186 void *va; 187 188 if (strcmp(ca->ca_name, "zsc")) 189 return 0; 190 191 va = (void *)cf->cf_addr; 192 193 /* This returns -1 on a fault (bus error). */ 194 if (badaddr(va, 1)) 195 return 0; 196 return 1; 197 } 198 199 /* 200 * Attach a found zs. 201 * 202 * Match slave number to zs unit number, so that misconfiguration will 203 * not set up the keyboard as ttya, etc. 204 */ 205 static void 206 zs_attach(parent, self, aux) 207 struct device *parent; 208 struct device *self; 209 void *aux; 210 { 211 struct zsc_softc *zsc = (void *) self; 212 struct confargs *ca = aux; 213 struct zsc_attach_args zsc_args; 214 struct zs_chanstate *cs; 215 struct zs_channel *ch; 216 int zs_unit, channel, s; 217 218 zsc->zsc_bustag = ca->ca_bustag; 219 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 220 sizeof(struct zsdevice), 221 BUS_SPACE_MAP_LINEAR, 222 &zsc->zsc_base) != 0) { 223 printf(": cannot map registers\n"); 224 return; 225 } 226 227 zs_unit = device_unit(&zsc->zsc_dev); 228 printf("\n"); 229 230 /* 231 * Initialize software state for each channel. 232 */ 233 for (channel = 0; channel < 2; channel++) { 234 zsc_args.channel = channel; 235 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 236 ch = &zsc->zsc_cs_store[channel]; 237 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 238 239 zs_lock_init(cs); 240 cs->cs_reg_csr = NULL; 241 cs->cs_reg_data = NULL; 242 cs->cs_channel = channel; 243 cs->cs_private = NULL; 244 cs->cs_ops = &zsops_null; 245 cs->cs_brg_clk = PCLK / 16; 246 247 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 248 zs_chan_offset[channel], 249 sizeof(struct zschan), 250 &ch->cs_regs) != 0) { 251 printf(": cannot map regs\n"); 252 return; 253 } 254 ch->cs_bustag = ca->ca_bustag; 255 256 memcpy(cs->cs_creg, zs_init_reg, 16); 257 memcpy(cs->cs_preg, zs_init_reg, 16); 258 259 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 260 cs->cs_defspeed = zs_get_speed(cs); 261 else 262 cs->cs_defspeed = zs_defspeed; 263 cs->cs_defcflag = zs_def_cflag; 264 265 /* Make these correspond to cs_defcflag (-crtscts) */ 266 cs->cs_rr0_dcd = ZSRR0_DCD; 267 cs->cs_rr0_cts = 0; 268 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 269 cs->cs_wr5_rts = 0; 270 271 /* 272 * Clear the master interrupt enable. 273 * The INTENA is common to both channels, 274 * so just do it on the A channel. 275 */ 276 if (channel == 0) { 277 zs_write_reg(cs, 9, 0); 278 } 279 /* 280 * Look for a child driver for this channel. 281 * The child attach will setup the hardware. 282 */ 283 if (!config_found(self, (void *)&zsc_args, zs_print)) { 284 /* No sub-driver. Just reset it. */ 285 u_char reset = (channel == 0) ? 286 ZSWR9_A_RESET : ZSWR9_B_RESET; 287 288 s = splhigh(); 289 zs_write_reg(cs, 9, reset); 290 splx(s); 291 } 292 } 293 294 295 zsc->sc_si = softint_establish(SOFTINT_SERIAL, zssoft, zsc); 296 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 297 298 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 299 self->dv_xname, "intr"); 300 301 /* 302 * Set the master interrupt enable and interrupt vector. 303 * (common to both channels, do it on A) 304 */ 305 cs = zsc->zsc_cs[0]; 306 s = splhigh(); 307 /* interrupt vector */ 308 zs_write_reg(cs, 2, zs_init_reg[2]); 309 /* master interrupt control (enable) */ 310 zs_write_reg(cs, 9, zs_init_reg[9]); 311 splx(s); 312 } 313 314 static int 315 zs_print(aux, name) 316 void *aux; 317 const char *name; 318 { 319 struct zsc_attach_args *args = aux; 320 321 if (name != NULL) 322 aprint_normal("%s: ", name); 323 324 if (args->channel != -1) 325 aprint_normal(" channel %d", args->channel); 326 327 return UNCONF; 328 } 329 330 /* 331 * Our ZS chips all share a common, autovectored interrupt, 332 * so we have to look at all of them on each interrupt. 333 */ 334 static int 335 zshard(arg) 336 void *arg; 337 { 338 register struct zsc_softc *zsc; 339 register int unit, rval, softreq; 340 341 rval = 0; 342 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 343 zsc = zsc_cd.cd_devs[unit]; 344 if (zsc == NULL) 345 continue; 346 rval |= zsc_intr_hard(zsc); 347 softreq = zsc->zsc_cs[0]->cs_softreq; 348 softreq |= zsc->zsc_cs[1]->cs_softreq; 349 if (softreq && (zssoftpending == 0)) { 350 zssoftpending = 1; 351 softint_schedule(zsc->sc_si); 352 } 353 zsc->zs_intrcnt.ev_count++; 354 } 355 return rval; 356 } 357 358 /* 359 * Similar scheme as for zshard (look at all of them) 360 */ 361 void 362 zssoft(arg) 363 void *arg; 364 { 365 register struct zsc_softc *zsc; 366 register int s, unit; 367 368 /* This is not the only ISR on this IPL. */ 369 if (zssoftpending == 0) 370 return; 371 372 /* 373 * The soft intr. bit will be set by zshard only if 374 * the variable zssoftpending is zero. The order of 375 * these next two statements prevents our clearing 376 * the soft intr bit just after zshard has set it. 377 */ 378 /*isr_soft_clear(ZSSOFT_PRI);*/ 379 zssoftpending = 0; 380 381 /* Make sure we call the tty layer at spltty. */ 382 s = spltty(); 383 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 384 zsc = zsc_cd.cd_devs[unit]; 385 if (zsc == NULL) 386 continue; 387 (void) zsc_intr_soft(zsc); 388 } 389 splx(s); 390 return; 391 } 392 393 394 /* 395 * Compute the current baud rate given a ZS channel. 396 */ 397 static int 398 zs_get_speed(cs) 399 struct zs_chanstate *cs; 400 { 401 int tconst; 402 403 tconst = zs_read_reg(cs, 12); 404 tconst |= zs_read_reg(cs, 13) << 8; 405 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 406 } 407 408 /* 409 * MD functions for setting the baud rate and control modes. 410 */ 411 int 412 zs_set_speed(cs, bps) 413 struct zs_chanstate *cs; 414 int bps; /* bits per second */ 415 { 416 int tconst, real_bps; 417 418 #if 0 419 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 420 {/*nop*/} 421 #endif 422 /* Wait for transmit buffer to empty */ 423 if (bps == 0) { 424 return (0); 425 } 426 427 #ifdef DIAGNOSTIC 428 if (cs->cs_brg_clk == 0) 429 panic("zs_set_speed"); 430 #endif 431 432 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 433 if (tconst < 0) 434 return (EINVAL); 435 436 /* Convert back to make sure we can do it. */ 437 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 438 439 /* XXX - Allow some tolerance here? */ 440 #if 0 441 if (real_bps != bps) 442 return (EINVAL); 443 #endif 444 445 cs->cs_preg[12] = tconst; 446 cs->cs_preg[13] = tconst >> 8; 447 448 /* Caller will stuff the pending registers. */ 449 return (0); 450 } 451 452 int 453 zs_set_modes(cs, cflag) 454 struct zs_chanstate *cs; 455 int cflag; /* bits per second */ 456 { 457 int s; 458 459 /* 460 * Output hardware flow control on the chip is horrendous: 461 * if carrier detect drops, the receiver is disabled, and if 462 * CTS drops, the transmitter is stoped IN MID CHARACTER! 463 * Therefore, NEVER set the HFC bit, and instead use the 464 * status interrupt to detect CTS changes. 465 */ 466 s = splzs(); 467 cs->cs_rr0_pps = 0; 468 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 469 cs->cs_rr0_dcd = 0; 470 if ((cflag & MDMBUF) == 0) 471 cs->cs_rr0_pps = ZSRR0_DCD; 472 } else 473 cs->cs_rr0_dcd = ZSRR0_DCD; 474 if ((cflag & CRTSCTS) != 0) { 475 cs->cs_wr5_dtr = ZSWR5_DTR; 476 cs->cs_wr5_rts = ZSWR5_RTS; 477 cs->cs_rr0_cts = ZSRR0_CTS; 478 } else if ((cflag & MDMBUF) != 0) { 479 cs->cs_wr5_dtr = 0; 480 cs->cs_wr5_rts = ZSWR5_DTR; 481 cs->cs_rr0_cts = ZSRR0_DCD; 482 } else { 483 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 484 cs->cs_wr5_rts = 0; 485 cs->cs_rr0_cts = 0; 486 } 487 splx(s); 488 489 /* Caller will stuff the pending registers. */ 490 return (0); 491 } 492 493 494 /* 495 * Read or write the chip with suitable delays. 496 */ 497 498 u_char 499 zs_read_reg(cs, reg) 500 struct zs_chanstate *cs; 501 u_char reg; 502 { 503 u_char val; 504 struct zs_channel *zsc = (struct zs_channel *)cs; 505 506 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 507 ZS_DELAY(); 508 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 509 ZS_DELAY(); 510 return val; 511 } 512 513 void 514 zs_write_reg(cs, reg, val) 515 struct zs_chanstate *cs; 516 u_char reg, val; 517 { 518 struct zs_channel *zsc = (struct zs_channel *)cs; 519 520 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 521 ZS_DELAY(); 522 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 523 ZS_DELAY(); 524 } 525 526 u_char zs_read_csr(cs) 527 struct zs_chanstate *cs; 528 { 529 struct zs_channel *zsc = (struct zs_channel *)cs; 530 register u_char val; 531 532 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 533 ZS_DELAY(); 534 return val; 535 } 536 537 void zs_write_csr(cs, val) 538 struct zs_chanstate *cs; 539 u_char val; 540 { 541 struct zs_channel *zsc = (struct zs_channel *)cs; 542 543 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 544 ZS_DELAY(); 545 } 546 547 u_char zs_read_data(cs) 548 struct zs_chanstate *cs; 549 { 550 struct zs_channel *zsc = (struct zs_channel *)cs; 551 register u_char val; 552 553 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 554 ZS_DELAY(); 555 return val; 556 } 557 558 void zs_write_data(cs, val) 559 struct zs_chanstate *cs; 560 u_char val; 561 { 562 struct zs_channel *zsc = (struct zs_channel *)cs; 563 564 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 565 ZS_DELAY(); 566 } 567 568 void 569 zs_abort(cs) 570 struct zs_chanstate *cs; 571 { 572 #if defined(KGDB) 573 zskgdb(cs); 574 #elif defined(DDB) 575 Debugger(); 576 #endif 577 } 578 579 580 /*********************************************************/ 581 /* Polled character I/O functions for console and KGDB */ 582 /*********************************************************/ 583 584 struct zschan * 585 zs_get_chan_addr(zs_unit, channel) 586 int zs_unit, channel; 587 { 588 struct zsdevice *addr; 589 struct zschan *zc; 590 591 if (zs_unit >= NZS) 592 return NULL; 593 594 addr = (struct zsdevice *) ZS0_ADDR; 595 596 if (channel == 0) { 597 zc = &addr->zs_chan_a; 598 } else { 599 zc = &addr->zs_chan_b; 600 } 601 return (zc); 602 } 603 604 int 605 zs_getc(arg) 606 void *arg; 607 { 608 register volatile struct zschan *zc = arg; 609 register int s, c, rr0; 610 611 s = splhigh(); 612 /* Wait for a character to arrive. */ 613 do { 614 rr0 = zc->zc_csr; 615 ZS_DELAY(); 616 } while ((rr0 & ZSRR0_RX_READY) == 0); 617 618 c = zc->zc_data; 619 ZS_DELAY(); 620 splx(s); 621 622 return (c); 623 } 624 625 /* 626 * Polled output char. 627 */ 628 void 629 zs_putc(arg, c) 630 void *arg; 631 int c; 632 { 633 register volatile struct zschan *zc = arg; 634 register int s, rr0; 635 636 s = splhigh(); 637 /* Wait for transmitter to become ready. */ 638 do { 639 rr0 = zc->zc_csr; 640 ZS_DELAY(); 641 } while ((rr0 & ZSRR0_TX_READY) == 0); 642 643 zc->zc_data = c; 644 wbflush(); 645 ZS_DELAY(); 646 splx(s); 647 } 648 649 /***************************************************************/ 650 651 static void zscnprobe __P((struct consdev *)); 652 static void zscninit __P((struct consdev *)); 653 static int zscngetc __P((dev_t)); 654 static void zscnputc __P((dev_t, int)); 655 static void zscnpollc __P((dev_t, int)); 656 657 static int cons_port; 658 659 struct consdev consdev_zs = { 660 zscnprobe, 661 zscninit, 662 zscngetc, 663 zscnputc, 664 zscnpollc 665 }; 666 667 void 668 zscnprobe(cn) 669 struct consdev *cn; 670 { 671 } 672 673 void 674 zscninit(cn) 675 struct consdev *cn; 676 { 677 extern const struct cdevsw zstty_cdevsw; 678 679 cons_port = prom_getconsole(); 680 cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), cons_port); 681 cn->cn_pri = CN_REMOTE; 682 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 683 } 684 685 int 686 zscngetc(dev) 687 dev_t dev; 688 { 689 struct zschan *zs; 690 691 zs = zs_get_chan_addr(0, cons_port); 692 return zs_getc(zs); 693 } 694 695 void 696 zscnputc(dev, c) 697 dev_t dev; 698 int c; 699 { 700 struct zschan *zs; 701 702 zs = zs_get_chan_addr(0, cons_port); 703 zs_putc(zs, c); 704 } 705 706 void 707 zscnpollc(dev, on) 708 dev_t dev; 709 int on; 710 { 711 } 712
Indexes created Tue Sep 30 11:09:46 GMT 2025