zs.c revision 1.5
1 /* $NetBSD: zs.c,v 1.5 2000/12/03 04:51:05 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <machine/cpu.h> 61 #include <machine/mainboard.h> 62 #include <machine/autoconf.h> 63 #include <machine/prom.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include "zsc.h" /* NZSC */ 70 #define NZS NZSC 71 72 /* Make life easier for the initialized arrays here. */ 73 #if NZS < 2 74 #undef NZS 75 #define NZS 2 76 #endif 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zs_major = 1; 85 86 /* 87 * 10MHz PCLK 88 */ 89 #define PCLK 10000000 /* PCLK pin input clock rate */ 90 91 /* 92 * Define interrupt levels. 93 */ 94 #define ZSHARD_PRI 64 95 96 #define ZS_DELAY() delay(2); 97 98 static struct zschan *zs_get_chan_addr (int zs_unit, int channel); 99 static int zs_getc (void *); 100 static void zs_putc (void *, int); 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 u_char pad1[3]; 105 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 106 u_char pad2[3]; 107 volatile u_char zc_data; /* data */ 108 }; 109 struct zsdevice { 110 /* Yes, they are backwards. */ 111 struct zschan zs_chan_b; 112 struct zschan zs_chan_a; 113 }; 114 115 /* Flags from cninit() */ 116 static int zs_hwflags[NZS][2]; 117 118 /* Default speed for all channels */ 119 static int zs_defspeed = 9600; 120 121 static u_char zs_init_reg[16] = { 122 0, /* 0: CMD (reset, etc.) */ 123 0, /* 1: No interrupts yet. */ 124 ZSHARD_PRI, /* IVECT */ 125 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 126 ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP, 127 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 128 0, /* 6: TXSYNC/SYNCLO */ 129 0, /* 7: RXSYNC/SYNCHI */ 130 0, /* 8: alias for data port */ 131 ZSWR9_MASTER_IE, 132 0, /*10: Misc. TX/RX control bits */ 133 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 134 ((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */ 135 0, /*13: BAUDHI (default=9600) */ 136 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 137 ZSWR15_BREAK_IE, 138 }; 139 140 141 static struct zschan * 142 zs_get_chan_addr(zs_unit, channel) 143 int zs_unit, channel; 144 { 145 struct zsdevice *addr; 146 struct zschan *zc; 147 148 if (zs_unit >= NZS) 149 return NULL; 150 151 addr = (struct zsdevice *) ZS0_ADDR; 152 153 if (channel == 0) { 154 zc = &addr->zs_chan_a; 155 } else { 156 zc = &addr->zs_chan_b; 157 } 158 return (zc); 159 } 160 161 162 /**************************************************************** 163 * Autoconfig 164 ****************************************************************/ 165 166 /* Definition of the driver for autoconfig. */ 167 static int zs_match __P((struct device *, struct cfdata *, void *)); 168 static void zs_attach __P((struct device *, struct device *, void *)); 169 static int zs_print __P((void *, const char *name)); 170 171 struct cfattach zsc_ca = { 172 sizeof(struct zsc_softc), zs_match, zs_attach 173 }; 174 175 extern struct cfdriver zsc_cd; 176 177 static int zshard __P((void *)); 178 static void zssoft __P((void *)); 179 static int zs_get_speed __P((struct zs_chanstate *)); 180 181 182 /* 183 * Is the zs chip present? 184 */ 185 static int 186 zs_match(parent, cf, aux) 187 struct device *parent; 188 struct cfdata *cf; 189 void *aux; 190 { 191 struct confargs *ca = aux; 192 void *va; 193 194 if (strcmp(ca->ca_name, "zsc")) 195 return 0; 196 197 va = (void *)cf->cf_addr; 198 199 /* This returns -1 on a fault (bus error). */ 200 if (badaddr(va, 1)) 201 return 0; 202 return 1; 203 } 204 205 /* 206 * Attach a found zs. 207 * 208 * Match slave number to zs unit number, so that misconfiguration will 209 * not set up the keyboard as ttya, etc. 210 */ 211 static void 212 zs_attach(parent, self, aux) 213 struct device *parent; 214 struct device *self; 215 void *aux; 216 { 217 struct zsc_softc *zsc = (void *) self; 218 struct confargs *ca = aux; 219 struct zsc_attach_args zsc_args; 220 struct zsdevice *zsd; 221 struct zschan *zc; 222 struct zs_chanstate *cs; 223 int s, zs_unit, channel; 224 225 zsc->zsc_bustag = ca->ca_bustag; 226 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 227 sizeof(struct zsdevice), 228 BUS_SPACE_MAP_LINEAR, 229 &zsc->zsc_base) != 0) { 230 printf(": cannot map registers\n"); 231 return; 232 } 233 zsd = (struct zsdevice *)zsc->zsc_base; 234 235 zs_unit = zsc->zsc_dev.dv_unit; 236 printf("\n"); 237 238 /* 239 * Initialize software state for each channel. 240 */ 241 for (channel = 0; channel < 2; channel++) { 242 zsc_args.channel = channel; 243 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 244 cs = &zsc->zsc_cs_store[channel]; 245 zsc->zsc_cs[channel] = cs; 246 247 cs->cs_channel = channel; 248 cs->cs_private = NULL; 249 cs->cs_ops = &zsops_null; 250 cs->cs_brg_clk = PCLK / 16; 251 252 zc = (channel == 0) ? &zsd->zs_chan_a : &zsd->zs_chan_b; 253 254 cs->cs_reg_csr = &zc->zc_csr; 255 cs->cs_reg_data = &zc->zc_data; 256 257 bcopy(zs_init_reg, cs->cs_creg, 16); 258 bcopy(zs_init_reg, cs->cs_preg, 16); 259 260 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 261 cs->cs_defspeed = zs_get_speed(cs); 262 else 263 cs->cs_defspeed = zs_defspeed; 264 cs->cs_defcflag = zs_def_cflag; 265 266 /* Make these correspond to cs_defcflag (-crtscts) */ 267 cs->cs_rr0_dcd = ZSRR0_DCD; 268 cs->cs_rr0_cts = 0; 269 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 270 cs->cs_wr5_rts = 0; 271 272 /* 273 * Clear the master interrupt enable. 274 * The INTENA is common to both channels, 275 * so just do it on the A channel. 276 */ 277 if (channel == 0) { 278 zs_write_reg(cs, 9, 0); 279 } 280 /* 281 * Look for a child driver for this channel. 282 * The child attach will setup the hardware. 283 */ 284 if (!config_found(self, (void *)&zsc_args, zs_print)) { 285 /* No sub-driver. Just reset it. */ 286 u_char reset = (channel == 0) ? 287 ZSWR9_A_RESET : ZSWR9_B_RESET; 288 289 s = splhigh(); 290 zs_write_reg(cs, 9, reset); 291 splx(s); 292 } 293 } 294 295 /* bus_intr_establish(zssoft, NULL, ZSSOFT_PRI); */ 296 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 297 298 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 299 self->dv_xname, "intr"); 300 301 /* 302 * Set the master interrupt enable and interrupt vector. 303 * (common to both channels, do it on A) 304 */ 305 cs = zsc->zsc_cs[0]; 306 s = splhigh(); 307 /* interrupt vector */ 308 zs_write_reg(cs, 2, zs_init_reg[2]); 309 /* master interrupt control (enable) */ 310 zs_write_reg(cs, 9, zs_init_reg[9]); 311 splx(s); 312 } 313 314 static int 315 zs_print(aux, name) 316 void *aux; 317 const char *name; 318 { 319 struct zsc_attach_args *args = aux; 320 321 if (name != NULL) 322 printf("%s: ", name); 323 324 if (args->channel != -1) 325 printf(" channel %d", args->channel); 326 327 return UNCONF; 328 } 329 330 static volatile int zssoftpending; 331 332 /* 333 * Our ZS chips all share a common, autovectored interrupt, 334 * so we have to look at all of them on each interrupt. 335 */ 336 static int 337 zshard(arg) 338 void *arg; 339 { 340 register struct zsc_softc *zsc; 341 register int unit, rval, softreq; 342 343 rval = softreq = 0; 344 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 345 zsc = zsc_cd.cd_devs[unit]; 346 if (zsc == NULL) 347 continue; 348 rval |= zsc_intr_hard(zsc); 349 softreq |= zsc->zsc_cs[0]->cs_softreq; 350 softreq |= zsc->zsc_cs[1]->cs_softreq; 351 zsc->zs_intrcnt.ev_count++; 352 } 353 354 /* We are at splzs here, so no need to lock. */ 355 if (softreq && (zssoftpending == 0)) { 356 zssoftpending = 1; 357 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 358 } 359 return 0; 360 } 361 362 /* 363 * Similar scheme as for zshard (look at all of them) 364 */ 365 static void 366 zssoft(arg) 367 void *arg; 368 { 369 register struct zsc_softc *zsc; 370 register int s, unit; 371 372 /* This is not the only ISR on this IPL. */ 373 if (zssoftpending == 0) 374 return; 375 376 /* 377 * The soft intr. bit will be set by zshard only if 378 * the variable zssoftpending is zero. The order of 379 * these next two statements prevents our clearing 380 * the soft intr bit just after zshard has set it. 381 */ 382 /*isr_soft_clear(ZSSOFT_PRI);*/ 383 /*zssoftpending = 0;*/ 384 385 /* Make sure we call the tty layer at spltty. */ 386 s = spltty(); 387 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 388 zsc = zsc_cd.cd_devs[unit]; 389 if (zsc == NULL) 390 continue; 391 (void) zsc_intr_soft(zsc); 392 } 393 splx(s); 394 zssoftpending = 0; 395 return; 396 } 397 398 399 /* 400 * Compute the current baud rate given a ZS channel. 401 */ 402 static int 403 zs_get_speed(cs) 404 struct zs_chanstate *cs; 405 { 406 int tconst; 407 408 tconst = zs_read_reg(cs, 12); 409 tconst |= zs_read_reg(cs, 13) << 8; 410 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 411 } 412 413 /* 414 * MD functions for setting the baud rate and control modes. 415 */ 416 int 417 zs_set_speed(cs, bps) 418 struct zs_chanstate *cs; 419 int bps; /* bits per second */ 420 { 421 int tconst, real_bps; 422 423 /* Wait for transmit buffer to empty */ 424 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 425 {/*nop*/} 426 427 if (bps == 0) 428 return (0); 429 430 #ifdef DIAGNOSTIC 431 if (cs->cs_brg_clk == 0) 432 panic("zs_set_speed"); 433 #endif 434 435 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 436 if (tconst < 0) 437 return (EINVAL); 438 439 /* Convert back to make sure we can do it. */ 440 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 441 442 /* XXX - Allow some tolerance here? */ 443 #if 0 444 if (real_bps != bps) 445 return (EINVAL); 446 #endif 447 448 cs->cs_preg[12] = tconst; 449 cs->cs_preg[13] = tconst >> 8; 450 451 /* Caller will stuff the pending registers. */ 452 return (0); 453 } 454 455 int 456 zs_set_modes(cs, cflag) 457 struct zs_chanstate *cs; 458 int cflag; /* bits per second */ 459 { 460 int s; 461 462 /* 463 * Output hardware flow control on the chip is horrendous: 464 * if carrier detect drops, the receiver is disabled, and if 465 * CTS drops, the transmitter is stoped IN MID CHARACTER! 466 * Therefore, NEVER set the HFC bit, and instead use the 467 * status interrupt to detect CTS changes. 468 */ 469 s = splzs(); 470 cs->cs_rr0_pps = 0; 471 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 472 cs->cs_rr0_dcd = 0; 473 if ((cflag & MDMBUF) == 0) 474 cs->cs_rr0_pps = ZSRR0_DCD; 475 } else 476 cs->cs_rr0_dcd = ZSRR0_DCD; 477 if ((cflag & CRTSCTS) != 0) { 478 cs->cs_wr5_dtr = ZSWR5_DTR; 479 cs->cs_wr5_rts = ZSWR5_RTS; 480 cs->cs_rr0_cts = ZSRR0_CTS; 481 } else if ((cflag & MDMBUF) != 0) { 482 cs->cs_wr5_dtr = 0; 483 cs->cs_wr5_rts = ZSWR5_DTR; 484 cs->cs_rr0_cts = ZSRR0_DCD; 485 } else { 486 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 487 cs->cs_wr5_rts = 0; 488 cs->cs_rr0_cts = 0; 489 } 490 splx(s); 491 492 /* Caller will stuff the pending registers. */ 493 return (0); 494 } 495 496 497 /* 498 * Read or write the chip with suitable delays. 499 */ 500 501 u_char 502 zs_read_reg(cs, reg) 503 struct zs_chanstate *cs; 504 u_char reg; 505 { 506 u_char val; 507 508 *cs->cs_reg_csr = reg; 509 ZS_DELAY(); 510 val = *cs->cs_reg_csr; 511 ZS_DELAY(); 512 return val; 513 } 514 515 void 516 zs_write_reg(cs, reg, val) 517 struct zs_chanstate *cs; 518 u_char reg, val; 519 { 520 *cs->cs_reg_csr = reg; 521 ZS_DELAY(); 522 *cs->cs_reg_csr = val; 523 ZS_DELAY(); 524 } 525 526 u_char zs_read_csr(cs) 527 struct zs_chanstate *cs; 528 { 529 register u_char val; 530 531 val = *cs->cs_reg_csr; 532 ZS_DELAY(); 533 return val; 534 } 535 536 void zs_write_csr(cs, val) 537 struct zs_chanstate *cs; 538 u_char val; 539 { 540 *cs->cs_reg_csr = val; 541 ZS_DELAY(); 542 } 543 544 u_char zs_read_data(cs) 545 struct zs_chanstate *cs; 546 { 547 register u_char val; 548 549 val = *cs->cs_reg_data; 550 ZS_DELAY(); 551 return val; 552 } 553 554 void zs_write_data(cs, val) 555 struct zs_chanstate *cs; 556 u_char val; 557 { 558 *cs->cs_reg_data = val; 559 ZS_DELAY(); 560 } 561 562 void 563 zs_abort(cs) 564 struct zs_chanstate *cs; 565 { 566 #ifdef DDB 567 Debugger(); 568 #endif 569 } 570 571 /* 572 * Polled input char. 573 */ 574 int 575 zs_getc(arg) 576 void *arg; 577 { 578 register volatile struct zschan *zc = arg; 579 register int s, c, rr0; 580 581 s = splhigh(); 582 /* Wait for a character to arrive. */ 583 do { 584 rr0 = zc->zc_csr; 585 ZS_DELAY(); 586 } while ((rr0 & ZSRR0_RX_READY) == 0); 587 588 c = zc->zc_data; 589 ZS_DELAY(); 590 splx(s); 591 592 /* 593 * This is used by the kd driver to read scan codes, 594 * so don't translate '\r' ==> '\n' here... 595 */ 596 return (c); 597 } 598 599 /* 600 * Polled output char. 601 */ 602 static void 603 zs_putc(arg, c) 604 void *arg; 605 int c; 606 { 607 register volatile struct zschan *zc = arg; 608 register int s, rr0; 609 610 s = splhigh(); 611 /* Wait for transmitter to become ready. */ 612 do { 613 rr0 = zc->zc_csr; 614 ZS_DELAY(); 615 } while ((rr0 & ZSRR0_TX_READY) == 0); 616 617 zc->zc_data = c; 618 ZS_DELAY(); 619 splx(s); 620 } 621 622 /*****************************************************************/ 623 624 static void zscnprobe __P((struct consdev *)); 625 static void zscninit __P((struct consdev *)); 626 static int zscngetc __P((dev_t)); 627 static void zscnputc __P((dev_t, int)); 628 static void zscnpollc __P((dev_t, int)); 629 630 static int cons_port; 631 632 struct consdev consdev_zs = { 633 zscnprobe, 634 zscninit, 635 zscngetc, 636 zscnputc, 637 zscnpollc 638 }; 639 640 void 641 zscnprobe(cn) 642 struct consdev *cn; 643 { 644 } 645 646 void 647 zscninit(cn) 648 struct consdev *cn; 649 { 650 cons_port = prom_getconsole(); 651 cn->cn_dev = makedev(zs_major, cons_port); 652 cn->cn_pri = CN_REMOTE; 653 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 654 } 655 656 int 657 zscngetc(dev) 658 dev_t dev; 659 { 660 struct zschan *zs; 661 662 zs = zs_get_chan_addr(0, cons_port); 663 return zs_getc(zs); 664 } 665 666 void 667 zscnputc(dev, c) 668 dev_t dev; 669 int c; 670 { 671 struct zschan *zs; 672 673 zs = zs_get_chan_addr(0, cons_port); 674 zs_putc(zs, c); 675 } 676 677 void 678 zscnpollc(dev, on) 679 dev_t dev; 680 int on; 681 { 682 } 683
Indexes created Tue Sep 30 11:09:46 GMT 2025