zs.c revision 1.7
1 /* $NetBSD: zs.c,v 1.7 2001/02/21 09:12:14 wdk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 #ifdef KGDB 60 #include <sys/kgdb.h> 61 #endif 62 63 #include <machine/cpu.h> 64 #include <machine/mainboard.h> 65 #include <machine/autoconf.h> 66 #include <machine/prom.h> 67 #include <machine/z8530var.h> 68 69 #include <dev/cons.h> 70 #include <dev/ic/z8530reg.h> 71 72 #include "zsc.h" /* NZSC */ 73 #define NZS NZSC 74 75 /* Make life easier for the initialized arrays here. */ 76 #if NZS < 2 77 #undef NZS 78 #define NZS 2 79 #endif 80 81 /* 82 * Some warts needed by z8530tty.c - 83 * The default parity REALLY needs to be the same as the PROM uses, 84 * or you can not see messages done with printf during boot-up... 85 */ 86 int zs_def_cflag = (CREAD | CS8 | HUPCL); 87 int zs_major = 1; 88 89 90 #define PCLK 10000000 /* PCLK pin input clock rate */ 91 92 #ifndef ZS_DEFSPEED 93 #define ZS_DEFSPEED 9600 94 #endif 95 96 /* 97 * Define interrupt levels. 98 */ 99 #define ZSHARD_PRI 64 100 101 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 102 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 103 #define ZS_DELAY() delay(ZS_RECOVERY) 104 105 /* The layout of this is hardware-dependent (padding, order). */ 106 struct zschan { 107 u_char pad1[3]; 108 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 109 u_char pad2[3]; 110 volatile u_char zc_data; /* data */ 111 }; 112 struct zsdevice { 113 /* Yes, they are backwards. */ 114 struct zschan zs_chan_b; 115 struct zschan zs_chan_a; 116 }; 117 118 /* Return the byte offset of element within a structure */ 119 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 120 121 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 122 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 123 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 124 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 125 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 126 127 /* Flags from cninit() */ 128 static int zs_hwflags[NZS][2]; 129 130 /* Default speed for all channels */ 131 static int zs_defspeed = ZS_DEFSPEED; 132 static volatile int zssoftpending; 133 134 static u_char zs_init_reg[16] = { 135 0, /* 0: CMD (reset, etc.) */ 136 0, /* 1: No interrupts yet. */ 137 ZSHARD_PRI, /* 2: IVECT */ 138 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 139 ZSWR4_CLK_X16 | ZSWR4_ONESB, 140 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 141 0, /* 6: TXSYNC/SYNCLO */ 142 0, /* 7: RXSYNC/SYNCHI */ 143 0, /* 8: alias for data port */ 144 ZSWR9_MASTER_IE, 145 0, /*10: Misc. TX/RX control bits */ 146 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 147 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 148 0, /*13: BAUDHI (default=9600) */ 149 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 150 ZSWR15_BREAK_IE, 151 }; 152 153 154 /**************************************************************** 155 * Autoconfig 156 ****************************************************************/ 157 158 /* Definition of the driver for autoconfig. */ 159 static int zs_match __P((struct device *, struct cfdata *, void *)); 160 static void zs_attach __P((struct device *, struct device *, void *)); 161 static int zs_print __P((void *, const char *name)); 162 163 struct cfattach zsc_ca = { 164 sizeof(struct zsc_softc), zs_match, zs_attach 165 }; 166 167 extern struct cfdriver zsc_cd; 168 169 static int zshard __P((void *)); 170 static void zssoft __P((void *)); 171 static int zs_get_speed __P((struct zs_chanstate *)); 172 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 173 int zs_getc __P((void *)); 174 void zs_putc __P((void *, int)); 175 176 /* 177 * Is the zs chip present? 178 */ 179 static int 180 zs_match(parent, cf, aux) 181 struct device *parent; 182 struct cfdata *cf; 183 void *aux; 184 { 185 struct confargs *ca = aux; 186 void *va; 187 188 if (strcmp(ca->ca_name, "zsc")) 189 return 0; 190 191 va = (void *)cf->cf_addr; 192 193 /* This returns -1 on a fault (bus error). */ 194 if (badaddr(va, 1)) 195 return 0; 196 return 1; 197 } 198 199 /* 200 * Attach a found zs. 201 * 202 * Match slave number to zs unit number, so that misconfiguration will 203 * not set up the keyboard as ttya, etc. 204 */ 205 static void 206 zs_attach(parent, self, aux) 207 struct device *parent; 208 struct device *self; 209 void *aux; 210 { 211 struct zsc_softc *zsc = (void *) self; 212 struct confargs *ca = aux; 213 struct zsc_attach_args zsc_args; 214 struct zs_chanstate *cs; 215 struct zs_channel *ch; 216 int zs_unit, channel, s; 217 218 zsc->zsc_bustag = ca->ca_bustag; 219 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 220 sizeof(struct zsdevice), 221 BUS_SPACE_MAP_LINEAR, 222 &zsc->zsc_base) != 0) { 223 printf(": cannot map registers\n"); 224 return; 225 } 226 227 zs_unit = zsc->zsc_dev.dv_unit; 228 printf("\n"); 229 230 /* 231 * Initialize software state for each channel. 232 */ 233 for (channel = 0; channel < 2; channel++) { 234 zsc_args.channel = channel; 235 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 236 ch = &zsc->zsc_cs_store[channel]; 237 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 238 239 cs->cs_reg_csr = NULL; 240 cs->cs_reg_data = NULL; 241 cs->cs_channel = channel; 242 cs->cs_private = NULL; 243 cs->cs_ops = &zsops_null; 244 cs->cs_brg_clk = PCLK / 16; 245 246 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 247 zs_chan_offset[channel], 248 sizeof(struct zschan), 249 &ch->cs_regs) != 0) { 250 printf(": cannot map regs\n"); 251 return; 252 } 253 ch->cs_bustag = ca->ca_bustag; 254 255 bcopy(zs_init_reg, cs->cs_creg, 16); 256 bcopy(zs_init_reg, cs->cs_preg, 16); 257 258 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 259 cs->cs_defspeed = zs_get_speed(cs); 260 else 261 cs->cs_defspeed = zs_defspeed; 262 cs->cs_defcflag = zs_def_cflag; 263 264 /* Make these correspond to cs_defcflag (-crtscts) */ 265 cs->cs_rr0_dcd = ZSRR0_DCD; 266 cs->cs_rr0_cts = 0; 267 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 268 cs->cs_wr5_rts = 0; 269 270 /* 271 * Clear the master interrupt enable. 272 * The INTENA is common to both channels, 273 * so just do it on the A channel. 274 */ 275 if (channel == 0) { 276 zs_write_reg(cs, 9, 0); 277 } 278 /* 279 * Look for a child driver for this channel. 280 * The child attach will setup the hardware. 281 */ 282 if (!config_found(self, (void *)&zsc_args, zs_print)) { 283 /* No sub-driver. Just reset it. */ 284 u_char reset = (channel == 0) ? 285 ZSWR9_A_RESET : ZSWR9_B_RESET; 286 287 s = splhigh(); 288 zs_write_reg(cs, 9, reset); 289 splx(s); 290 } 291 } 292 293 /* bus_intr_establish(zssoft, NULL, ZSSOFT_PRI); */ 294 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 295 296 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 297 self->dv_xname, "intr"); 298 299 /* 300 * Set the master interrupt enable and interrupt vector. 301 * (common to both channels, do it on A) 302 */ 303 cs = zsc->zsc_cs[0]; 304 s = splhigh(); 305 /* interrupt vector */ 306 zs_write_reg(cs, 2, zs_init_reg[2]); 307 /* master interrupt control (enable) */ 308 zs_write_reg(cs, 9, zs_init_reg[9]); 309 splx(s); 310 } 311 312 static int 313 zs_print(aux, name) 314 void *aux; 315 const char *name; 316 { 317 struct zsc_attach_args *args = aux; 318 319 if (name != NULL) 320 printf("%s: ", name); 321 322 if (args->channel != -1) 323 printf(" channel %d", args->channel); 324 325 return UNCONF; 326 } 327 328 /* 329 * Our ZS chips all share a common, autovectored interrupt, 330 * so we have to look at all of them on each interrupt. 331 */ 332 static int 333 zshard(arg) 334 void *arg; 335 { 336 register struct zsc_softc *zsc; 337 register int unit, rval, softreq; 338 339 rval = softreq = 0; 340 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 341 zsc = zsc_cd.cd_devs[unit]; 342 if (zsc == NULL) 343 continue; 344 rval |= zsc_intr_hard(zsc); 345 softreq |= zsc->zsc_cs[0]->cs_softreq; 346 softreq |= zsc->zsc_cs[1]->cs_softreq; 347 zsc->zs_intrcnt.ev_count++; 348 } 349 350 /* We are at splzs here, so no need to lock. */ 351 if (softreq && (zssoftpending == 0)) { 352 zssoftpending = 1; 353 zssoft(arg); /*isr_soft_request(ZSSOFT_PRI);*/ 354 } 355 return 0; 356 } 357 358 /* 359 * Similar scheme as for zshard (look at all of them) 360 */ 361 static void 362 zssoft(arg) 363 void *arg; 364 { 365 register struct zsc_softc *zsc; 366 register int s, unit; 367 368 /* This is not the only ISR on this IPL. */ 369 if (zssoftpending == 0) 370 return; 371 372 /* 373 * The soft intr. bit will be set by zshard only if 374 * the variable zssoftpending is zero. The order of 375 * these next two statements prevents our clearing 376 * the soft intr bit just after zshard has set it. 377 */ 378 /*isr_soft_clear(ZSSOFT_PRI);*/ 379 /*zssoftpending = 0;*/ 380 381 /* Make sure we call the tty layer at spltty. */ 382 s = spltty(); 383 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 384 zsc = zsc_cd.cd_devs[unit]; 385 if (zsc == NULL) 386 continue; 387 (void) zsc_intr_soft(zsc); 388 } 389 splx(s); 390 zssoftpending = 0; 391 return; 392 } 393 394 395 /* 396 * Compute the current baud rate given a ZS channel. 397 */ 398 static int 399 zs_get_speed(cs) 400 struct zs_chanstate *cs; 401 { 402 int tconst; 403 404 tconst = zs_read_reg(cs, 12); 405 tconst |= zs_read_reg(cs, 13) << 8; 406 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 407 } 408 409 /* 410 * MD functions for setting the baud rate and control modes. 411 */ 412 int 413 zs_set_speed(cs, bps) 414 struct zs_chanstate *cs; 415 int bps; /* bits per second */ 416 { 417 int tconst, real_bps; 418 419 #if 1 420 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 421 {/*nop*/} 422 #endif 423 /* Wait for transmit buffer to empty */ 424 if (bps == 0) { 425 return (0); 426 } 427 428 #ifdef DIAGNOSTIC 429 if (cs->cs_brg_clk == 0) 430 panic("zs_set_speed"); 431 #endif 432 433 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 434 if (tconst < 0) 435 return (EINVAL); 436 437 /* Convert back to make sure we can do it. */ 438 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 439 440 /* XXX - Allow some tolerance here? */ 441 #if 0 442 if (real_bps != bps) 443 return (EINVAL); 444 #endif 445 446 cs->cs_preg[12] = tconst; 447 cs->cs_preg[13] = tconst >> 8; 448 449 /* Caller will stuff the pending registers. */ 450 return (0); 451 } 452 453 int 454 zs_set_modes(cs, cflag) 455 struct zs_chanstate *cs; 456 int cflag; /* bits per second */ 457 { 458 int s; 459 460 /* 461 * Output hardware flow control on the chip is horrendous: 462 * if carrier detect drops, the receiver is disabled, and if 463 * CTS drops, the transmitter is stoped IN MID CHARACTER! 464 * Therefore, NEVER set the HFC bit, and instead use the 465 * status interrupt to detect CTS changes. 466 */ 467 s = splzs(); 468 cs->cs_rr0_pps = 0; 469 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 470 cs->cs_rr0_dcd = 0; 471 if ((cflag & MDMBUF) == 0) 472 cs->cs_rr0_pps = ZSRR0_DCD; 473 } else 474 cs->cs_rr0_dcd = ZSRR0_DCD; 475 if ((cflag & CRTSCTS) != 0) { 476 cs->cs_wr5_dtr = ZSWR5_DTR; 477 cs->cs_wr5_rts = ZSWR5_RTS; 478 cs->cs_rr0_cts = ZSRR0_CTS; 479 } else if ((cflag & MDMBUF) != 0) { 480 cs->cs_wr5_dtr = 0; 481 cs->cs_wr5_rts = ZSWR5_DTR; 482 cs->cs_rr0_cts = ZSRR0_DCD; 483 } else { 484 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 485 cs->cs_wr5_rts = 0; 486 cs->cs_rr0_cts = 0; 487 } 488 splx(s); 489 490 /* Caller will stuff the pending registers. */ 491 return (0); 492 } 493 494 495 /* 496 * Read or write the chip with suitable delays. 497 */ 498 499 u_char 500 zs_read_reg(cs, reg) 501 struct zs_chanstate *cs; 502 u_char reg; 503 { 504 u_char val; 505 struct zs_channel *zsc = (struct zs_channel *)cs; 506 507 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 508 ZS_DELAY(); 509 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 510 ZS_DELAY(); 511 return val; 512 } 513 514 void 515 zs_write_reg(cs, reg, val) 516 struct zs_chanstate *cs; 517 u_char reg, val; 518 { 519 struct zs_channel *zsc = (struct zs_channel *)cs; 520 521 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 522 ZS_DELAY(); 523 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 524 ZS_DELAY(); 525 } 526 527 u_char zs_read_csr(cs) 528 struct zs_chanstate *cs; 529 { 530 struct zs_channel *zsc = (struct zs_channel *)cs; 531 register u_char val; 532 533 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 534 ZS_DELAY(); 535 return val; 536 } 537 538 void zs_write_csr(cs, val) 539 struct zs_chanstate *cs; 540 u_char val; 541 { 542 struct zs_channel *zsc = (struct zs_channel *)cs; 543 544 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 545 ZS_DELAY(); 546 } 547 548 u_char zs_read_data(cs) 549 struct zs_chanstate *cs; 550 { 551 struct zs_channel *zsc = (struct zs_channel *)cs; 552 register u_char val; 553 554 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 555 ZS_DELAY(); 556 return val; 557 } 558 559 void zs_write_data(cs, val) 560 struct zs_chanstate *cs; 561 u_char val; 562 { 563 struct zs_channel *zsc = (struct zs_channel *)cs; 564 565 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 566 ZS_DELAY(); 567 } 568 569 void 570 zs_abort(cs) 571 struct zs_chanstate *cs; 572 { 573 #ifdef DDB 574 Debugger(); 575 #endif 576 } 577 578 579 /*********************************************************/ 580 /* Polled character I/O functions for console and KGDB */ 581 /*********************************************************/ 582 583 struct zschan * 584 zs_get_chan_addr(zs_unit, channel) 585 int zs_unit, channel; 586 { 587 struct zsdevice *addr; 588 struct zschan *zc; 589 590 if (zs_unit >= NZS) 591 return NULL; 592 593 addr = (struct zsdevice *) ZS0_ADDR; 594 595 if (channel == 0) { 596 zc = &addr->zs_chan_a; 597 } else { 598 zc = &addr->zs_chan_b; 599 } 600 return (zc); 601 } 602 603 int 604 zs_getc(arg) 605 void *arg; 606 { 607 register volatile struct zschan *zc = arg; 608 register int s, c, rr0; 609 610 s = splhigh(); 611 /* Wait for a character to arrive. */ 612 do { 613 rr0 = zc->zc_csr; 614 ZS_DELAY(); 615 } while ((rr0 & ZSRR0_RX_READY) == 0); 616 617 c = zc->zc_data; 618 ZS_DELAY(); 619 splx(s); 620 621 return (c); 622 } 623 624 /* 625 * Polled output char. 626 */ 627 void 628 zs_putc(arg, c) 629 void *arg; 630 int c; 631 { 632 register volatile struct zschan *zc = arg; 633 register int s, rr0; 634 635 s = splhigh(); 636 /* Wait for transmitter to become ready. */ 637 do { 638 rr0 = zc->zc_csr; 639 ZS_DELAY(); 640 } while ((rr0 & ZSRR0_TX_READY) == 0); 641 642 zc->zc_data = c; 643 wbflush(); 644 ZS_DELAY(); 645 splx(s); 646 } 647 648 /***************************************************************/ 649 650 static void zscnprobe __P((struct consdev *)); 651 static void zscninit __P((struct consdev *)); 652 static int zscngetc __P((dev_t)); 653 static void zscnputc __P((dev_t, int)); 654 static void zscnpollc __P((dev_t, int)); 655 656 static int cons_port; 657 658 struct consdev consdev_zs = { 659 zscnprobe, 660 zscninit, 661 zscngetc, 662 zscnputc, 663 zscnpollc 664 }; 665 666 void 667 zscnprobe(cn) 668 struct consdev *cn; 669 { 670 } 671 672 void 673 zscninit(cn) 674 struct consdev *cn; 675 { 676 cons_port = prom_getconsole(); 677 cn->cn_dev = makedev(zs_major, cons_port); 678 cn->cn_pri = CN_REMOTE; 679 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 680 } 681 682 int 683 zscngetc(dev) 684 dev_t dev; 685 { 686 struct zschan *zs; 687 688 zs = zs_get_chan_addr(0, cons_port); 689 return zs_getc(zs); 690 } 691 692 void 693 zscnputc(dev, c) 694 dev_t dev; 695 int c; 696 { 697 struct zschan *zs; 698 699 zs = zs_get_chan_addr(0, cons_port); 700 zs_putc(zs, c); 701 } 702 703 void 704 zscnpollc(dev, on) 705 dev_t dev; 706 int on; 707 { 708 } 709
Indexes created Tue Sep 30 17:09:57 GMT 2025