zs.c revision 1.9
1 /* $NetBSD: zs.c,v 1.9 2001/03/30 23:28:00 wdk Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross and Wayne Knowles 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Zilog Z8530 Dual UART driver (machine-dependent part) 41 * 42 * Runs two serial lines per chip using slave drivers. 43 * Plain tty/async lines use the zs_async slave. 44 */ 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/conf.h> 51 #include <sys/device.h> 52 #include <sys/file.h> 53 #include <sys/ioctl.h> 54 #include <sys/kernel.h> 55 #include <sys/proc.h> 56 #include <sys/tty.h> 57 #include <sys/time.h> 58 #include <sys/syslog.h> 59 60 #include <machine/cpu.h> 61 #include <machine/mainboard.h> 62 #include <machine/autoconf.h> 63 #include <machine/prom.h> 64 #include <machine/z8530var.h> 65 66 #include <dev/cons.h> 67 #include <dev/ic/z8530reg.h> 68 69 #include "zsc.h" /* NZSC */ 70 #define NZS NZSC 71 72 /* Make life easier for the initialized arrays here. */ 73 #if NZS < 2 74 #undef NZS 75 #define NZS 2 76 #endif 77 78 /* 79 * Some warts needed by z8530tty.c - 80 * The default parity REALLY needs to be the same as the PROM uses, 81 * or you can not see messages done with printf during boot-up... 82 */ 83 int zs_def_cflag = (CREAD | CS8 | HUPCL); 84 int zs_major = 1; 85 86 87 #define PCLK 10000000 /* PCLK pin input clock rate */ 88 89 #ifndef ZS_DEFSPEED 90 #define ZS_DEFSPEED 9600 91 #endif 92 93 /* 94 * Define interrupt levels. 95 */ 96 #define ZSHARD_PRI 64 97 98 /* Register recovery time is 3.5 to 4 PCLK Cycles */ 99 #define ZS_RECOVERY 1 /* 1us = 10 PCLK Cycles */ 100 #define ZS_DELAY() delay(ZS_RECOVERY) 101 102 /* The layout of this is hardware-dependent (padding, order). */ 103 struct zschan { 104 u_char pad1[3]; 105 volatile u_char zc_csr; /* ctrl,status, and indirect access */ 106 u_char pad2[3]; 107 volatile u_char zc_data; /* data */ 108 }; 109 struct zsdevice { 110 /* Yes, they are backwards. */ 111 struct zschan zs_chan_b; 112 struct zschan zs_chan_a; 113 }; 114 115 /* Return the byte offset of element within a structure */ 116 #define OFFSET(struct_def, el) ((size_t)&((struct_def *)0)->el) 117 118 #define ZS_CHAN_A OFFSET(struct zsdevice, zs_chan_a) 119 #define ZS_CHAN_B OFFSET(struct zsdevice, zs_chan_b) 120 #define ZS_REG_CSR OFFSET(struct zschan, zc_csr) 121 #define ZS_REG_DATA OFFSET(struct zschan, zc_data) 122 static int zs_chan_offset[] = {ZS_CHAN_A, ZS_CHAN_B}; 123 124 /* Flags from cninit() */ 125 static int zs_hwflags[NZS][2]; 126 127 /* Default speed for all channels */ 128 static int zs_defspeed = ZS_DEFSPEED; 129 static volatile int zssoftpending; 130 131 static u_char zs_init_reg[16] = { 132 0, /* 0: CMD (reset, etc.) */ 133 0, /* 1: No interrupts yet. */ 134 ZSHARD_PRI, /* 2: IVECT */ 135 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 136 ZSWR4_CLK_X16 | ZSWR4_ONESB, 137 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 138 0, /* 6: TXSYNC/SYNCLO */ 139 0, /* 7: RXSYNC/SYNCHI */ 140 0, /* 8: alias for data port */ 141 ZSWR9_MASTER_IE, 142 0, /*10: Misc. TX/RX control bits */ 143 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD | ZSWR11_TRXC_OUT_ENA, 144 BPS_TO_TCONST(PCLK/16, ZS_DEFSPEED), /*12: BAUDLO (default=9600) */ 145 0, /*13: BAUDHI (default=9600) */ 146 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 147 ZSWR15_BREAK_IE, 148 }; 149 150 151 /**************************************************************** 152 * Autoconfig 153 ****************************************************************/ 154 155 /* Definition of the driver for autoconfig. */ 156 static int zs_match __P((struct device *, struct cfdata *, void *)); 157 static void zs_attach __P((struct device *, struct device *, void *)); 158 static int zs_print __P((void *, const char *name)); 159 160 struct cfattach zsc_ca = { 161 sizeof(struct zsc_softc), zs_match, zs_attach 162 }; 163 164 extern struct cfdriver zsc_cd; 165 166 static int zshard __P((void *)); 167 void zssoft __P((void *)); 168 static int zs_get_speed __P((struct zs_chanstate *)); 169 struct zschan *zs_get_chan_addr (int zs_unit, int channel); 170 int zs_getc __P((void *)); 171 void zs_putc __P((void *, int)); 172 173 /* 174 * Is the zs chip present? 175 */ 176 static int 177 zs_match(parent, cf, aux) 178 struct device *parent; 179 struct cfdata *cf; 180 void *aux; 181 { 182 struct confargs *ca = aux; 183 void *va; 184 185 if (strcmp(ca->ca_name, "zsc")) 186 return 0; 187 188 va = (void *)cf->cf_addr; 189 190 /* This returns -1 on a fault (bus error). */ 191 if (badaddr(va, 1)) 192 return 0; 193 return 1; 194 } 195 196 /* 197 * Attach a found zs. 198 * 199 * Match slave number to zs unit number, so that misconfiguration will 200 * not set up the keyboard as ttya, etc. 201 */ 202 static void 203 zs_attach(parent, self, aux) 204 struct device *parent; 205 struct device *self; 206 void *aux; 207 { 208 struct zsc_softc *zsc = (void *) self; 209 struct confargs *ca = aux; 210 struct zsc_attach_args zsc_args; 211 struct zs_chanstate *cs; 212 struct zs_channel *ch; 213 int zs_unit, channel, s; 214 215 zsc->zsc_bustag = ca->ca_bustag; 216 if (bus_space_map(ca->ca_bustag, ca->ca_addr, 217 sizeof(struct zsdevice), 218 BUS_SPACE_MAP_LINEAR, 219 &zsc->zsc_base) != 0) { 220 printf(": cannot map registers\n"); 221 return; 222 } 223 224 zs_unit = zsc->zsc_dev.dv_unit; 225 printf("\n"); 226 227 /* 228 * Initialize software state for each channel. 229 */ 230 for (channel = 0; channel < 2; channel++) { 231 zsc_args.channel = channel; 232 zsc_args.hwflags = zs_hwflags[zs_unit][channel]; 233 ch = &zsc->zsc_cs_store[channel]; 234 cs = zsc->zsc_cs[channel] = (struct zs_chanstate *)ch; 235 236 cs->cs_reg_csr = NULL; 237 cs->cs_reg_data = NULL; 238 cs->cs_channel = channel; 239 cs->cs_private = NULL; 240 cs->cs_ops = &zsops_null; 241 cs->cs_brg_clk = PCLK / 16; 242 243 if (bus_space_subregion(ca->ca_bustag, zsc->zsc_base, 244 zs_chan_offset[channel], 245 sizeof(struct zschan), 246 &ch->cs_regs) != 0) { 247 printf(": cannot map regs\n"); 248 return; 249 } 250 ch->cs_bustag = ca->ca_bustag; 251 252 bcopy(zs_init_reg, cs->cs_creg, 16); 253 bcopy(zs_init_reg, cs->cs_preg, 16); 254 255 if (zsc_args.hwflags & ZS_HWFLAG_CONSOLE) 256 cs->cs_defspeed = zs_get_speed(cs); 257 else 258 cs->cs_defspeed = zs_defspeed; 259 cs->cs_defcflag = zs_def_cflag; 260 261 /* Make these correspond to cs_defcflag (-crtscts) */ 262 cs->cs_rr0_dcd = ZSRR0_DCD; 263 cs->cs_rr0_cts = 0; 264 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 265 cs->cs_wr5_rts = 0; 266 267 /* 268 * Clear the master interrupt enable. 269 * The INTENA is common to both channels, 270 * so just do it on the A channel. 271 */ 272 if (channel == 0) { 273 zs_write_reg(cs, 9, 0); 274 } 275 /* 276 * Look for a child driver for this channel. 277 * The child attach will setup the hardware. 278 */ 279 if (!config_found(self, (void *)&zsc_args, zs_print)) { 280 /* No sub-driver. Just reset it. */ 281 u_char reset = (channel == 0) ? 282 ZSWR9_A_RESET : ZSWR9_B_RESET; 283 284 s = splhigh(); 285 zs_write_reg(cs, 9, reset); 286 splx(s); 287 } 288 } 289 290 291 zsc->sc_si = softintr_establish(IPL_SOFTSERIAL, zssoft, zsc); 292 bus_intr_establish(zsc->zsc_bustag, SYS_INTR_SCC0, 0, 0, zshard, NULL); 293 294 evcnt_attach_dynamic(&zsc->zs_intrcnt, EVCNT_TYPE_INTR, NULL, 295 self->dv_xname, "intr"); 296 297 /* 298 * Set the master interrupt enable and interrupt vector. 299 * (common to both channels, do it on A) 300 */ 301 cs = zsc->zsc_cs[0]; 302 s = splhigh(); 303 /* interrupt vector */ 304 zs_write_reg(cs, 2, zs_init_reg[2]); 305 /* master interrupt control (enable) */ 306 zs_write_reg(cs, 9, zs_init_reg[9]); 307 splx(s); 308 } 309 310 static int 311 zs_print(aux, name) 312 void *aux; 313 const char *name; 314 { 315 struct zsc_attach_args *args = aux; 316 317 if (name != NULL) 318 printf("%s: ", name); 319 320 if (args->channel != -1) 321 printf(" channel %d", args->channel); 322 323 return UNCONF; 324 } 325 326 /* 327 * Our ZS chips all share a common, autovectored interrupt, 328 * so we have to look at all of them on each interrupt. 329 */ 330 static int 331 zshard(arg) 332 void *arg; 333 { 334 register struct zsc_softc *zsc; 335 register int unit, rval, softreq; 336 337 rval = 0; 338 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 339 zsc = zsc_cd.cd_devs[unit]; 340 if (zsc == NULL) 341 continue; 342 rval |= zsc_intr_hard(zsc); 343 softreq = zsc->zsc_cs[0]->cs_softreq; 344 softreq |= zsc->zsc_cs[1]->cs_softreq; 345 if (softreq && (zssoftpending == 0)) { 346 zssoftpending = 1; 347 softintr_schedule(zsc->sc_si); 348 } 349 zsc->zs_intrcnt.ev_count++; 350 } 351 return 0; 352 } 353 354 /* 355 * Similar scheme as for zshard (look at all of them) 356 */ 357 void 358 zssoft(arg) 359 void *arg; 360 { 361 register struct zsc_softc *zsc; 362 register int s, unit; 363 364 /* This is not the only ISR on this IPL. */ 365 if (zssoftpending == 0) 366 return; 367 368 /* 369 * The soft intr. bit will be set by zshard only if 370 * the variable zssoftpending is zero. The order of 371 * these next two statements prevents our clearing 372 * the soft intr bit just after zshard has set it. 373 */ 374 /*isr_soft_clear(ZSSOFT_PRI);*/ 375 zssoftpending = 0; 376 377 /* Make sure we call the tty layer at spltty. */ 378 s = spltty(); 379 for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) { 380 zsc = zsc_cd.cd_devs[unit]; 381 if (zsc == NULL) 382 continue; 383 (void) zsc_intr_soft(zsc); 384 } 385 splx(s); 386 return; 387 } 388 389 390 /* 391 * Compute the current baud rate given a ZS channel. 392 */ 393 static int 394 zs_get_speed(cs) 395 struct zs_chanstate *cs; 396 { 397 int tconst; 398 399 tconst = zs_read_reg(cs, 12); 400 tconst |= zs_read_reg(cs, 13) << 8; 401 return (TCONST_TO_BPS(cs->cs_brg_clk, tconst)); 402 } 403 404 /* 405 * MD functions for setting the baud rate and control modes. 406 */ 407 int 408 zs_set_speed(cs, bps) 409 struct zs_chanstate *cs; 410 int bps; /* bits per second */ 411 { 412 int tconst, real_bps; 413 414 #if 1 415 while (!(zs_read_csr(cs) & ZSRR0_TX_READY)) 416 {/*nop*/} 417 #endif 418 /* Wait for transmit buffer to empty */ 419 if (bps == 0) { 420 return (0); 421 } 422 423 #ifdef DIAGNOSTIC 424 if (cs->cs_brg_clk == 0) 425 panic("zs_set_speed"); 426 #endif 427 428 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 429 if (tconst < 0) 430 return (EINVAL); 431 432 /* Convert back to make sure we can do it. */ 433 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 434 435 /* XXX - Allow some tolerance here? */ 436 #if 0 437 if (real_bps != bps) 438 return (EINVAL); 439 #endif 440 441 cs->cs_preg[12] = tconst; 442 cs->cs_preg[13] = tconst >> 8; 443 444 /* Caller will stuff the pending registers. */ 445 return (0); 446 } 447 448 int 449 zs_set_modes(cs, cflag) 450 struct zs_chanstate *cs; 451 int cflag; /* bits per second */ 452 { 453 int s; 454 455 /* 456 * Output hardware flow control on the chip is horrendous: 457 * if carrier detect drops, the receiver is disabled, and if 458 * CTS drops, the transmitter is stoped IN MID CHARACTER! 459 * Therefore, NEVER set the HFC bit, and instead use the 460 * status interrupt to detect CTS changes. 461 */ 462 s = splzs(); 463 cs->cs_rr0_pps = 0; 464 if ((cflag & (CLOCAL | MDMBUF)) != 0) { 465 cs->cs_rr0_dcd = 0; 466 if ((cflag & MDMBUF) == 0) 467 cs->cs_rr0_pps = ZSRR0_DCD; 468 } else 469 cs->cs_rr0_dcd = ZSRR0_DCD; 470 if ((cflag & CRTSCTS) != 0) { 471 cs->cs_wr5_dtr = ZSWR5_DTR; 472 cs->cs_wr5_rts = ZSWR5_RTS; 473 cs->cs_rr0_cts = ZSRR0_CTS; 474 } else if ((cflag & MDMBUF) != 0) { 475 cs->cs_wr5_dtr = 0; 476 cs->cs_wr5_rts = ZSWR5_DTR; 477 cs->cs_rr0_cts = ZSRR0_DCD; 478 } else { 479 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 480 cs->cs_wr5_rts = 0; 481 cs->cs_rr0_cts = 0; 482 } 483 splx(s); 484 485 /* Caller will stuff the pending registers. */ 486 return (0); 487 } 488 489 490 /* 491 * Read or write the chip with suitable delays. 492 */ 493 494 u_char 495 zs_read_reg(cs, reg) 496 struct zs_chanstate *cs; 497 u_char reg; 498 { 499 u_char val; 500 struct zs_channel *zsc = (struct zs_channel *)cs; 501 502 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 503 ZS_DELAY(); 504 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 505 ZS_DELAY(); 506 return val; 507 } 508 509 void 510 zs_write_reg(cs, reg, val) 511 struct zs_chanstate *cs; 512 u_char reg, val; 513 { 514 struct zs_channel *zsc = (struct zs_channel *)cs; 515 516 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, reg); 517 ZS_DELAY(); 518 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 519 ZS_DELAY(); 520 } 521 522 u_char zs_read_csr(cs) 523 struct zs_chanstate *cs; 524 { 525 struct zs_channel *zsc = (struct zs_channel *)cs; 526 register u_char val; 527 528 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR); 529 ZS_DELAY(); 530 return val; 531 } 532 533 void zs_write_csr(cs, val) 534 struct zs_chanstate *cs; 535 u_char val; 536 { 537 struct zs_channel *zsc = (struct zs_channel *)cs; 538 539 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_CSR, val); 540 ZS_DELAY(); 541 } 542 543 u_char zs_read_data(cs) 544 struct zs_chanstate *cs; 545 { 546 struct zs_channel *zsc = (struct zs_channel *)cs; 547 register u_char val; 548 549 val = bus_space_read_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA); 550 ZS_DELAY(); 551 return val; 552 } 553 554 void zs_write_data(cs, val) 555 struct zs_chanstate *cs; 556 u_char val; 557 { 558 struct zs_channel *zsc = (struct zs_channel *)cs; 559 560 bus_space_write_1(zsc->cs_bustag, zsc->cs_regs, ZS_REG_DATA, val); 561 ZS_DELAY(); 562 } 563 564 void 565 zs_abort(cs) 566 struct zs_chanstate *cs; 567 { 568 #ifdef DDB 569 Debugger(); 570 #endif 571 } 572 573 574 /*********************************************************/ 575 /* Polled character I/O functions for console and KGDB */ 576 /*********************************************************/ 577 578 struct zschan * 579 zs_get_chan_addr(zs_unit, channel) 580 int zs_unit, channel; 581 { 582 struct zsdevice *addr; 583 struct zschan *zc; 584 585 if (zs_unit >= NZS) 586 return NULL; 587 588 addr = (struct zsdevice *) ZS0_ADDR; 589 590 if (channel == 0) { 591 zc = &addr->zs_chan_a; 592 } else { 593 zc = &addr->zs_chan_b; 594 } 595 return (zc); 596 } 597 598 int 599 zs_getc(arg) 600 void *arg; 601 { 602 register volatile struct zschan *zc = arg; 603 register int s, c, rr0; 604 605 s = splhigh(); 606 /* Wait for a character to arrive. */ 607 do { 608 rr0 = zc->zc_csr; 609 ZS_DELAY(); 610 } while ((rr0 & ZSRR0_RX_READY) == 0); 611 612 c = zc->zc_data; 613 ZS_DELAY(); 614 splx(s); 615 616 return (c); 617 } 618 619 /* 620 * Polled output char. 621 */ 622 void 623 zs_putc(arg, c) 624 void *arg; 625 int c; 626 { 627 register volatile struct zschan *zc = arg; 628 register int s, rr0; 629 630 s = splhigh(); 631 /* Wait for transmitter to become ready. */ 632 do { 633 rr0 = zc->zc_csr; 634 ZS_DELAY(); 635 } while ((rr0 & ZSRR0_TX_READY) == 0); 636 637 zc->zc_data = c; 638 wbflush(); 639 ZS_DELAY(); 640 splx(s); 641 } 642 643 /***************************************************************/ 644 645 static void zscnprobe __P((struct consdev *)); 646 static void zscninit __P((struct consdev *)); 647 static int zscngetc __P((dev_t)); 648 static void zscnputc __P((dev_t, int)); 649 static void zscnpollc __P((dev_t, int)); 650 651 static int cons_port; 652 653 struct consdev consdev_zs = { 654 zscnprobe, 655 zscninit, 656 zscngetc, 657 zscnputc, 658 zscnpollc 659 }; 660 661 void 662 zscnprobe(cn) 663 struct consdev *cn; 664 { 665 } 666 667 void 668 zscninit(cn) 669 struct consdev *cn; 670 { 671 cons_port = prom_getconsole(); 672 cn->cn_dev = makedev(zs_major, cons_port); 673 cn->cn_pri = CN_REMOTE; 674 zs_hwflags[0][cons_port] = ZS_HWFLAG_CONSOLE; 675 } 676 677 int 678 zscngetc(dev) 679 dev_t dev; 680 { 681 struct zschan *zs; 682 683 zs = zs_get_chan_addr(0, cons_port); 684 return zs_getc(zs); 685 } 686 687 void 688 zscnputc(dev, c) 689 dev_t dev; 690 int c; 691 { 692 struct zschan *zs; 693 694 zs = zs_get_chan_addr(0, cons_port); 695 zs_putc(zs, c); 696 } 697 698 void 699 zscnpollc(dev, on) 700 dev_t dev; 701 int on; 702 { 703 } 704
Indexes created Tue Sep 30 11:09:46 GMT 2025