wdc_mainbus.c revision 1.4
1 /* $NetBSD: wdc_mainbus.c,v 1.4 2012/07/31 15:50:33 bouyer Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: wdc_mainbus.c,v 1.4 2012/07/31 15:50:33 bouyer Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/errno.h> 36 37 #include <machine/autoconf.h> 38 #include <machine/intr.h> 39 #include <machine/mmeye.h> 40 41 #include <dev/ic/wdcreg.h> 42 #include <dev/ata/atavar.h> 43 #include <dev/ic/wdcvar.h> 44 45 #include "locators.h" 46 47 #define WDC_MAINBUS_REG_NPORTS 8 48 #define WDC_MAINBUS_AUXREG_OFFSET 0x206 49 #define WDC_MAINBUS_AUXREG_NPORTS 1 50 51 /* options passed via the 'flags' config keyword */ 52 #define WDC_OPTIONS_32 0x01 /* try to use 32bit data I/O */ 53 #define WDC_OPTIONS_ATA_NOSTREAM 0x04 54 #define WDC_OPTIONS_ATAPI_NOSTREAM 0x08 55 56 struct wdc_mainbus_softc { 57 struct wdc_softc sc_wdcdev; 58 struct ata_channel *wdc_chanlist[1]; 59 struct ata_channel ata_channel; 60 struct ata_queue wdc_chqueue; 61 struct wdc_regs wdc_regs; 62 }; 63 64 static int wdc_mainbus_match(device_t, cfdata_t, void *); 65 static void wdc_mainbus_attach(device_t, device_t, void *); 66 67 CFATTACH_DECL_NEW(wdc_mainbus, sizeof(struct wdc_mainbus_softc), 68 wdc_mainbus_match, wdc_mainbus_attach, NULL, NULL); 69 70 static int 71 wdc_mainbus_match(device_t parent, cfdata_t match, void *aux) 72 { 73 struct mainbus_attach_args *ma = aux; 74 struct ata_channel ch; 75 struct wdc_softc wdc; 76 struct wdc_regs wdr; 77 int result = 0, i; 78 79 if (strcmp(ma->ma_name, match->cf_name) != 0) 80 return 0; 81 82 /* Disallow wildcarded values. */ 83 if (ma->ma_addr1 == MAINBUSCF_ADDR1_DEFAULT || 84 ma->ma_irq1 == MAINBUSCF_IRQ1_DEFAULT) 85 return 0; 86 87 memset(&wdc, 0, sizeof(wdc)); 88 memset(&ch, 0, sizeof(ch)); 89 ch.ch_atac = &wdc.sc_atac; 90 wdc.regs = &wdr; 91 92 wdr.cmd_iot = SH3_BUS_SPACE_PCMCIA_IO; 93 if (bus_space_map(wdr.cmd_iot, ma->ma_addr1, 94 WDC_MAINBUS_REG_NPORTS, 0, &wdr.cmd_baseioh) != 0) 95 goto out; 96 97 for (i = 0; i < WDC_MAINBUS_REG_NPORTS; i++) { 98 if (bus_space_subregion(wdr.cmd_iot, wdr.cmd_baseioh, i, 99 i == 0 ? 4 : 1, &wdr.cmd_iohs[i]) != 0) 100 goto outunmap; 101 } 102 wdc_init_shadow_regs(&ch); 103 104 wdr.ctl_iot = SH3_BUS_SPACE_PCMCIA_IO; 105 if (bus_space_map(wdr.ctl_iot, ma->ma_addr1 + WDC_MAINBUS_AUXREG_OFFSET, 106 WDC_MAINBUS_AUXREG_NPORTS, 0, &wdr.ctl_ioh) != 0) 107 goto outunmap; 108 109 #if 0 110 bus_space_write_1(iot, ioh, 0x200, 0x80); 111 delay(1000); 112 bus_space_write_1(iot, ioh, 0x200, 0x00); 113 delay(1000); 114 printf("CF COR=0x%x\n", bus_space_read_1(iot, ioh, 0x200)); 115 bus_space_write_1(iot, ioh, 0x200, 0x41); 116 printf("CF COR=0x%x\n", bus_space_read_1(iot, ioh, 0x200)); 117 delay(1000000); 118 #endif 119 result = wdcprobe(&ch); 120 121 bus_space_unmap(wdr.ctl_iot, wdr.ctl_ioh, WDC_MAINBUS_AUXREG_NPORTS); 122 outunmap: 123 bus_space_unmap(wdr.cmd_iot, wdr.cmd_baseioh, WDC_MAINBUS_REG_NPORTS); 124 out: 125 return result; 126 } 127 128 static void 129 wdc_mainbus_attach(device_t parent, device_t self, void *aux) 130 { 131 struct wdc_mainbus_softc *sc = device_private(self); 132 struct mainbus_attach_args *ma = aux; 133 struct wdc_regs *wdr; 134 int wdc_cf_flags = device_cfdata(self)->cf_flags; 135 int i; 136 137 sc->sc_wdcdev.sc_atac.atac_dev = self; 138 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs; 139 wdr->cmd_iot = SH3_BUS_SPACE_PCMCIA_IO; 140 wdr->ctl_iot = SH3_BUS_SPACE_PCMCIA_IO; 141 if (bus_space_map(wdr->cmd_iot, ma->ma_addr1, 142 WDC_MAINBUS_REG_NPORTS, 0, &wdr->cmd_baseioh) || 143 bus_space_map(wdr->ctl_iot, 144 ma->ma_addr1 + WDC_MAINBUS_AUXREG_OFFSET, 145 WDC_MAINBUS_AUXREG_NPORTS, 0, &wdr->ctl_ioh)) { 146 aprint_error(": couldn't map registers\n"); 147 return; 148 } 149 for (i = 0; i < WDC_MAINBUS_REG_NPORTS; i++) { 150 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 151 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 152 aprint_error(": couldn't subregion registers (3)\n"); 153 return; 154 } 155 } 156 157 wdr->data32iot = wdr->cmd_iot; 158 wdr->data32ioh = wdr->cmd_iohs[0]; 159 160 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA; 161 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 162 if (wdc_cf_flags & WDC_OPTIONS_32) 163 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32; 164 if (wdc_cf_flags & WDC_OPTIONS_ATA_NOSTREAM) 165 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATA_NOSTREAM; 166 if (wdc_cf_flags & WDC_OPTIONS_ATAPI_NOSTREAM) 167 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_ATAPI_NOSTREAM; 168 169 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 170 sc->wdc_chanlist[0] = &sc->ata_channel; 171 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist; 172 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 173 sc->sc_wdcdev.wdc_maxdrives = 2; 174 sc->ata_channel.ch_channel = 0; 175 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 176 sc->ata_channel.ch_queue = &sc->wdc_chqueue; 177 wdc_init_shadow_regs(&sc->ata_channel); 178 179 aprint_normal("\n"); 180 181 mmeye_intr_establish(ma->ma_irq1, IST_LEVEL, IPL_BIO, 182 wdcintr, &sc->ata_channel); 183 184 wdcattach(&sc->ata_channel); 185 } 186
Indexes created Thu Oct 02 10:09:58 GMT 2025