wdc.c revision 1.3
1 /* $NetBSD: wdc.c,v 1.3 2019/01/08 17:15:31 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Manuel Bouyer. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/disklabel.h> 35 #include <sys/bootblock.h> 36 37 #include <lib/libsa/stand.h> 38 #include <lib/libkern/libkern.h> 39 #include <machine/param.h> 40 41 #include "boot.h" 42 #include "wdvar.h" 43 44 #if defined(SH3) 45 #define MMEYE_WDC0_IOBASE 0xb6000000 46 #define MMEYE_WDC1_IOBASE 0xb7000000 47 #elif defined(SH4) 48 #define MMEYE_WDC0_IOBASE 0xb6000000 49 #define MMEYE_WDC1_IOBASE 0xb7000000 50 #endif 51 #define MMEYE_WDC_CTLBASE 0x206 52 53 #define WDCDELAY 100 54 #define WDCNDELAY_RST 31000 * 10 55 56 static int wdcprobe(struct wdc_channel *chp); 57 static int wdc_wait_for_ready(struct wdc_channel *chp); 58 static int wdc_read_block(struct wd_softc *sc, struct wdc_command *wd_c); 59 static int __wdcwait_reset(struct wdc_channel *chp, int drv_mask); 60 61 /* 62 * Reset the controller. 63 */ 64 static int 65 __wdcwait_reset(struct wdc_channel *chp, int drv_mask) 66 { 67 int timeout; 68 uint8_t st0, st1; 69 70 /* wait for BSY to deassert */ 71 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) { 72 WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM); /* master */ 73 delay(10); 74 st0 = WDC_READ_REG(chp, wd_status); 75 WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM | 0x10); /* slave */ 76 delay(10); 77 st1 = WDC_READ_REG(chp, wd_status); 78 79 if ((drv_mask & 0x01) == 0) { 80 /* no master */ 81 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 82 /* No master, slave is ready, it's done */ 83 goto end; 84 } 85 } else if ((drv_mask & 0x02) == 0) { 86 /* no slave */ 87 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 88 /* No slave, master is ready, it's done */ 89 goto end; 90 } 91 } else { 92 /* Wait for both master and slave to be ready */ 93 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 94 goto end; 95 } 96 } 97 98 delay(WDCDELAY); 99 } 100 101 /* Reset timed out. Maybe it's because drv_mask was not right */ 102 if (st0 & WDCS_BSY) 103 drv_mask &= ~0x01; 104 if (st1 & WDCS_BSY) 105 drv_mask &= ~0x02; 106 107 end: 108 return drv_mask; 109 } 110 111 /* Test to see controller with at last one attached drive is there. 112 * Returns a bit for each possible drive found (0x01 for drive 0, 113 * 0x02 for drive 1). 114 * Logic: 115 * - If a status register is at 0xff, assume there is no drive here 116 * (ISA has pull-up resistors). Similarly if the status register has 117 * the value we last wrote to the bus (for IDE interfaces without pullups). 118 * If no drive at all -> return. 119 * - reset the controller, wait for it to complete (may take up to 31s !). 120 * If timeout -> return. 121 */ 122 static int 123 wdcprobe(struct wdc_channel *chp) 124 { 125 uint8_t st0, st1; 126 uint8_t ret_value = 0x03; 127 uint8_t drive; 128 129 /* 130 * Sanity check to see if the wdc channel responds at all. 131 */ 132 WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM); 133 delay(10); 134 st0 = WDC_READ_REG(chp, wd_status); 135 WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM | 0x10); 136 delay(10); 137 st1 = WDC_READ_REG(chp, wd_status); 138 139 if (st0 == 0xff || st0 == WDSD_IBM) 140 ret_value &= ~0x01; 141 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 142 ret_value &= ~0x02; 143 if (ret_value == 0) 144 return ENXIO; 145 146 /* assert SRST, wait for reset to complete */ 147 WDC_WRITE_REG(chp, wd_sdh, WDSD_IBM); 148 delay(10); 149 WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_RST | WDCTL_IDS); 150 delay(1000); 151 WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_IDS); 152 delay(1000); 153 (void) WDC_READ_REG(chp, wd_error); 154 WDC_WRITE_CTLREG(chp, wd_aux_ctlr, WDCTL_4BIT); 155 delay(10); 156 157 ret_value = __wdcwait_reset(chp, ret_value); 158 159 /* if reset failed, there's nothing here */ 160 if (ret_value == 0) 161 return ENXIO; 162 163 /* 164 * Test presence of drives. First test register signatures looking for 165 * ATAPI devices. If it's not an ATAPI and reset said there may be 166 * something here assume it's ATA or OLD. Ghost will be killed later in 167 * attach routine. 168 */ 169 for (drive = 0; drive < 2; drive++) { 170 if ((ret_value & (0x01 << drive)) == 0) 171 continue; 172 return 0; 173 } 174 return ENXIO; 175 } 176 177 /* 178 * Initialize the device. 179 */ 180 int 181 wdc_init(struct wd_softc *sc, u_int *unit) 182 { 183 struct wdc_channel *chp = &sc->sc_channel; 184 uint32_t cmdreg, ctlreg; 185 int i; 186 187 /* XXXX: Shuld reset CF COR here? */ 188 189 switch (*unit) { 190 case 0: cmdreg = MMEYE_WDC0_IOBASE; break; 191 case 1: cmdreg = MMEYE_WDC1_IOBASE; break; 192 193 default: 194 return ENXIO; 195 } 196 ctlreg = cmdreg + MMEYE_WDC_CTLBASE; 197 198 /* set up cmd registers */ 199 chp->c_cmdbase = (uint8_t *)cmdreg; 200 chp->c_data = (uint16_t *)(cmdreg + wd_data); 201 for (i = 0; i < WDC_NPORTS; i++) 202 chp->c_cmdreg[i] = chp->c_cmdbase + i; 203 /* set up shadow registers */ 204 chp->c_cmdreg[wd_status] = chp->c_cmdreg[wd_command]; 205 chp->c_cmdreg[wd_features] = chp->c_cmdreg[wd_precomp]; 206 /* set up ctl registers */ 207 chp->c_ctlbase = (uint8_t *)ctlreg; 208 209 if (wdcprobe(&sc->sc_channel) != 0) 210 return ENXIO; 211 return 0; 212 } 213 214 /* 215 * Wait until the device is ready. 216 */ 217 int 218 wdc_wait_for_ready(struct wdc_channel *chp) 219 { 220 u_int timeout; 221 222 for (timeout = WDC_TIMEOUT; timeout > 0; --timeout) { 223 if ((WDC_READ_REG(chp, wd_status) & (WDCS_BSY | WDCS_DRDY)) 224 == WDCS_DRDY) 225 return 0; 226 delay(1); 227 } 228 return ENXIO; 229 } 230 231 /* 232 * Read one block off the device. 233 */ 234 int 235 wdc_read_block(struct wd_softc *sc, struct wdc_command *wd_c) 236 { 237 int i; 238 struct wdc_channel *chp = &sc->sc_channel; 239 uint16_t *ptr = (uint16_t *)wd_c->data; 240 241 if (ptr == NULL) 242 return 0; 243 244 if (wd_c->r_command == WDCC_IDENTIFY) 245 for (i = wd_c->bcount; i > 0; i -= sizeof(uint16_t)) 246 *ptr++ = WDC_READ_DATA(chp); 247 else 248 for (i = wd_c->bcount; i > 0; i -= sizeof(uint16_t)) 249 *ptr++ = WDC_READ_DATA_STREAM(chp); 250 251 return 0; 252 } 253 254 /* 255 * Send a command to the device (CHS and LBA addressing). 256 */ 257 int 258 wdccommand(struct wd_softc *sc, struct wdc_command *wd_c) 259 { 260 struct wdc_channel *chp = &sc->sc_channel; 261 262 #if 0 263 DPRINTF(("wdccommand(%d, %d, %d, %d, %d, %d, %d)\n", 264 wd_c->drive, wd_c->r_command, wd_c->r_cyl, 265 wd_c->r_head, wd_c->r_sector, wd_c->bcount, 266 wd_c->r_precomp)); 267 #endif 268 269 WDC_WRITE_REG(chp, wd_features, wd_c->r_features); 270 WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count); 271 WDC_WRITE_REG(chp, wd_sector, wd_c->r_sector); 272 WDC_WRITE_REG(chp, wd_cyl_lo, wd_c->r_cyl); 273 WDC_WRITE_REG(chp, wd_cyl_hi, wd_c->r_cyl >> 8); 274 WDC_WRITE_REG(chp, wd_sdh, 275 WDSD_IBM | (wd_c->drive << 4) | wd_c->r_head); 276 WDC_WRITE_REG(chp, wd_command, wd_c->r_command); 277 278 if (wdc_wait_for_ready(chp) != 0) 279 return ENXIO; 280 281 if (WDC_READ_REG(chp, wd_status) & WDCS_ERR) { 282 printf("wd%d: error %x\n", chp->compatchan, 283 WDC_READ_REG(chp, wd_error)); 284 return ENXIO; 285 } 286 287 return 0; 288 } 289 290 /* 291 * Send a command to the device (LBA48 addressing). 292 */ 293 int 294 wdccommandext(struct wd_softc *wd, struct wdc_command *wd_c) 295 { 296 struct wdc_channel *chp = &wd->sc_channel; 297 298 #if 0 299 DPRINTF(("%s(%d, %x, %" PRId64 ", %d)\n", __func__, 300 wd_c->drive, wd_c->r_command, 301 wd_c->r_blkno, wd_c->r_count)); 302 #endif 303 304 /* Select drive, head, and addressing mode. */ 305 WDC_WRITE_REG(chp, wd_sdh, (wd_c->drive << 4) | WDSD_LBA); 306 307 /* previous */ 308 WDC_WRITE_REG(chp, wd_features, 0); 309 WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count >> 8); 310 WDC_WRITE_REG(chp, wd_lba_hi, wd_c->r_blkno >> 40); 311 WDC_WRITE_REG(chp, wd_lba_mi, wd_c->r_blkno >> 32); 312 WDC_WRITE_REG(chp, wd_lba_lo, wd_c->r_blkno >> 24); 313 314 /* current */ 315 WDC_WRITE_REG(chp, wd_features, 0); 316 WDC_WRITE_REG(chp, wd_seccnt, wd_c->r_count); 317 WDC_WRITE_REG(chp, wd_lba_hi, wd_c->r_blkno >> 16); 318 WDC_WRITE_REG(chp, wd_lba_mi, wd_c->r_blkno >> 8); 319 WDC_WRITE_REG(chp, wd_lba_lo, wd_c->r_blkno); 320 321 /* Send command. */ 322 WDC_WRITE_REG(chp, wd_command, wd_c->r_command); 323 324 if (wdc_wait_for_ready(chp) != 0) 325 return ENXIO; 326 327 if (WDC_READ_REG(chp, wd_status) & WDCS_ERR) { 328 printf("wd%d: error %x\n", chp->compatchan, 329 WDC_READ_REG(chp, wd_error)); 330 return ENXIO; 331 } 332 333 return 0; 334 } 335 336 /* 337 * Issue 'device identify' command. 338 */ 339 int 340 wdc_exec_identify(struct wd_softc *wd, void *data) 341 { 342 int error; 343 struct wdc_command wd_c; 344 345 memset(&wd_c, 0, sizeof(wd_c)); 346 347 wd_c.drive = 0; 348 wd_c.r_command = WDCC_IDENTIFY; 349 wd_c.bcount = DEV_BSIZE; 350 wd_c.data = data; 351 352 if ((error = wdccommand(wd, &wd_c)) != 0) 353 return error; 354 355 return wdc_read_block(wd, &wd_c); 356 } 357 358 /* 359 * Issue 'read' command. 360 */ 361 int 362 wdc_exec_read(struct wd_softc *wd, uint8_t cmd, daddr_t blkno, void *data) 363 { 364 int error; 365 struct wdc_command wd_c; 366 bool lba, lba48; 367 368 memset(&wd_c, 0, sizeof(wd_c)); 369 lba = false; 370 lba48 = false; 371 372 wd_c.data = data; 373 wd_c.r_count = 1; 374 wd_c.r_features = 0; 375 wd_c.drive = 0; 376 wd_c.bcount = wd->sc_label.d_secsize; 377 378 if ((wd->sc_flags & WDF_LBA48) != 0 && blkno > wd->sc_capacity28) 379 lba48 = true; 380 else if ((wd->sc_flags & WDF_LBA) != 0) 381 lba = true; 382 383 if (lba48) { 384 /* LBA48 */ 385 wd_c.r_command = atacmd_to48(cmd); 386 wd_c.r_blkno = blkno; 387 } else if (lba) { 388 /* LBA */ 389 wd_c.r_command = cmd; 390 wd_c.r_sector = (blkno >> 0) & 0xff; 391 wd_c.r_cyl = (blkno >> 8) & 0xffff; 392 wd_c.r_head = (blkno >> 24) & 0x0f; 393 wd_c.r_head |= WDSD_LBA; 394 } else { 395 /* CHS */ 396 wd_c.r_command = cmd; 397 wd_c.r_sector = blkno % wd->sc_label.d_nsectors; 398 wd_c.r_sector++; /* Sectors begin with 1, not 0. */ 399 blkno /= wd->sc_label.d_nsectors; 400 wd_c.r_head = blkno % wd->sc_label.d_ntracks; 401 blkno /= wd->sc_label.d_ntracks; 402 wd_c.r_cyl = blkno; 403 wd_c.r_head |= WDSD_CHS; 404 } 405 406 if (lba48) 407 error = wdccommandext(wd, &wd_c); 408 else 409 error = wdccommand(wd, &wd_c); 410 411 if (error != 0) 412 return error; 413 414 return wdc_read_block(wd, &wd_c); 415 } 416
Indexes created Tue Oct 14 11:09:46 GMT 2025