lpt_pccreg.h revision 1.2.16.1
1 1.2.16.1 scw /* $NetBSD: lpt_pccreg.h,v 1.2.16.1 2000/03/11 20:51:49 scw Exp $ */ 2 1.2 scw 3 1.2 scw /*- 4 1.2 scw * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.2 scw * All rights reserved. 6 1.2 scw * 7 1.2 scw * This code is derived from software contributed to The NetBSD Foundation 8 1.2 scw * by Steve C. Woodford. 9 1.2 scw * 10 1.2 scw * Redistribution and use in source and binary forms, with or without 11 1.2 scw * modification, are permitted provided that the following conditions 12 1.2 scw * are met: 13 1.2 scw * 1. Redistributions of source code must retain the above copyright 14 1.2 scw * notice, this list of conditions and the following disclaimer. 15 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 scw * notice, this list of conditions and the following disclaimer in the 17 1.2 scw * documentation and/or other materials provided with the distribution. 18 1.2 scw * 3. All advertising materials mentioning features or use of this software 19 1.2 scw * must display the following acknowledgement: 20 1.2 scw * This product includes software developed by the NetBSD 21 1.2 scw * Foundation, Inc. and its contributors. 22 1.2 scw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.2 scw * contributors may be used to endorse or promote products derived 24 1.2 scw * from this software without specific prior written permission. 25 1.2 scw * 26 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.2 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.2 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.2 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.2 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.2 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.2 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.2 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.2 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.2 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.2 scw * POSSIBILITY OF SUCH DAMAGE. 37 1.2 scw */ 38 1.2 scw 39 1.2 scw /* 40 1.2 scw * MVME147 Parallel Port Register Definitions 41 1.2 scw */ 42 1.2.16.1 scw #ifndef _MVME68K_LPT_PCCREG_H 43 1.2.16.1 scw #define _MVME68K_LPT_PCCREG_H 44 1.2 scw 45 1.2 scw /* 46 1.2 scw * The mvme147's PCC chip has two status/control registers for the 47 1.2 scw * printer port: 48 1.2 scw * 49 1.2.16.1 scw * PCCREG_PRNT_INTR_CTRL Printer interrupt control register 50 1.2 scw * 0 - 2 Interrupt Level 51 1.2 scw * 3 Interrupt Enable 52 1.2 scw * 4 ACK Polarity. If set, falling edge of ACK generates 53 1.2 scw * the interrupt. If clear, rising edge of ACK generates 54 1.2 scw * the interrupt. 55 1.2 scw * 5 Indicates an ACK interrupt in progress. Cleared by 56 1.2 scw * writing a one, or disabling lpt interrupts. 57 1.2 scw * 6 Indicates a FAULT interrupt. Set on falling edge 58 1.2 scw * of printer's fault signal. Cleared by writing a one. 59 1.2 scw * 7 Printer Interrupt in progress. Basically just the 60 1.2 scw * logical OR of bits 5 and 6. 61 1.2 scw */ 62 1.2 scw #define LPI_ENABLE (1 << 3) 63 1.2 scw #define LPI_ACKPOL (1 << 4) 64 1.2 scw #define LPI_ACKINT (1 << 5) 65 1.2 scw #define LPI_FAULTINT (1 << 6) 66 1.2 scw #define LPI_INTERRUPT (1 << 7) 67 1.2 scw 68 1.2.16.1 scw 69 1.2 scw /* 70 1.2.16.1 scw * PCCREG_PRNT_CONTROL Printer Control Register 71 1.2 scw * 0 Selects auto or manual strobe mode. When low, strobe 72 1.2 scw * is automatically generated by a write to the printer 73 1.2 scw * data register. When set, strobe must be generated 74 1.2 scw * manually using bit 2 of this register. 75 1.2 scw * 1 Controls strobe timing in auto mode. When low, strobe 76 1.2 scw * time is 6.4uS. When high, strobe time is 1.6uS. 77 1.2 scw * 2 Controls strobe in manual mode. 78 1.2 scw * 3 Control Input Prime signal. When set, Input Prime 79 1.2 scw * is activated. 80 1.2 scw * 81 1.2 scw * Two other registers which are not addressed via the global PCC structure, 82 1.2 scw * live at 0xfffe2800. This address is virtualised and passed to the driver 83 1.2 scw * in the pcc_attach_args structure: 84 1.2 scw */ 85 1.2 scw #define LPC_STROBE_MODE (1 << 0) 86 1.2 scw #define LPC_FAST_STROBE (1 << 1) 87 1.2 scw #define LPC_STROBE (1 << 2) 88 1.2 scw #define LPC_INPUT_PRIME (1 << 3) 89 1.2 scw 90 1.2.16.1 scw #define lpt_control_read() pcc_reg_read(sys_pcc, PCCREG_PRNT_CONTROL) 91 1.2.16.1 scw #define lpt_control_write(v) pcc_reg_write(sys_pcc, PCCREG_PRNT_CONTROL, v) 92 1.2.16.1 scw 93 1.2 scw /* 94 1.2.16.1 scw * Data and status registers appear at the same offset. 95 1.2.16.1 scw * Write to access the data register. Read to access the status register. 96 1.2 scw */ 97 1.2.16.1 scw #define LPREG_DATA 0x00 /* Write only data register */ 98 1.2.16.1 scw #define LPREG_STATUS 0x00 /* Read only status register */ 99 1.2.16.1 scw 100 1.2.16.1 scw #define LPREG_SIZE 0x1 101 1.2 scw 102 1.2 scw /* 103 1.2 scw * Access macros for the status register 104 1.2 scw */ 105 1.2 scw #define LPS_BUSY (1 << 3) 106 1.2 scw #define LPS_PAPER_EMPTY (1 << 4) 107 1.2 scw #define LPS_SELECT (1 << 5) 108 1.2 scw #define LPS_FAULT (1 << 6) 109 1.2 scw #define LPS_ACK (1 << 7) 110 1.2 scw 111 1.2.16.1 scw #define lpt_data_write(sc,v) \ 112 1.2.16.1 scw bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, LPREG_DATA, (v)) 113 1.2.16.1 scw #define lpt_status_read(sc) \ 114 1.2.16.1 scw bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, LPREG_STATUS) 115 1.2.16.1 scw 116 1.2.16.1 scw #endif /* _MVME68K_LPT_PCCREG_H */ 117
Indexes created Fri Oct 31 11:10:07 GMT 2025