lpt_pccreg.h revision 1.3.134.1
1 1.3.134.1 yamt /* $NetBSD: lpt_pccreg.h,v 1.3.134.1 2008/05/16 02:22:52 yamt Exp $ */ 2 1.2 scw 3 1.2 scw /*- 4 1.2 scw * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.2 scw * All rights reserved. 6 1.2 scw * 7 1.2 scw * This code is derived from software contributed to The NetBSD Foundation 8 1.2 scw * by Steve C. Woodford. 9 1.2 scw * 10 1.2 scw * Redistribution and use in source and binary forms, with or without 11 1.2 scw * modification, are permitted provided that the following conditions 12 1.2 scw * are met: 13 1.2 scw * 1. Redistributions of source code must retain the above copyright 14 1.2 scw * notice, this list of conditions and the following disclaimer. 15 1.2 scw * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 scw * notice, this list of conditions and the following disclaimer in the 17 1.2 scw * documentation and/or other materials provided with the distribution. 18 1.2 scw * 19 1.2 scw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 scw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 scw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 scw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 scw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 scw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 scw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 scw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 scw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 scw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 scw * POSSIBILITY OF SUCH DAMAGE. 30 1.2 scw */ 31 1.2 scw 32 1.2 scw /* 33 1.2 scw * MVME147 Parallel Port Register Definitions 34 1.2 scw */ 35 1.3 scw #ifndef _MVME68K_LPT_PCCREG_H 36 1.3 scw #define _MVME68K_LPT_PCCREG_H 37 1.2 scw 38 1.2 scw /* 39 1.2 scw * The mvme147's PCC chip has two status/control registers for the 40 1.2 scw * printer port: 41 1.2 scw * 42 1.3 scw * PCCREG_PRNT_INTR_CTRL Printer interrupt control register 43 1.2 scw * 0 - 2 Interrupt Level 44 1.2 scw * 3 Interrupt Enable 45 1.2 scw * 4 ACK Polarity. If set, falling edge of ACK generates 46 1.2 scw * the interrupt. If clear, rising edge of ACK generates 47 1.2 scw * the interrupt. 48 1.2 scw * 5 Indicates an ACK interrupt in progress. Cleared by 49 1.2 scw * writing a one, or disabling lpt interrupts. 50 1.2 scw * 6 Indicates a FAULT interrupt. Set on falling edge 51 1.2 scw * of printer's fault signal. Cleared by writing a one. 52 1.2 scw * 7 Printer Interrupt in progress. Basically just the 53 1.2 scw * logical OR of bits 5 and 6. 54 1.2 scw */ 55 1.2 scw #define LPI_ENABLE (1 << 3) 56 1.2 scw #define LPI_ACKPOL (1 << 4) 57 1.2 scw #define LPI_ACKINT (1 << 5) 58 1.2 scw #define LPI_FAULTINT (1 << 6) 59 1.2 scw #define LPI_INTERRUPT (1 << 7) 60 1.2 scw 61 1.3 scw 62 1.2 scw /* 63 1.3 scw * PCCREG_PRNT_CONTROL Printer Control Register 64 1.2 scw * 0 Selects auto or manual strobe mode. When low, strobe 65 1.2 scw * is automatically generated by a write to the printer 66 1.2 scw * data register. When set, strobe must be generated 67 1.2 scw * manually using bit 2 of this register. 68 1.2 scw * 1 Controls strobe timing in auto mode. When low, strobe 69 1.2 scw * time is 6.4uS. When high, strobe time is 1.6uS. 70 1.2 scw * 2 Controls strobe in manual mode. 71 1.2 scw * 3 Control Input Prime signal. When set, Input Prime 72 1.2 scw * is activated. 73 1.2 scw * 74 1.2 scw * Two other registers which are not addressed via the global PCC structure, 75 1.2 scw * live at 0xfffe2800. This address is virtualised and passed to the driver 76 1.2 scw * in the pcc_attach_args structure: 77 1.2 scw */ 78 1.2 scw #define LPC_STROBE_MODE (1 << 0) 79 1.2 scw #define LPC_FAST_STROBE (1 << 1) 80 1.2 scw #define LPC_STROBE (1 << 2) 81 1.2 scw #define LPC_INPUT_PRIME (1 << 3) 82 1.2 scw 83 1.3 scw #define lpt_control_read() pcc_reg_read(sys_pcc, PCCREG_PRNT_CONTROL) 84 1.3 scw #define lpt_control_write(v) pcc_reg_write(sys_pcc, PCCREG_PRNT_CONTROL, v) 85 1.3 scw 86 1.2 scw /* 87 1.3 scw * Data and status registers appear at the same offset. 88 1.3 scw * Write to access the data register. Read to access the status register. 89 1.2 scw */ 90 1.3 scw #define LPREG_DATA 0x00 /* Write only data register */ 91 1.3 scw #define LPREG_STATUS 0x00 /* Read only status register */ 92 1.3 scw 93 1.3 scw #define LPREG_SIZE 0x1 94 1.2 scw 95 1.2 scw /* 96 1.2 scw * Access macros for the status register 97 1.2 scw */ 98 1.2 scw #define LPS_BUSY (1 << 3) 99 1.2 scw #define LPS_PAPER_EMPTY (1 << 4) 100 1.2 scw #define LPS_SELECT (1 << 5) 101 1.2 scw #define LPS_FAULT (1 << 6) 102 1.2 scw #define LPS_ACK (1 << 7) 103 1.2 scw 104 1.3 scw #define lpt_data_write(sc,v) \ 105 1.3 scw bus_space_write_1((sc)->sc_bust, (sc)->sc_bush, LPREG_DATA, (v)) 106 1.3 scw #define lpt_status_read(sc) \ 107 1.3 scw bus_space_read_1((sc)->sc_bust, (sc)->sc_bush, LPREG_STATUS) 108 1.3 scw 109 1.3 scw #endif /* _MVME68K_LPT_PCCREG_H */ 110
Indexes created Thu Oct 23 22:10:10 GMT 2025