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pccreg.h revision 1.2 
      1 /* $Id: pccreg.h,v 1.2 1996/04/18 18:07:08 chuck Exp $ */
      2 
      3 /*
      4  *
      5  * Copyright (c) 1995 Charles D. Cranor
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *      This product includes software developed by Charles D. Cranor.
     19  * 4. The name of the author may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 /*
     35  * peripheral channel controller (at pa fffe1000)
     36  */
     37 
     38 struct pcc {
     39   volatile u_long dma_taddr;		/* dma table address */
     40   volatile u_long dma_daddr;		/* dma data address */
     41   volatile u_long dma_bcnt;		/* dma byte count */
     42   volatile u_long dma_hold;		/* dma data hold register */
     43   volatile u_short t1_pload;		/* timer1 preload */
     44   volatile u_short t1_count;		/* timer1 count */
     45   volatile u_short t2_pload;		/* timer2 preload */
     46   volatile u_short t2_count;		/* timer2 count */
     47   volatile u_char t1_int;		/* timer1 interrupt ctrl */
     48   volatile u_char t1_cr;		/* timer1 ctrl reg */
     49   volatile u_char t2_int;		/* timer2 interrupt ctrl */
     50   volatile u_char t2_cr;		/* timer2 ctrl reg */
     51   volatile u_char acf_int;		/* acfail intr reg */
     52   volatile u_char dog_int;		/* watchdog intr reg */
     53   volatile u_char pr_int;		/* printer intr reg */
     54   volatile u_char pr_cr;		/* printer ctrl */
     55   volatile u_char dma_int;		/* dma interrupt control */
     56   volatile u_char dma_csr;		/* dma csr */
     57   volatile u_char bus_int;		/* bus error interrupt */
     58   volatile u_char dma_sr;		/* dma status register */
     59   volatile u_char abrt_int;		/* abort interrupt control reg */
     60   volatile u_char ta_fcr;		/* table address function code reg */
     61   volatile u_char zs_int;		/* serial interrupt reg */
     62   volatile u_char gen_cr;		/* general control register */
     63   volatile u_char le_int;		/* ethernet interrupt */
     64   volatile u_char gen_sr;		/* general status */
     65   volatile u_char scsi_int;		/* scsi interrupt reg */
     66   volatile u_char slave_ba;		/* slave base addr reg */
     67   volatile u_char sw1_int;		/* software interrupt #1 cr */
     68   volatile u_char int_vectr;		/* interrupt base vector register */
     69   volatile u_char sw2_int;		/* software interrupt #2 cr */
     70   volatile u_char pcc_rev;		/* revision level */
     71 };
     72 
     73 
     74 /*
     75  * points to system's PCC
     76  */
     77 
     78 extern struct pcc *sys_pcc;
     79 
     80 /*
     81  * we lock off our interrupt vector at 0x40.  if this is changed
     82  * we'll need to change vector.s
     83  */
     84 
     85 #define PCC_VECBASE 0x40
     86 #define PCC_NVEC 12
     87 
     88 /*
     89  * vectors we use
     90  */
     91 
     92 #define PCCV_ACFAIL	0
     93 #define PCCV_BERR	1
     94 #define PCCV_ABORT	2
     95 #define PCCV_ZS		3
     96 #define PCCV_LE		4
     97 #define PCCV_SCSIP	5
     98 #define PCCV_SCSID	6
     99 #define PCCV_PRINTER	7
    100 #define PCCV_TIMER1	8
    101 #define PCCV_TIMER2	9
    102 #define PCCV_SOFT1	10
    103 #define PCCV_SOFT2	11
    104 
    105 /*
    106  * enable interrupt
    107  */
    108 
    109 #define PCC_ICLEAR  0x80
    110 #define PCC_IENABLE 0x08
    111 
    112 /*
    113  * interrupt mask
    114  */
    115 
    116 #define PCC_IMASK 0x7
    117 
    118 /*
    119  * clock/timer
    120  */
    121 
    122 #define PCC_TIMERACK 0x80	/* ack intr */
    123 #define PCC_TIMER100HZ 63936	/* load value for 100Hz */
    124 #define PCC_TIMERCLEAR 0x0	/* reset and clear timer */
    125 #define PCC_TIMERSTART 0x3      /* start timer */
    126 
    127 /*
    128  * serial control
    129  */
    130 
    131 #define PCC_ZSEXTERN 0x10	/* let PCC supply vector */
    132