pccreg.h revision 1.5
1 /* $NetBSD: pccreg.h,v 1.5 1996/09/12 04:54:19 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 1995 Charles D. Cranor 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Charles D. Cranor. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * peripheral channel controller (at pa fffe0000) 36 */ 37 38 #define PCC_BASE 0xfffe0000 /* PA of PCC chip space */ 39 #define PCC_CLOCK_OFF 0x0000 /* offset of Mostek clock chip */ 40 #define PCC_RTC_OFF 0x07f8 /* offset of clock registers in MK */ 41 #define PCC_REG_OFF 0x1000 /* offset of PCC chip registers */ 42 #define PCC_LE_OFF 0x1800 /* offset of LANCE ethernet chip */ 43 #define PCC_VME_OFF 0x2000 /* offset of VME chip */ 44 #define PCC_LPT_OFF 0x2800 /* offset of parallel port register */ 45 #define PCC_ZS0_OFF 0x3000 /* offset of first 8530 UART */ 46 #define PCC_ZS1_OFF 0x3800 /* offset of second 8530 UART */ 47 #define PCC_WDSC_OFF 0x4000 /* offset of 33c93 SCSI chip */ 48 49 #define PCC_PADDR(off) ((void *)(PCC_BASE + (off))) 50 51 /* 52 * The PCC space is permanently mapped by pmap_bootstrap(). This 53 * macro translates PCC offsets into the corresponding KVA. 54 */ 55 #define PCC_VADDR(off) ((void *)IIOV(PCC_BASE + (off))) 56 57 struct pcc { 58 volatile u_long dma_taddr; /* dma table address */ 59 volatile u_long dma_daddr; /* dma data address */ 60 volatile u_long dma_bcnt; /* dma byte count */ 61 volatile u_long dma_hold; /* dma data hold register */ 62 volatile u_short t1_pload; /* timer1 preload */ 63 volatile u_short t1_count; /* timer1 count */ 64 volatile u_short t2_pload; /* timer2 preload */ 65 volatile u_short t2_count; /* timer2 count */ 66 volatile u_char t1_int; /* timer1 interrupt ctrl */ 67 volatile u_char t1_cr; /* timer1 ctrl reg */ 68 volatile u_char t2_int; /* timer2 interrupt ctrl */ 69 volatile u_char t2_cr; /* timer2 ctrl reg */ 70 volatile u_char acf_int; /* acfail intr reg */ 71 volatile u_char dog_int; /* watchdog intr reg */ 72 volatile u_char pr_int; /* printer intr reg */ 73 volatile u_char pr_cr; /* printer ctrl */ 74 volatile u_char dma_int; /* dma interrupt control */ 75 volatile u_char dma_csr; /* dma csr */ 76 volatile u_char bus_int; /* bus error interrupt */ 77 volatile u_char dma_sr; /* dma status register */ 78 volatile u_char abrt_int; /* abort interrupt control reg */ 79 volatile u_char ta_fcr; /* table address function code reg */ 80 volatile u_char zs_int; /* serial interrupt reg */ 81 volatile u_char gen_cr; /* general control register */ 82 volatile u_char le_int; /* ethernet interrupt */ 83 volatile u_char gen_sr; /* general status */ 84 volatile u_char scsi_int; /* scsi interrupt reg */ 85 volatile u_char slave_ba; /* slave base addr reg */ 86 volatile u_char sw1_int; /* software interrupt #1 cr */ 87 volatile u_char int_vectr; /* interrupt base vector register */ 88 volatile u_char sw2_int; /* software interrupt #2 cr */ 89 volatile u_char pcc_rev; /* revision level */ 90 }; 91 92 93 /* 94 * points to system's PCC 95 */ 96 97 extern struct pcc *sys_pcc; 98 99 /* 100 * we lock off our interrupt vector at 0x40. 101 */ 102 103 #define PCC_VECBASE 0x40 104 #define PCC_NVEC 12 105 106 /* 107 * vectors we use 108 */ 109 110 #define PCCV_ACFAIL 0 111 #define PCCV_BERR 1 112 #define PCCV_ABORT 2 113 #define PCCV_ZS 3 114 #define PCCV_LE 4 115 #define PCCV_SCSIP 5 116 #define PCCV_SCSID 6 117 #define PCCV_PRINTER 7 118 #define PCCV_TIMER1 8 119 #define PCCV_TIMER2 9 120 #define PCCV_SOFT1 10 121 #define PCCV_SOFT2 11 122 123 /* 124 * enable interrupt 125 */ 126 127 #define PCC_ICLEAR 0x80 128 #define PCC_IENABLE 0x08 129 130 /* 131 * interrupt mask 132 */ 133 134 #define PCC_IMASK 0x7 135 136 /* 137 * clock/timer 138 */ 139 140 #define PCC_TIMERACK 0x80 /* ack intr */ 141 #define PCC_TIMER100HZ 63936 /* load value for 100Hz */ 142 #define PCC_TIMERCLEAR 0x0 /* reset and clear timer */ 143 #define PCC_TIMERSTOP 0x1 /* stop clock, but don't clear it */ 144 #define PCC_TIMERSTART 0x3 /* start timer */ 145 146 #define pcc_timer_hz2lim(hz) (65536 - (160000/(hz))) 147 #define pcc_timer_us2lim(us) (65536 - (160000/(1000000/(us)))) 148 149 /* 150 * serial control 151 */ 152 153 #define PCC_ZSEXTERN 0x10 /* let PCC supply vector */ 154 155 /* 156 * abort switch 157 */ 158 159 #define PCC_ABORT_IEN 0x08 /* enable interrupt */ 160 #define PCC_ABORT_ABS 0x40 /* current state of switch */ 161 #define PCC_ABORT_ACK 0x80 /* interrupt active; write to ack */ 162 163 /* 164 * general control register 165 */ 166 167 #define PCC_GENCR_IEN 0x10 /* global interrupt enable */ 168
Indexes created Tue Sep 30 11:09:46 GMT 2025