sbic.c revision 1.1
1 /* $NetBSD: sbic.c,v 1.1 1996/04/18 18:30:55 chuck Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/device.h> 59 #include <sys/kernel.h> /* For hz */ 60 #include <sys/disklabel.h> 61 #include <sys/dkstat.h> 62 #include <sys/buf.h> 63 #include <scsi/scsi_all.h> 64 #include <scsi/scsiconf.h> 65 #include <vm/vm.h> 66 #include <vm/vm_kern.h> 67 #include <vm/vm_page.h> 68 #include <vm/pmap.h> 69 #include <machine/pmap.h> 70 #include <mvme68k/mvme68k/isr.h> 71 #include <mvme68k/dev/dmavar.h> 72 #include <mvme68k/dev/sbicreg.h> 73 #include <mvme68k/dev/sbicvar.h> 74 75 76 /* 77 * Since I can't find this in any other header files 78 */ 79 #define SCSI_PHASE(reg) (reg&0x07) 80 81 /* 82 * SCSI delays 83 * In u-seconds, primarily for state changes on the SPC. 84 */ 85 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 86 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 87 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 88 89 /* 90 * Convenience macro for waiting for a particular sbic event 91 */ 92 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 93 94 extern u_int kvtop(); 95 96 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 97 int sbicgo __P((struct sbic_softc *, struct scsi_xfer *)); 98 int sbicdmaok __P((struct sbic_softc *, struct scsi_xfer *)); 99 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 100 int sbiccheckdmap __P((void *, u_long, u_long)); 101 u_char sbicselectbus __P((struct sbic_softc *)); 102 int sbicxfout __P((sbic_regmap_p, int, void *)); 103 int sbicxfin __P((sbic_regmap_p, int, void *)); 104 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 105 int sbictoscsiperiod __P((struct sbic_softc *, int)); 106 int sbicintr __P((struct sbic_softc *)); 107 int sbicpoll __P((struct sbic_softc *)); 108 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 109 int sbicmsgin __P((struct sbic_softc *)); 110 int sbicabort __P((struct sbic_softc *, char *)); 111 void sbicxfdone __P((struct sbic_softc *)); 112 void sbicerror __P((struct sbic_softc *,u_char)); 113 void sbicreset __P((struct sbic_softc *)); 114 void sbic_scsidone __P((struct sbic_acb *, int)); 115 void sbic_sched __P((struct sbic_softc *)); 116 void sbic_save_ptrs __P((struct sbic_softc *)); 117 void sbic_load_ptrs __P((struct sbic_softc *)); 118 119 /* 120 * Synch xfer parameters, and timing conversions 121 */ 122 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 123 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 124 int sbic_cmd_wait = SBIC_CMD_WAIT; 125 int sbic_data_wait = SBIC_DATA_WAIT; 126 int sbic_init_wait = SBIC_INIT_WAIT; 127 128 /* 129 * was broken before.. now if you want this you get it for all drives 130 * on sbic controllers. 131 */ 132 u_char sbic_inhibit_sync[8]; 133 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 134 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 135 int sbic_parallel_operations = 1; /* Allow command queues */ 136 137 /* 138 * Some useful stuff for debugging purposes 139 */ 140 #ifdef DEBUG 141 int sbicdma_ops = 0; /* total DMA operations */ 142 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 143 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 144 int sbicdma_saves = 0; 145 146 #define QPRINTF(a) if (sbic_debug > 1) printf a 147 148 int sbic_debug = 0; /* Debug all chip related things */ 149 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 150 int reselect_debug = 0; /* Debug all reselection related things */ 151 int report_sense = 0; /* Always print Sense information */ 152 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 153 154 void sbictimeout __P((struct sbic_softc *dev)); 155 156 #else 157 #define QPRINTF(a) /* */ 158 #endif 159 160 161 /* 162 * default minphys routine for sbic based controllers 163 */ 164 void 165 sbic_minphys(bp) 166 struct buf *bp; 167 { 168 /* 169 * No max transfer at this level. 170 */ 171 minphys(bp); 172 } 173 174 175 /* 176 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 177 */ 178 void 179 sbic_save_ptrs(dev) 180 struct sbic_softc *dev; 181 { 182 sbic_regmap_p regs; 183 struct sbic_acb* acb; 184 int count, 185 asr, 186 s; 187 188 /* 189 * Only need to save pointers if DMA was active... 190 */ 191 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 192 return; 193 194 regs = dev->sc_sbicp; 195 196 s = splbio(); 197 198 /* 199 * Wait until WD chip is idle 200 */ 201 do { 202 GET_SBIC_asr(regs, asr); 203 if( asr & SBIC_ASR_DBR ) { 204 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 205 splx(s); 206 return; 207 } 208 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 209 210 211 /* 212 * Save important state. 213 * must be done before dmastop 214 */ 215 acb = dev->sc_nexus; 216 acb->sc_dmacmd = dev->sc_dmacmd; 217 218 /* 219 * Fetch the residual count 220 */ 221 SBIC_TC_GET(regs, count); 222 223 /* 224 * Shut down DMA 225 */ 226 dev->sc_dmastop(dev); 227 228 /* 229 * No longer in DMA 230 */ 231 dev->sc_flags &= ~SBICF_INDMA; 232 233 /* 234 * Ensure the WD chip is back in polled I/O mode, with nothing to 235 * transfer. 236 */ 237 SBIC_TC_PUT(regs, 0); 238 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 239 240 /* 241 * Update current count... 242 */ 243 acb->sc_tcnt = count; 244 245 /* 246 * Work out how many bytes were actually transferred 247 */ 248 count = dev->sc_tcnt - count; 249 dev->sc_tcnt = acb->sc_tcnt; 250 251 /* 252 * Fixup partial xfers 253 */ 254 acb->sc_kv.dc_addr += count; 255 acb->sc_kv.dc_count -= count; 256 acb->sc_pa.dc_addr += count; 257 acb->sc_pa.dc_count -= count >> 1; 258 259 #ifdef DEBUG 260 if ( data_pointer_debug ) 261 printf("save at (%x,%x):%x\n", 262 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 263 sbicdma_saves++; 264 #endif 265 266 splx(s); 267 } 268 269 270 /* 271 * DOES NOT RESTART DMA!!! 272 */ 273 void 274 sbic_load_ptrs(dev) 275 struct sbic_softc *dev; 276 { 277 struct sbic_acb *acb = dev->sc_nexus; 278 int s; 279 280 if ( acb->sc_kv.dc_count == 0 ) { 281 /* 282 * No data to xfer 283 */ 284 return; 285 } 286 287 s = splbio(); 288 289 /* 290 * Reset the Scatter-Gather chain 291 */ 292 dev->sc_last = dev->sc_cur = &acb->sc_pa; 293 294 /* 295 * Restore the Transfer Count and DMA specific data 296 */ 297 dev->sc_tcnt = acb->sc_tcnt; 298 dev->sc_dmacmd = acb->sc_dmacmd; 299 300 #ifdef DEBUG 301 sbicdma_ops++; 302 #endif 303 304 /* 305 * Need to fixup new segment? 306 */ 307 if ( dev->sc_tcnt == 0 ) { 308 /* 309 * sc_tcnt == 0 implies end of segment 310 */ 311 char *vaddr, *paddr; 312 int count; 313 314 /* 315 * do kvm to pa mappings 316 */ 317 vaddr = acb->sc_kv.dc_addr; 318 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 319 320 for (count = (NBPG - ((int)vaddr & PGOFSET)); 321 count < acb->sc_kv.dc_count && 322 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 323 count += NBPG) 324 ; /* Do nothing */ 325 326 /* 327 * If it's all contiguous... 328 */ 329 if ( count > acb->sc_kv.dc_count ) { 330 count = acb->sc_kv.dc_count; 331 #ifdef DEBUG 332 sbicdma_hits++; 333 #endif 334 } 335 #ifdef DEBUG 336 else 337 sbicdma_misses++; 338 #endif 339 340 acb->sc_tcnt = count; 341 acb->sc_pa.dc_count = count >> 1; 342 343 #ifdef DEBUG 344 if ( data_pointer_debug ) 345 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 346 acb->sc_kv.dc_count, 347 acb->sc_pa.dc_addr, 348 acb->sc_tcnt); 349 #endif 350 351 } 352 353 splx(s); 354 } 355 356 /* 357 * used by specific sbic controller 358 * 359 * it appears that the higher level code does nothing with LUN's 360 * so I will too. I could plug it in, however so could they 361 * in scsi_scsi_cmd(). 362 */ 363 int 364 sbic_scsicmd(xs) 365 struct scsi_xfer *xs; 366 { 367 struct scsi_link *slp = xs->sc_link; 368 struct sbic_softc *dev = slp->adapter_softc; 369 struct sbic_acb *acb; 370 int flags = xs->flags, 371 s; 372 373 if ( flags & SCSI_DATA_UIO ) 374 panic("sbic: scsi data uio requested"); 375 376 if ( dev->sc_nexus && (flags & SCSI_POLL) ) 377 panic("sbic_scsicmd: busy"); 378 379 if ( slp->target == slp->adapter_target ) 380 return ESCAPE_NOT_SUPPORTED; 381 382 s = splbio(); 383 384 if ( (acb = dev->free_list.tqh_first) != NULL ) 385 TAILQ_REMOVE(&dev->free_list, acb, chain); 386 387 splx(s); 388 389 if ( acb == NULL ) { 390 #ifdef DEBUG 391 printf("sbic_scsicmd: unable to queue request for target %d\n", 392 slp->target); 393 #ifdef DDB 394 Debugger(); 395 #endif 396 #endif 397 xs->error = XS_DRIVER_STUFFUP; 398 399 return(TRY_AGAIN_LATER); 400 } 401 402 if ( flags & SCSI_DATA_IN ) 403 acb->flags = ACB_ACTIVE | ACB_DATAIN; 404 else 405 acb->flags = ACB_ACTIVE; 406 407 acb->xs = xs; 408 acb->clen = xs->cmdlen; 409 acb->sc_kv.dc_addr = xs->data; 410 acb->sc_kv.dc_count = xs->datalen; 411 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 412 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 413 414 if ( flags & SCSI_POLL ) { 415 /* 416 * This has major side effects -- it locks up the machine 417 */ 418 int stat; 419 420 s = splbio(); 421 422 dev->sc_flags |= SBICF_ICMD; 423 424 do { 425 /* 426 * If we already had a nexus, while away the time until idle... 427 * This is likely only to happen if a reselection occurs between 428 * here and our earlier check for ICMD && sc_nexus (which would 429 * have resulted in a panic() had it been true). 430 */ 431 while ( dev->sc_nexus ) 432 sbicpoll(dev); 433 434 /* 435 * Fix up the new nexus 436 */ 437 dev->sc_nexus = acb; 438 dev->sc_xs = xs; 439 dev->target = slp->target; 440 dev->lun = slp->lun; 441 442 stat = sbicicmd(dev, &acb->cmd, acb->clen, 443 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 444 445 } while ( dev->sc_nexus != acb ); 446 447 sbic_scsidone(acb, stat); 448 449 splx(s); 450 451 return(COMPLETE); 452 } 453 454 s = splbio(); 455 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 456 457 /* 458 * If nothing is active, try to start it now. 459 */ 460 if ( dev->sc_nexus == NULL ) 461 sbic_sched(dev); 462 463 splx(s); 464 465 return(SUCCESSFULLY_QUEUED); 466 } 467 468 /* 469 * attempt to start the next available command 470 */ 471 void 472 sbic_sched(dev) 473 struct sbic_softc *dev; 474 { 475 struct scsi_xfer *xs; 476 struct scsi_link *slp = NULL; /* Gag the compiler */ 477 struct sbic_acb *acb; 478 int flags, 479 stat; 480 481 /* 482 * XXXSCW 483 * I'll keep this test here, even though I can't see any obvious way 484 * in which sbic_sched() could be called with sc_nexus non NULL 485 */ 486 if ( dev->sc_nexus ) 487 return; /* a command is current active */ 488 489 /* 490 * Loop through the ready list looking for work to do... 491 */ 492 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 493 int i, j; 494 495 slp = acb->xs->sc_link; 496 i = slp->target; 497 j = 1 << slp->lun; 498 499 /* 500 * We've found a potential command, but is the target/lun busy? 501 */ 502 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 503 /* 504 * Nope, it's not busy, so we can use it. 505 */ 506 dev->sc_tinfo[i].lubusy |= j; 507 TAILQ_REMOVE(&dev->ready_list, acb, chain); 508 dev->sc_nexus = acb; 509 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 510 break; 511 } 512 } 513 514 if ( acb == NULL ) { 515 QPRINTF(("sbicsched: no work\n")); 516 return; /* did not find an available command */ 517 } 518 519 #ifdef DEBUG 520 if ( data_pointer_debug > 1 ) 521 printf("sbic_sched(%d,%d)\n", slp->target, slp->lun); 522 #endif 523 524 dev->sc_xs = xs = acb->xs; 525 flags = xs->flags; 526 527 if ( flags & SCSI_RESET ) 528 sbicreset(dev); 529 530 dev->sc_stat[0] = -1; 531 dev->target = slp->target; 532 dev->lun = slp->lun; 533 534 if ( flags & SCSI_POLL || (!sbic_parallel_operations && 535 (sbicdmaok(dev, xs) == 0)) ) 536 stat = sbicicmd(dev, &acb->cmd, acb->clen, 537 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 538 else 539 if ( sbicgo(dev, xs) == 0 ) 540 return; 541 else 542 stat = dev->sc_stat[0]; 543 544 sbic_scsidone(acb, stat); 545 } 546 547 void 548 sbic_scsidone(acb, stat) 549 struct sbic_acb *acb; 550 int stat; 551 { 552 struct scsi_xfer *xs = acb->xs; 553 struct scsi_link *slp = xs->sc_link; 554 struct sbic_softc *dev = slp->adapter_softc; 555 int dosched = 0; 556 557 #ifdef DIAGNOSTIC 558 if ( acb == NULL || xs == NULL ) { 559 printf("sbic_scsidone -- (%d,%d) no scsi_xfer\n", dev->target, dev->lun); 560 #ifdef DDB 561 Debugger(); 562 #endif 563 return; 564 } 565 #endif 566 567 if ( slp->device_softc && 568 ((struct device *)(slp->device_softc))->dv_unit < dk_ndrive) 569 ++dk_xfer[((struct device *)(slp->device_softc))->dv_unit]; 570 571 /* 572 * is this right? 573 */ 574 xs->status = stat; 575 576 #ifdef DEBUG 577 if ( data_pointer_debug > 1 ) 578 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->target, slp->lun, 579 dev->target, dev->lun, stat); 580 581 if ( xs->sc_link->target == dev->sc_link.adapter_target ) 582 panic("target == hostid"); 583 #endif 584 585 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 586 587 if ( stat == SCSI_CHECK ) { 588 /* 589 * Schedule a REQUEST SENSE 590 */ 591 struct scsi_sense *ss = (void *)&acb->cmd; 592 593 #ifdef DEBUG 594 if ( report_sense ) 595 printf("sbic_scsidone: autosense %02x targ %d lun %d", 596 acb->cmd.opcode, slp->target, slp->lun); 597 #endif 598 599 bzero(ss, sizeof(*ss)); 600 601 ss->opcode = REQUEST_SENSE; 602 ss->byte2 = slp->lun << 5; 603 ss->length = sizeof(struct scsi_sense_data); 604 605 acb->clen = sizeof(*ss); 606 acb->sc_kv.dc_addr = (char *)&xs->sense; 607 acb->sc_kv.dc_count = sizeof(struct scsi_sense_data); 608 acb->pa_addr = (char *)kvtop(&xs->sense); /* XXX check */ 609 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 610 611 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 612 613 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 614 dev->sc_tinfo[slp->target].senses++; 615 616 if ( dev->sc_nexus == acb ) { 617 dev->sc_nexus = NULL; 618 dev->sc_xs = NULL; 619 sbic_sched(dev); 620 } 621 return; 622 } 623 } 624 625 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 626 627 xs->error = XS_SENSE; 628 629 #ifdef DEBUG 630 if (report_sense) 631 printf(" => %02x %02x\n", xs->sense.flags, 632 xs->sense.extra_bytes[3]); 633 #endif 634 635 } else { 636 xs->resid = 0; /* XXXX */ 637 } 638 639 xs->flags |= ITSDONE; 640 641 /* 642 * Remove the ACB from whatever queue it's on. We have to do a bit of 643 * a hack to figure out which queue it's on. Note that it is *not* 644 * necessary to cdr down the ready queue, but we must cdr down the 645 * nexus queue and see if it's there, so we can mark the unit as no 646 * longer busy. This code is sickening, but it works. 647 */ 648 if ( acb == dev->sc_nexus ) { 649 650 dev->sc_nexus = NULL; 651 dev->sc_xs = NULL; 652 653 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 654 655 if ( dev->ready_list.tqh_first ) 656 dosched = 1; /* start next command */ 657 658 } else 659 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 660 661 TAILQ_REMOVE(&dev->ready_list, acb, chain); 662 663 } else { 664 665 register struct sbic_acb *a; 666 667 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 668 if ( a == acb ) { 669 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 670 dev->sc_tinfo[slp->target].lubusy &= ~(1 << slp->lun); 671 break; 672 } 673 } 674 675 if ( a ) 676 ; 677 else if ( acb->chain.tqe_next ) { 678 TAILQ_REMOVE(&dev->ready_list, acb, chain); 679 } else { 680 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 681 #ifdef DDB 682 Debugger(); 683 #endif 684 } 685 } 686 687 /* 688 * Put it on the free list. 689 */ 690 acb->flags = ACB_FREE; 691 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 692 693 dev->sc_tinfo[slp->target].cmds++; 694 695 scsi_done(xs); 696 697 if ( dosched ) 698 sbic_sched(dev); 699 } 700 701 int 702 sbicdmaok(dev, xs) 703 struct sbic_softc *dev; 704 struct scsi_xfer *xs; 705 { 706 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 707 return(0); 708 709 /* 710 * controller supports dma to any addresses? 711 */ 712 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 713 return(1); 714 715 /* 716 * this address is ok for dma? 717 */ 718 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 719 return(1); 720 721 return(0); 722 } 723 724 int 725 sbicwait(regs, until, timeo, line) 726 sbic_regmap_p regs; 727 u_char until; 728 int timeo; 729 int line; 730 { 731 u_char val; 732 733 if ( timeo == 0 ) 734 timeo = 1000000; /* some large value.. */ 735 736 GET_SBIC_asr(regs, val); 737 738 while ( (val & until) == 0 ) { 739 740 if ( timeo-- == 0 ) { 741 int csr; 742 GET_SBIC_csr(regs, csr); 743 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 744 #if defined(DDB) && defined(DEBUG) 745 Debugger(); 746 #endif 747 return(val); /* Maybe I should abort */ 748 break; 749 } 750 751 DELAY(1); 752 GET_SBIC_asr(regs, val); 753 } 754 755 return(val); 756 } 757 758 int 759 sbicabort(dev, where) 760 struct sbic_softc *dev; 761 char *where; 762 { 763 sbic_regmap_p regs = dev->sc_sbicp; 764 u_char csr, 765 asr; 766 767 GET_SBIC_asr(regs, asr); 768 GET_SBIC_csr(regs, csr); 769 770 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 771 dev->sc_dev.dv_xname, where, csr, asr); 772 773 /* 774 * Clean up chip itself 775 */ 776 if ( dev->sc_flags & SBICF_SELECTED ) { 777 778 while ( asr & SBIC_ASR_DBR ) { 779 /* 780 * sbic is jammed w/data. need to clear it 781 * But we don't know what direction it needs to go 782 */ 783 GET_SBIC_data(regs, asr); 784 printf("%s: abort %s: clearing data buffer 0x%02x\n", 785 dev->sc_dev.dv_xname, where, asr); 786 GET_SBIC_asr(regs, asr); 787 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 788 SET_SBIC_data(regs, asr); 789 GET_SBIC_asr(regs, asr); 790 } 791 792 WAIT_CIP(regs); 793 794 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 795 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 796 WAIT_CIP(regs); 797 798 GET_SBIC_asr(regs, asr); 799 800 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 801 /* 802 * ok, get more drastic.. 803 */ 804 printf("%s: sbicabort - asr %x, trying to reset\n", 805 dev->sc_dev.dv_xname, asr); 806 sbicreset(dev); 807 dev->sc_flags &= ~SBICF_SELECTED; 808 return -1; 809 } 810 811 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 812 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 813 814 do { 815 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 816 GET_SBIC_asr(regs, asr); 817 GET_SBIC_csr (regs, csr); 818 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 819 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 820 (csr != SBIC_CSR_CMD_INVALID) ); 821 822 /* 823 * lets just hope it worked.. 824 */ 825 dev->sc_flags &= ~SBICF_SELECTED; 826 } 827 828 return -1; 829 } 830 831 832 /* 833 * Initialize driver-private structures 834 */ 835 void 836 sbicinit(dev) 837 struct sbic_softc *dev; 838 { 839 u_int i; 840 841 extern u_long scsi_nosync; 842 extern int shift_nosync; 843 844 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 845 846 struct sbic_acb *acb; 847 848 TAILQ_INIT(&dev->ready_list); 849 TAILQ_INIT(&dev->nexus_list); 850 TAILQ_INIT(&dev->free_list); 851 852 dev->sc_nexus = NULL; 853 dev->sc_xs = NULL; 854 855 acb = dev->sc_acb; 856 bzero(acb, sizeof(dev->sc_acb)); 857 858 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 859 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 860 acb++; 861 } 862 863 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 864 865 #ifdef DEBUG 866 /* 867 * make sure timeout is really not needed 868 */ 869 timeout((void *)sbictimeout, dev, 30 * hz); 870 #endif 871 872 } else 873 panic("sbic: reinitializing driver!"); 874 875 dev->sc_flags |= SBICF_ALIVE; 876 dev->sc_flags &= ~SBICF_SELECTED; 877 878 /* 879 * initialize inhibit array 880 */ 881 if ( scsi_nosync ) { 882 883 u_int inhibit_sync = (scsi_nosync >> shift_nosync) & 0xff; 884 885 shift_nosync += 8; 886 887 #ifdef DEBUG 888 if ( inhibit_sync ) 889 printf("%s: Inhibiting synchronous transfer %02x\n", 890 dev->sc_dev.dv_xname, inhibit_sync); 891 #endif 892 for (i = 0; i < 8; ++i) { 893 if ( inhibit_sync & (1 << i) ) 894 sbic_inhibit_sync[i] = 1; 895 } 896 } 897 898 sbicreset(dev); 899 } 900 901 void 902 sbicreset(dev) 903 struct sbic_softc *dev; 904 { 905 sbic_regmap_p regs = dev->sc_sbicp; 906 u_int my_id, 907 s; 908 u_char csr; 909 910 s = splbio(); 911 912 my_id = dev->sc_link.adapter_target & SBIC_ID_MASK; 913 914 if (dev->sc_clkfreq < 110) 915 my_id |= SBIC_ID_FS_8_10; 916 else if (dev->sc_clkfreq < 160) 917 my_id |= SBIC_ID_FS_12_15; 918 else if (dev->sc_clkfreq < 210) 919 my_id |= SBIC_ID_FS_16_20; 920 921 SET_SBIC_myid(regs, my_id); 922 923 /* 924 * Reset the chip 925 */ 926 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 927 DELAY(25); 928 929 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 930 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 931 932 /* 933 * Set up various chip parameters 934 */ 935 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 936 937 /* 938 * don't allow Selection (SBIC_RID_ES) 939 * until we can handle target mode!! 940 */ 941 SET_SBIC_rselid(regs, SBIC_RID_ER); 942 943 /* 944 * Asynchronous for now 945 */ 946 SET_SBIC_syn(regs, 0); 947 948 /* 949 * Anything else was zeroed by reset 950 */ 951 splx(s); 952 953 dev->sc_flags &= ~SBICF_SELECTED; 954 } 955 956 void 957 sbicerror(dev, csr) 958 struct sbic_softc *dev; 959 u_char csr; 960 { 961 struct scsi_xfer *xs = dev->sc_xs; 962 963 #ifdef DIAGNOSTIC 964 if ( xs == NULL ) 965 panic("sbicerror: dev->sc_xs == NULL"); 966 #endif 967 968 if ( xs->flags & SCSI_SILENT ) 969 return; 970 971 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 972 } 973 974 /* 975 * select the bus, return when selected or error. 976 * 977 * Returns the current CSR following selection and optionally MSG out phase. 978 * i.e. the returned CSR *should* indicate CMD phase... 979 * If the return value is 0, some error happened. 980 */ 981 u_char 982 sbicselectbus(dev) 983 struct sbic_softc *dev; 984 { 985 sbic_regmap_p regs = dev->sc_sbicp; 986 u_char target = dev->target, 987 lun = dev->lun, 988 asr, 989 csr, 990 id; 991 992 /* 993 * if we're already selected, return (XXXX panic maybe?) 994 */ 995 if ( dev->sc_flags & SBICF_SELECTED ) 996 return(0); 997 998 QPRINTF(("sbicselectbus %d: ", target)); 999 1000 /* 1001 * issue select 1002 */ 1003 SET_SBIC_selid(regs, target); 1004 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 1005 1006 /* 1007 * set sync or async 1008 */ 1009 if ( dev->sc_sync[target].state == SYNC_DONE ) 1010 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1011 dev->sc_sync[target].period)); 1012 else 1013 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1014 1015 GET_SBIC_asr(regs, asr); 1016 1017 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 1018 /* 1019 * This means we got ourselves reselected upon 1020 */ 1021 QPRINTF(("WD busy (reselect?)\n")); 1022 return 0; 1023 } 1024 1025 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1026 1027 /* 1028 * wait for select (merged from seperate function may need 1029 * cleanup) 1030 */ 1031 WAIT_CIP(regs); 1032 1033 do { 1034 1035 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1036 1037 if ( asr & SBIC_ASR_LCI ) { 1038 QPRINTF(("late LCI: asr %02x\n", asr)); 1039 return 0; 1040 } 1041 1042 /* 1043 * Clear interrupt 1044 */ 1045 GET_SBIC_csr (regs, csr); 1046 1047 QPRINTF(("%02x ", csr)); 1048 1049 /* 1050 * Reselected from under our feet? 1051 */ 1052 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1053 QPRINTF(("got reselected, asr %02x\n", asr)); 1054 /* 1055 * We need to handle this now so we don't lock up later 1056 */ 1057 sbicnextstate(dev, csr, asr); 1058 1059 return 0; 1060 } 1061 1062 /* 1063 * Whoops! 1064 */ 1065 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1066 panic("sbicselectbus: target issued select!"); 1067 return 0; 1068 } 1069 1070 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1071 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1072 csr != SBIC_CSR_SEL_TIMEO); 1073 1074 /* 1075 * Anyone at home? 1076 */ 1077 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1078 dev->sc_xs->error = XS_SELTIMEOUT; 1079 QPRINTF(("Selection Timeout\n")); 1080 return 0; 1081 } 1082 1083 QPRINTF(("Selection Complete\n")); 1084 1085 /* 1086 * Assume we're now selected 1087 */ 1088 GET_SBIC_selid(regs, id); 1089 dev->target = id; 1090 dev->lun = lun; 1091 dev->sc_flags |= SBICF_SELECTED; 1092 1093 /* 1094 * Enable (or not) reselection 1095 * XXXSCW This is probably not necessary since we don't use use the 1096 * Select-and-Xfer-with-ATN command to initialte a selection... 1097 */ 1098 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1099 SET_SBIC_rselid (regs, 0); 1100 else 1101 SET_SBIC_rselid (regs, SBIC_RID_ER); 1102 1103 /* 1104 * We only really need to do anything when the target goes to MSG out 1105 * If the device ignored ATN, it's probably old and brain-dead, 1106 * but we'll try to support it anyhow. 1107 * If it doesn't support message out, it definately doesn't 1108 * support synchronous transfers, so no point in even asking... 1109 */ 1110 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1111 /* 1112 * Send identify message (SCSI-2 requires an identify msg) 1113 */ 1114 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1115 /* 1116 * Handle drives that don't want to be asked 1117 * whether to go sync at all. 1118 */ 1119 dev->sc_sync[id].offset = 0; 1120 dev->sc_sync[id].period = sbic_min_period; 1121 dev->sc_sync[id].state = SYNC_DONE; 1122 } 1123 1124 /* 1125 * Do we need to negotiate Synchronous Xfers for this target? 1126 */ 1127 if ( dev->sc_sync[id].state != SYNC_START ) { 1128 /* 1129 * Nope, we've already negotiated. 1130 * Now see if we should allow the target to disconnect/reselect... 1131 */ 1132 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 1133 !sbic_enable_reselect ) 1134 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1135 else 1136 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1137 1138 } else { 1139 /* 1140 * try to initiate a sync transfer. 1141 * So compose the sync message we're going 1142 * to send to the target 1143 */ 1144 #ifdef DEBUG 1145 if ( sync_debug ) 1146 printf("\nSending sync request to target %d ... ", id); 1147 #endif 1148 /* 1149 * setup scsi message sync message request 1150 */ 1151 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1152 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1153 dev->sc_msg[2] = 3; 1154 dev->sc_msg[3] = MSG_SYNC_REQ; 1155 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1156 dev->sc_msg[5] = sbic_max_offset; 1157 1158 sbicxfout(regs, 6, dev->sc_msg); 1159 1160 dev->sc_sync[id].state = SYNC_SENT; 1161 #ifdef DEBUG 1162 if ( sync_debug ) 1163 printf ("sent\n"); 1164 #endif 1165 } 1166 1167 /* 1168 * There's one interrupt still to come: the change to CMD phase... 1169 */ 1170 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1171 GET_SBIC_csr(regs, csr); 1172 } 1173 1174 return csr; 1175 } 1176 1177 /* 1178 * Information Transfer *to* a Scsi Target 1179 */ 1180 int 1181 sbicxfout(regs, len, bp) 1182 sbic_regmap_p regs; 1183 int len; 1184 void *bp; 1185 { 1186 int wait = sbic_data_wait; 1187 u_char asr, 1188 *buf = bp; 1189 1190 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1191 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1192 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1193 1194 /* 1195 * sigh.. WD-PROTO strikes again.. sending the command in one go 1196 * causes the chip to lock up if talking to certain (misbehaving?) 1197 * targets. Anyway, this procedure should work for all targets, but 1198 * it's slightly slower due to the overhead 1199 */ 1200 WAIT_CIP (regs); 1201 1202 SBIC_TC_PUT (regs, 0); 1203 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1204 SBIC_TC_PUT (regs, (unsigned)len); 1205 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1206 1207 /* 1208 * Loop for each byte transferred 1209 */ 1210 do { 1211 1212 GET_SBIC_asr (regs, asr); 1213 1214 if ( asr & SBIC_ASR_DBR ) { 1215 if ( len ) { 1216 SET_SBIC_data (regs, *buf); 1217 buf++; 1218 len--; 1219 } else { 1220 SET_SBIC_data (regs, 0); 1221 } 1222 wait = sbic_data_wait; 1223 } 1224 1225 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1226 1227 SBIC_TC_GET(regs, len); 1228 SBIC_TC_PUT(regs, 0); 1229 1230 #ifdef DEBUG 1231 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1232 #endif 1233 1234 /* 1235 * this leaves with one csr to be read 1236 */ 1237 return(len); 1238 } 1239 1240 /* 1241 * Information Transfer *from* a Scsi Target 1242 * returns # bytes left to read 1243 */ 1244 int 1245 sbicxfin(regs, len, bp) 1246 sbic_regmap_p regs; 1247 int len; 1248 void *bp; 1249 { 1250 int wait = sbic_data_wait; 1251 u_char *buf = bp; 1252 u_char asr; 1253 #ifdef DEBUG 1254 u_char *obp = bp; 1255 #endif 1256 1257 WAIT_CIP (regs); 1258 1259 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1260 SBIC_TC_PUT (regs, (unsigned)len); 1261 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1262 1263 /* 1264 * Loop for each byte transferred 1265 */ 1266 do { 1267 1268 GET_SBIC_asr (regs, asr); 1269 1270 if ( asr & SBIC_ASR_DBR ) { 1271 if ( len ) { 1272 GET_SBIC_data (regs, *buf); 1273 buf++; 1274 len--; 1275 } else { 1276 u_char foo; 1277 GET_SBIC_data (regs, foo); 1278 } 1279 wait = sbic_data_wait; 1280 } 1281 1282 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1283 1284 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1285 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1286 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1287 1288 SBIC_TC_PUT (regs, 0); 1289 1290 /* 1291 * this leaves with one csr to be read 1292 */ 1293 return len; 1294 } 1295 1296 /* 1297 * SCSI 'immediate' command: issue a command to some SCSI device 1298 * and get back an 'immediate' response (i.e., do programmed xfer 1299 * to get the response data). 'cbuf' is a buffer containing a scsi 1300 * command of length clen bytes. 'buf' is a buffer of length 'len' 1301 * bytes for data. The transfer direction is determined by the device 1302 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1303 * command must supply no data. 1304 */ 1305 int 1306 sbicicmd(dev, cbuf, clen, buf, len) 1307 struct sbic_softc *dev; 1308 void *cbuf, 1309 *buf; 1310 int clen, 1311 len; 1312 { 1313 sbic_regmap_p regs = dev->sc_sbicp; 1314 struct sbic_acb *acb = dev->sc_nexus; 1315 u_char csr, 1316 asr; 1317 int still_busy = 1; 1318 1319 /* 1320 * Make sure pointers are OK 1321 */ 1322 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1323 dev->sc_tcnt = acb->sc_tcnt = 0; 1324 1325 acb->sc_dmacmd = 0; 1326 acb->sc_pa.dc_count = 0; /* No DMA */ 1327 acb->sc_kv.dc_addr = buf; 1328 acb->sc_kv.dc_count = len; 1329 1330 #ifdef DEBUG 1331 if ( data_pointer_debug > 1 ) 1332 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1333 #endif 1334 1335 /* 1336 * set the sbic into non-DMA mode 1337 */ 1338 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1339 1340 dev->sc_stat[0] = 0xff; 1341 dev->sc_msg[0] = 0xff; 1342 1343 /* 1344 * We're stealing the SCSI bus 1345 */ 1346 dev->sc_flags |= SBICF_ICMD; 1347 1348 do { 1349 GET_SBIC_asr (regs, asr); 1350 1351 /* 1352 * select the SCSI bus (it's an error if bus isn't free) 1353 */ 1354 if ( (dev->sc_flags & SBICF_SELECTED) == 0 ) { 1355 if ( (csr = sbicselectbus(dev)) == 0 ) { 1356 dev->sc_flags &= ~SBICF_ICMD; 1357 return(-1); 1358 } 1359 } else 1360 GET_SBIC_csr(regs, csr); 1361 1362 QPRINTF((">ASR:0x%02x CSR:0x%02x <", asr, csr)); 1363 1364 switch ( csr ) { 1365 1366 case SBIC_CSR_S_XFERRED: 1367 case SBIC_CSR_DISC: 1368 case SBIC_CSR_DISC_1: 1369 { 1370 u_char phase; 1371 1372 dev->sc_flags &= ~SBICF_SELECTED; 1373 GET_SBIC_cmd_phase (regs, phase); 1374 1375 if ( phase == 0x60 ) { 1376 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1377 still_busy = 0; /* done */ 1378 } else { 1379 #ifdef DEBUG 1380 if ( reselect_debug > 1 ) 1381 printf("sbicicmd: handling disconnect\n"); 1382 #endif 1383 still_busy = SBIC_STATE_DISCONNECT; 1384 } 1385 } 1386 break; 1387 1388 case SBIC_CSR_XFERRED | CMD_PHASE: 1389 case SBIC_CSR_MIS | CMD_PHASE: 1390 case SBIC_CSR_MIS_1 | CMD_PHASE: 1391 case SBIC_CSR_MIS_2 | CMD_PHASE: 1392 { 1393 if ( sbicxfout(regs, clen, cbuf) ) 1394 still_busy = sbicabort(dev, "icmd sending cmd"); 1395 } 1396 break; 1397 1398 case SBIC_CSR_XFERRED | STATUS_PHASE: 1399 case SBIC_CSR_MIS | STATUS_PHASE: 1400 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1401 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1402 { 1403 /* 1404 * The sbic does the status/cmd-complete reading ok, 1405 * so do this with its hi-level commands. 1406 */ 1407 #ifdef DEBUG 1408 if ( sbic_debug ) 1409 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1410 #endif 1411 SET_SBIC_cmd_phase(regs, 0x46); 1412 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1413 } 1414 break; 1415 1416 default: 1417 { 1418 still_busy = sbicnextstate(dev, csr, asr); 1419 } 1420 break; 1421 } 1422 1423 /* 1424 * make sure the last command was taken, 1425 * ie. we're not hunting after an ignored command.. 1426 */ 1427 GET_SBIC_asr(regs, asr); 1428 1429 /* 1430 * tapes may take a loooong time.. 1431 */ 1432 while (asr & SBIC_ASR_BSY ) { 1433 1434 if ( asr & SBIC_ASR_DBR ) { 1435 int i; 1436 1437 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1438 #ifdef DDB 1439 Debugger(); 1440 #endif 1441 /* 1442 * SBIC is jammed 1443 * DUNNO which direction 1444 * Try old direction 1445 */ 1446 GET_SBIC_data(regs, i); 1447 GET_SBIC_asr(regs, asr); 1448 1449 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1450 SET_SBIC_data(regs, i); 1451 } 1452 1453 GET_SBIC_asr(regs, asr); 1454 } 1455 1456 /* 1457 * wait for last command to complete 1458 */ 1459 if ( asr & SBIC_ASR_LCI ) { 1460 printf("sbicicmd: last command ignored\n"); 1461 } 1462 else 1463 if ( still_busy == 1 ) /* Bsy */ 1464 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1465 1466 /* 1467 * do it again 1468 */ 1469 } while ( still_busy > 0 && dev->sc_stat[0] == 0xff ); 1470 1471 /* 1472 * Sometimes we need to do an extra read of the CSR 1473 */ 1474 GET_SBIC_csr(regs, csr); 1475 1476 #ifdef DEBUG 1477 if ( data_pointer_debug > 1 ) 1478 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1479 acb->sc_kv.dc_count, 1480 dev->sc_stat[0]); 1481 #endif 1482 1483 dev->sc_flags &= ~SBICF_ICMD; 1484 1485 return(dev->sc_stat[0]); 1486 } 1487 1488 /* 1489 * Finish SCSI xfer command: After the completion interrupt from 1490 * a read/write operation, sequence through the final phases in 1491 * programmed i/o. This routine is a lot like sbicicmd except we 1492 * skip (and don't allow) the select, cmd out and data in/out phases. 1493 */ 1494 void 1495 sbicxfdone(dev) 1496 struct sbic_softc *dev; 1497 { 1498 sbic_regmap_p regs = dev->sc_sbicp; 1499 u_char phase, 1500 csr; 1501 int s; 1502 1503 QPRINTF(("{")); 1504 s = splbio(); 1505 1506 /* 1507 * have the sbic complete on its own 1508 */ 1509 SBIC_TC_PUT(regs, 0); 1510 SET_SBIC_cmd_phase(regs, 0x46); 1511 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1512 1513 do { 1514 1515 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1516 GET_SBIC_csr (regs, csr); 1517 QPRINTF(("%02x:", csr)); 1518 1519 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1520 (csr != SBIC_CSR_S_XFERRED)); 1521 1522 dev->sc_flags &= ~SBICF_SELECTED; 1523 1524 GET_SBIC_cmd_phase (regs, phase); 1525 QPRINTF(("}%02x", phase)); 1526 1527 if ( phase == 0x60 ) 1528 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1529 else 1530 sbicerror(dev, csr); 1531 1532 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1533 1534 splx(s); 1535 } 1536 1537 /* 1538 * No DMA chains 1539 */ 1540 int 1541 sbicgo(dev, xs) 1542 struct sbic_softc *dev; 1543 struct scsi_xfer *xs; 1544 { 1545 struct sbic_acb *acb = dev->sc_nexus; 1546 sbic_regmap_p regs = dev->sc_sbicp; 1547 int i, 1548 dmaflags, 1549 count, 1550 usedma; 1551 u_char csr, 1552 asr, 1553 *addr; 1554 1555 dev->target = xs->sc_link->target; 1556 dev->lun = xs->sc_link->lun; 1557 1558 usedma = sbicdmaok(dev, xs); 1559 1560 #ifdef DEBUG 1561 if ( data_pointer_debug > 1 ) 1562 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1563 #endif 1564 1565 /* 1566 * select the SCSI bus (it's an error if bus isn't free) 1567 */ 1568 if ( (csr = sbicselectbus(dev)) == 0 ) 1569 return(0); /* Not done: needs to be rescheduled */ 1570 1571 dev->sc_stat[0] = 0xff; 1572 1573 /* 1574 * Calculate DMA chains now 1575 */ 1576 if ( acb->flags & ACB_DATAIN ) 1577 dmaflags = DMAGO_READ; 1578 else 1579 dmaflags = 0; 1580 1581 addr = acb->sc_kv.dc_addr; 1582 count = acb->sc_kv.dc_count; 1583 1584 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1585 printf("sbic: DMA buffer mapping changed %x->%x\n", 1586 acb->sc_pa.dc_addr, kvtop(addr)); 1587 #ifdef DDB 1588 Debugger(); 1589 #endif 1590 } 1591 1592 #ifdef DEBUG 1593 ++sbicdma_ops; /* count total DMA operations */ 1594 #endif 1595 1596 /* 1597 * Allocate the DMA chain 1598 * Mark end of segment... 1599 */ 1600 acb->sc_tcnt = dev->sc_tcnt = 0; 1601 acb->sc_pa.dc_count = 0; 1602 1603 sbic_load_ptrs(dev); 1604 1605 /* 1606 * Enable interrupts but don't do any DMA 1607 * enintr() also enables interrupts for the sbic 1608 */ 1609 dev->sc_enintr(dev); 1610 1611 if ( usedma ) { 1612 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1613 acb->sc_pa.dc_count, dmaflags); 1614 #ifdef DEBUG 1615 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1616 #endif 1617 } else 1618 dev->sc_dmacmd = 0; /* Don't use DMA */ 1619 1620 acb->sc_dmacmd = dev->sc_dmacmd; 1621 1622 #ifdef DEBUG 1623 if ( data_pointer_debug > 1 ) { 1624 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1625 dev->sc_cur->dc_addr, 1626 dev->sc_tcnt, 1627 dev->sc_dmacmd); 1628 } 1629 #endif 1630 1631 /* 1632 * Lets cycle a while then let the interrupt handler take over. 1633 */ 1634 GET_SBIC_asr(regs, asr); 1635 1636 do { 1637 1638 QPRINTF(("go ")); 1639 1640 /* 1641 * Handle the new phase 1642 */ 1643 i = sbicnextstate(dev, csr, asr); 1644 #if 0 1645 WAIT_CIP(regs); 1646 #endif 1647 if ( i == SBIC_STATE_RUNNING ) { 1648 GET_SBIC_asr(regs, asr); 1649 1650 if ( asr & SBIC_ASR_LCI ) 1651 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1652 1653 if ( asr & SBIC_ASR_INT ) 1654 GET_SBIC_csr(regs, csr); 1655 } 1656 1657 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1658 1659 if ( i == SBIC_STATE_DONE ) { 1660 if ( dev->sc_stat[0] == 0xff ) 1661 #if 0 1662 printf("sbicgo: done & stat = 0xff\n"); 1663 #else 1664 ; 1665 #endif 1666 else 1667 return 1; /* Did we really finish that fast? */ 1668 } 1669 1670 return 0; 1671 } 1672 1673 1674 int 1675 sbicintr(dev) 1676 struct sbic_softc *dev; 1677 { 1678 sbic_regmap_p regs = dev->sc_sbicp; 1679 u_char asr, 1680 csr; 1681 int i; 1682 1683 /* 1684 * pending interrupt? 1685 */ 1686 GET_SBIC_asr (regs, asr); 1687 if ( (asr & SBIC_ASR_INT) == 0 ) 1688 return(0); 1689 1690 do { 1691 1692 if ( asr & SBIC_ASR_INT ) 1693 GET_SBIC_csr(regs, csr); 1694 1695 QPRINTF(("intr[0x%x]", csr)); 1696 1697 i = sbicnextstate(dev, csr, asr); 1698 #if 0 1699 WAIT_CIP(regs); 1700 #endif 1701 GET_SBIC_asr(regs, asr); 1702 1703 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1704 1705 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1706 1707 return(1); 1708 } 1709 1710 /* 1711 * Run commands and wait for disconnect. 1712 * This is only ever called when a command is in progress, when we 1713 * want to busy wait for it to finish. 1714 */ 1715 int 1716 sbicpoll(dev) 1717 struct sbic_softc *dev; 1718 { 1719 sbic_regmap_p regs = dev->sc_sbicp; 1720 u_char asr, 1721 csr; 1722 int i; 1723 1724 /* 1725 * Wait for the next interrupt 1726 */ 1727 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1728 1729 do { 1730 GET_SBIC_asr (regs, asr); 1731 1732 if ( asr & SBIC_ASR_INT ) 1733 GET_SBIC_csr(regs, csr); 1734 1735 QPRINTF(("poll[0x%x]", csr)); 1736 1737 /* 1738 * Handle it 1739 */ 1740 i = sbicnextstate(dev, csr, asr); 1741 1742 WAIT_CIP(regs); 1743 GET_SBIC_asr(regs, asr); 1744 1745 /* 1746 * tapes may take a loooong time.. 1747 */ 1748 while ( asr & SBIC_ASR_BSY ) { 1749 1750 if ( asr & SBIC_ASR_DBR ) { 1751 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1752 #ifdef DDB 1753 Debugger(); 1754 #endif 1755 /* 1756 * SBIC is jammed 1757 * DUNNO which direction 1758 * Try old direction 1759 */ 1760 GET_SBIC_data(regs, i); 1761 GET_SBIC_asr(regs, asr); 1762 1763 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1764 SET_SBIC_data(regs, i); 1765 } 1766 1767 GET_SBIC_asr(regs, asr); 1768 } 1769 1770 if ( asr & SBIC_ASR_LCI ) 1771 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1772 else 1773 if ( i == 1 ) /* BSY */ 1774 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1775 1776 } while ( i == SBIC_STATE_RUNNING ); 1777 1778 return(1); 1779 } 1780 1781 /* 1782 * Handle a single msgin 1783 */ 1784 int 1785 sbicmsgin(dev) 1786 struct sbic_softc *dev; 1787 { 1788 sbic_regmap_p regs = dev->sc_sbicp; 1789 int recvlen = 1; 1790 u_char asr, 1791 csr, 1792 *tmpaddr, 1793 *msgaddr; 1794 1795 tmpaddr = msgaddr = dev->sc_msg; 1796 1797 tmpaddr[0] = 0xff; 1798 tmpaddr[1] = 0xff; 1799 1800 GET_SBIC_asr(regs, asr); 1801 1802 #ifdef DEBUG 1803 if ( reselect_debug > 1 ) 1804 printf("sbicmsgin asr=%02x\n", asr); 1805 #endif 1806 1807 GET_SBIC_selid (regs, csr); 1808 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1809 1810 SBIC_TC_PUT(regs, 0); 1811 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1812 1813 do { 1814 while( recvlen-- ) { 1815 1816 /* 1817 * Fetch the next byte of the message 1818 */ 1819 RECV_BYTE(regs, *tmpaddr); 1820 1821 /* 1822 * get the command completion interrupt, or we 1823 * can't send a new command (LCI) 1824 */ 1825 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1826 GET_SBIC_csr(regs, csr); 1827 1828 #ifdef DEBUG 1829 if ( reselect_debug > 1 ) 1830 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1831 #endif 1832 1833 tmpaddr++; 1834 1835 if ( recvlen ) { 1836 /* 1837 * Clear ACK, and wait for the interrupt for the next byte 1838 */ 1839 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1840 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1841 GET_SBIC_csr(regs, csr); 1842 } 1843 } 1844 1845 if ( msgaddr[0] == 0xff ) { 1846 printf("sbicmsgin: sbic swallowed our message\n"); 1847 break; 1848 } 1849 1850 #ifdef DEBUG 1851 if ( sync_debug ) { 1852 GET_SBIC_asr(regs, asr); 1853 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1854 } 1855 #endif 1856 /* 1857 * test whether this is a reply to our sync 1858 * request 1859 */ 1860 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1861 1862 /* 1863 * Got IFFY msg -- ack it 1864 */ 1865 QPRINTF(("IFFY")); 1866 1867 } else 1868 if ( msgaddr[0] == MSG_REJECT && 1869 dev->sc_sync[dev->target].state == SYNC_SENT) { 1870 1871 /* 1872 * Target probably rejected our Sync negotiation. 1873 */ 1874 QPRINTF(("REJECT of SYN")); 1875 1876 #ifdef DEBUG 1877 if ( sync_debug ) 1878 printf("target %d rejected sync, going async\n", dev->target); 1879 #endif 1880 1881 dev->sc_sync[dev->target].period = sbic_min_period; 1882 dev->sc_sync[dev->target].offset = 0; 1883 dev->sc_sync[dev->target].state = SYNC_DONE; 1884 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1885 dev->sc_sync[dev->target].period)); 1886 1887 } else 1888 if ( msgaddr[0] == MSG_REJECT ) { 1889 1890 /* 1891 * we'll never REJECt a REJECT message.. 1892 */ 1893 QPRINTF(("REJECT")); 1894 1895 } else 1896 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1897 1898 /* 1899 * don't reject this either. 1900 */ 1901 QPRINTF(("MSG_SAVE_DATA_PTR")); 1902 1903 } else 1904 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1905 1906 /* 1907 * don't reject this either. 1908 */ 1909 QPRINTF(("MSG_RESTORE_PTR")); 1910 1911 } else 1912 if ( msgaddr[0] == MSG_DISCONNECT ) { 1913 1914 /* 1915 * Target is disconnecting... 1916 */ 1917 QPRINTF(("DISCONNECT")); 1918 1919 #ifdef DEBUG 1920 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1921 printf("sbicmsgin: got disconnect msg %s\n", 1922 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1923 #endif 1924 1925 if ( dev->sc_flags & SBICF_ICMD ) { 1926 /* 1927 * We're in immediate mode. Prevent disconnects. 1928 * prepare to reject the message, NACK 1929 */ 1930 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1931 WAIT_CIP(regs); 1932 } 1933 1934 } else 1935 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1936 1937 /* 1938 * !! KLUDGE ALERT !! quite a few drives don't seem to 1939 * really like the current way of sending the 1940 * sync-handshake together with the ident-message, and 1941 * they react by sending command-complete and 1942 * disconnecting right after returning the valid sync 1943 * handshake. So, all I can do is reselect the drive, 1944 * and hope it won't disconnect again. I don't think 1945 * this is valid behavior, but I can't help fixing a 1946 * problem that apparently exists. 1947 * 1948 * Note: we should not get here on `normal' command 1949 * completion, as that condition is handled by the 1950 * high-level sel&xfer resume command used to walk 1951 * thru status/cc-phase. 1952 */ 1953 QPRINTF(("CMD_COMPLETE")); 1954 1955 #ifdef DEBUG 1956 if ( sync_debug ) 1957 printf ("GOT MSG %d! target %d acting weird.." 1958 " waiting for disconnect...\n", msgaddr[0], dev->target); 1959 #endif 1960 1961 /* 1962 * Check to see if sbic is handling this 1963 */ 1964 GET_SBIC_asr(regs, asr); 1965 1966 /* 1967 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1968 */ 1969 if ( asr & SBIC_ASR_BSY ) 1970 return SBIC_STATE_RUNNING; 1971 1972 /* 1973 * Let's try this: Assume it works and set status to 00 1974 */ 1975 dev->sc_stat[0] = 0; 1976 1977 } else 1978 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 1979 1980 /* 1981 * Target is sending us an extended message. We'll assume it's 1982 * the response to our Sync. negotiation. 1983 */ 1984 QPRINTF(("ExtMSG\n")); 1985 1986 /* 1987 * Read in whole extended message. First, negate ACK to accept 1988 * the MSG_EXT_MESSAGE byte... 1989 */ 1990 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1991 1992 /* 1993 * Wait for the interrupt for the next byte (length) 1994 */ 1995 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1996 GET_SBIC_csr(regs, csr); 1997 1998 #ifdef DEBUG 1999 QPRINTF(("CLR ACK csr %02x\n", csr)); 2000 #endif 2001 2002 /* 2003 * Read the length byte 2004 */ 2005 RECV_BYTE(regs, *tmpaddr); 2006 2007 /* 2008 * Wait for command completion IRQ 2009 */ 2010 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2011 GET_SBIC_csr(regs, csr); 2012 2013 /* 2014 * Reload the loop counter 2015 */ 2016 recvlen = *tmpaddr++; 2017 2018 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2019 2020 } else 2021 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2022 msgaddr[2] == MSG_SYNC_REQ ) { 2023 2024 /* 2025 * We've received the complete Extended Message Sync. Request... 2026 */ 2027 QPRINTF(("SYN")); 2028 2029 /* 2030 * Compute the required Transfer Period for the WD chip... 2031 */ 2032 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2033 dev->sc_sync[dev->target].offset = msgaddr[4]; 2034 dev->sc_sync[dev->target].state = SYNC_DONE; 2035 2036 /* 2037 * Put the WD chip in synchronous mode 2038 */ 2039 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2040 dev->sc_sync[dev->target].period)); 2041 2042 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2043 dev->sc_dev.dv_xname, dev->target, 2044 msgaddr[3] * 4, msgaddr[4]); 2045 2046 } else { 2047 2048 /* 2049 * We don't support whatever this message is... 2050 */ 2051 #ifdef DEBUG 2052 if ( sbic_debug || sync_debug ) 2053 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2054 #endif 2055 2056 /* 2057 * prepare to reject the message, NACK 2058 */ 2059 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2060 WAIT_CIP(regs); 2061 } 2062 2063 /* 2064 * Negate ACK to complete the transfer 2065 */ 2066 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2067 2068 /* 2069 * Wait for the interrupt for the next byte, or phase change. 2070 * Only read the CSR if we have more data to transfer. 2071 * XXXSCW: We should really verify that we're still in MSG IN phase 2072 * before blindly going back around this loop, but that would mean 2073 * we read the CSR... <sigh> 2074 */ 2075 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2076 if ( recvlen > 0 ) 2077 GET_SBIC_csr(regs, csr); 2078 2079 } while ( recvlen > 0 ); 2080 2081 /* 2082 * Should still have one CSR to read 2083 */ 2084 return SBIC_STATE_RUNNING; 2085 } 2086 2087 2088 /* 2089 * sbicnextstate() 2090 * return: 2091 * 0 == done 2092 * 1 == working 2093 * 2 == disconnected 2094 * -1 == error 2095 */ 2096 int 2097 sbicnextstate(dev, csr, asr) 2098 struct sbic_softc *dev; 2099 u_char csr, 2100 asr; 2101 { 2102 sbic_regmap_p regs = dev->sc_sbicp; 2103 struct sbic_acb *acb = dev->sc_nexus; 2104 2105 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2106 2107 switch (csr) { 2108 2109 case SBIC_CSR_XFERRED | CMD_PHASE: 2110 case SBIC_CSR_MIS | CMD_PHASE: 2111 case SBIC_CSR_MIS_1 | CMD_PHASE: 2112 case SBIC_CSR_MIS_2 | CMD_PHASE: 2113 { 2114 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2115 goto abort; 2116 } 2117 break; 2118 2119 case SBIC_CSR_XFERRED | STATUS_PHASE: 2120 case SBIC_CSR_MIS | STATUS_PHASE: 2121 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2122 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2123 { 2124 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2125 2126 /* 2127 * this should be the normal i/o completion case. 2128 * get the status & cmd complete msg then let the 2129 * device driver look at what happened. 2130 */ 2131 sbicxfdone(dev); 2132 2133 #ifdef DEBUG 2134 dev->sc_dmatimo = 0; 2135 if ( data_pointer_debug > 1 ) 2136 printf("next dmastop: %d(%x:%x)\n", dev->target, 2137 dev->sc_cur->dc_addr, 2138 dev->sc_tcnt); 2139 #endif 2140 /* 2141 * Stop the DMA chip 2142 */ 2143 dev->sc_dmastop(dev); 2144 2145 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2146 2147 /* 2148 * Indicate to the upper layers that the command is done 2149 */ 2150 sbic_scsidone(acb, dev->sc_stat[0]); 2151 2152 return SBIC_STATE_DONE; 2153 } 2154 2155 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2156 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2157 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2158 case SBIC_CSR_MIS | DATA_IN_PHASE: 2159 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2160 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2161 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2162 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2163 { 2164 /* 2165 * Verify that we expected to transfer data... 2166 */ 2167 if ( acb->sc_kv.dc_count <= 0 ) { 2168 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2169 acb->sc_kv.dc_count, asr, csr); 2170 goto abort; 2171 } 2172 2173 /* 2174 * Should we transfer using PIO or DMA ? 2175 */ 2176 if ( dev->sc_xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2177 acb->sc_dmacmd == 0 ) { 2178 2179 /* 2180 * Do PIO transfer 2181 */ 2182 int i; 2183 2184 #ifdef DEBUG 2185 if ( data_pointer_debug > 1 ) 2186 printf("next PIO: %d(%x:%x)\n", dev->target, 2187 acb->sc_kv.dc_addr, 2188 acb->sc_kv.dc_count); 2189 #endif 2190 2191 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2192 /* 2193 * data in 2194 */ 2195 i = sbicxfin(regs, acb->sc_kv.dc_count, 2196 acb->sc_kv.dc_addr); 2197 else 2198 /* 2199 * data out 2200 */ 2201 i = sbicxfout(regs, acb->sc_kv.dc_count, 2202 acb->sc_kv.dc_addr); 2203 2204 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2205 acb->sc_kv.dc_count = i; 2206 2207 /* 2208 * Update current count... 2209 */ 2210 acb->sc_tcnt = dev->sc_tcnt = i; 2211 2212 dev->sc_flags &= ~SBICF_INDMA; 2213 2214 } else { 2215 2216 /* 2217 * Do DMA transfer 2218 * set next dma addr and dec count 2219 */ 2220 sbic_save_ptrs(dev); 2221 sbic_load_ptrs(dev); 2222 2223 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2224 SBIC_MACHINE_DMA_MODE); 2225 2226 #ifdef DEBUG 2227 dev->sc_dmatimo = 1; 2228 if ( data_pointer_debug > 1 ) 2229 printf("next DMA: %d(%x:%x)\n", dev->target, 2230 dev->sc_cur->dc_addr, 2231 dev->sc_tcnt); 2232 #endif 2233 /* 2234 * Start the DMA chip going 2235 */ 2236 dev->sc_tcnt = dev->sc_dmanext(dev); 2237 2238 /* 2239 * Tell the WD chip how much to transfer this time around 2240 */ 2241 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2242 2243 /* 2244 * Start the transfer 2245 */ 2246 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2247 2248 /* 2249 * Indicate that we're in DMA mode 2250 */ 2251 dev->sc_flags |= SBICF_INDMA; 2252 } 2253 } 2254 break; 2255 2256 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2257 case SBIC_CSR_MIS | MESG_IN_PHASE: 2258 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2259 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2260 { 2261 sbic_save_ptrs(dev); 2262 2263 /* 2264 * Handle a single message in... 2265 */ 2266 return sbicmsgin(dev); 2267 } 2268 2269 case SBIC_CSR_MSGIN_W_ACK: 2270 { 2271 /* 2272 * We should never see this since it's handled in 'sbicmsgin()' 2273 * but just for the sake of paranoia... 2274 */ 2275 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2276 printf("Acking unknown msgin CSR:%02x",csr); 2277 } 2278 break; 2279 2280 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2281 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2282 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2283 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2284 { 2285 /* 2286 * We only ever handle a message out phase here for sending a 2287 * REJECT message. 2288 */ 2289 sbic_save_ptrs(dev); 2290 2291 #ifdef DEBUG 2292 if (sync_debug) 2293 printf ("sending REJECT msg to last msg.\n"); 2294 #endif 2295 2296 SEND_BYTE(regs, MSG_REJECT); 2297 WAIT_CIP(regs); 2298 } 2299 break; 2300 2301 case SBIC_CSR_DISC: 2302 case SBIC_CSR_DISC_1: 2303 { 2304 /* 2305 * Try to schedule another target 2306 */ 2307 sbic_save_ptrs(dev); 2308 2309 dev->sc_flags &= ~SBICF_SELECTED; 2310 2311 #ifdef DEBUG 2312 if ( reselect_debug > 1 ) 2313 printf("sbicnext target %d disconnected\n", dev->target); 2314 #endif 2315 2316 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2317 2318 ++dev->sc_tinfo[dev->target].dconns; 2319 2320 dev->sc_nexus = NULL; 2321 dev->sc_xs = NULL; 2322 2323 if ( acb->xs->flags & SCSI_POLL || dev->sc_flags & SBICF_ICMD || 2324 !sbic_parallel_operations ) 2325 return SBIC_STATE_DISCONNECT; 2326 2327 QPRINTF(("sbicnext: calling sbic_sched\n")); 2328 2329 sbic_sched(dev); 2330 2331 QPRINTF(("sbicnext: sbic_sched returned\n")); 2332 2333 return SBIC_STATE_DISCONNECT; 2334 } 2335 2336 case SBIC_CSR_RSLT_NI: 2337 case SBIC_CSR_RSLT_IFY: 2338 { 2339 /* 2340 * A reselection. 2341 * Note that since we don't enable Advanced Features (assuming 2342 * the WD chip is at least the 'A' revision), we're only ever 2343 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2344 * hell of it, we'll handle it anyway, for all the extra code 2345 * it needs... 2346 */ 2347 u_char newtarget, 2348 newlun; 2349 2350 GET_SBIC_rselid(regs, newtarget); 2351 2352 /* 2353 * check SBIC_RID_SIV? 2354 */ 2355 newtarget &= SBIC_RID_MASK; 2356 2357 if ( csr == SBIC_CSR_RSLT_IFY ) { 2358 2359 /* 2360 * Read Identify msg to avoid lockup 2361 */ 2362 GET_SBIC_data(regs, newlun); 2363 WAIT_CIP(regs); 2364 newlun &= SBIC_TLUN_MASK; 2365 2366 } else { 2367 2368 /* 2369 * Need to read Identify message the hard way, assuming 2370 * the target even sends us one... 2371 */ 2372 for (newlun = 255; newlun; --newlun) { 2373 GET_SBIC_asr(regs, asr); 2374 if (asr & SBIC_ASR_INT) 2375 break; 2376 delay(1); 2377 } 2378 2379 /* 2380 * If we didn't get an interrupt, somethink's up 2381 */ 2382 if ( (asr & SBIC_ASR_INT) == 0 ) { 2383 #ifdef DEBUG 2384 if ( reselect_debug ) 2385 printf("RSLT_NI - no IFFY message? asr %x\n", asr); 2386 #endif 2387 newlun = 0; /* XXXX */ 2388 2389 } else { 2390 /* 2391 * We got an interrupt, verify that it's a change to 2392 * message in phase, and if so read the message. 2393 */ 2394 GET_SBIC_csr(regs,csr); 2395 2396 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2397 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2398 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2399 /* 2400 * Yup, gone to message in. Fetch the target LUN 2401 */ 2402 sbicmsgin(dev); 2403 newlun = dev->sc_msg[0] & 0x07; 2404 2405 } else { 2406 /* 2407 * Whoops! Target didn't go to message in phase!! 2408 */ 2409 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2410 newlun = 0; /* XXXSCW */ 2411 } 2412 } 2413 } 2414 2415 /* 2416 * Ok, we have the identity of the reselecting target. 2417 */ 2418 #ifdef DEBUG 2419 if ( reselect_debug > 1 || 2420 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2421 printf("sbicnext: reselect %s from targ %d lun %d\n", 2422 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2423 } 2424 #endif 2425 2426 if ( dev->sc_nexus ) { 2427 /* 2428 * Whoops! We've been reselected with an command in progress! 2429 * The best we can do is to put the current command back on the 2430 * ready list and hope for the best. 2431 */ 2432 #ifdef DEBUG 2433 if ( reselect_debug > 1 ) { 2434 printf("%s: reselect %s with active command\n", 2435 dev->sc_dev.dv_xname, 2436 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2437 } 2438 #endif 2439 2440 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2441 2442 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2443 2444 dev->sc_nexus = NULL; 2445 dev->sc_xs = NULL; 2446 } 2447 2448 /* 2449 * Reload sync values for this target 2450 */ 2451 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2452 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2453 dev->sc_sync[newtarget].period)); 2454 else 2455 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2456 2457 /* 2458 * Loop through the nexus list until we find the saved entry 2459 * for the reselecting target... 2460 */ 2461 for (acb = dev->nexus_list.tqh_first; acb; 2462 acb = acb->chain.tqe_next) { 2463 2464 if ( acb->xs->sc_link->target == newtarget && 2465 acb->xs->sc_link->lun == newlun) { 2466 /* 2467 * We've found the saved entry. Dequeue it, and 2468 * make it current again. 2469 */ 2470 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2471 2472 dev->sc_nexus = acb; 2473 dev->sc_xs = acb->xs; 2474 dev->sc_flags |= SBICF_SELECTED; 2475 dev->target = newtarget; 2476 dev->lun = newlun; 2477 break; 2478 } 2479 } 2480 2481 if ( acb == NULL ) { 2482 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2483 dev->sc_dev.dv_xname, 2484 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2485 &dev->nexus_list.tqh_first); 2486 panic("bad reselect in sbic"); 2487 } 2488 2489 if ( csr == SBIC_CSR_RSLT_IFY ) 2490 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2491 } 2492 break; 2493 2494 default: 2495 abort: 2496 { 2497 /* 2498 * Something unexpected happened -- deal with it. 2499 */ 2500 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2501 2502 #ifdef DDB 2503 Debugger(); 2504 #endif 2505 2506 #ifdef DEBUG 2507 dev->sc_dmatimo = 0; 2508 if ( data_pointer_debug > 1 ) 2509 printf("next dmastop: %d(%x:%x)\n", dev->target, 2510 dev->sc_cur->dc_addr, 2511 dev->sc_tcnt); 2512 #endif 2513 2514 dev->sc_dmastop(dev); 2515 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2516 if ( dev->sc_xs ) sbicerror(dev, csr); 2517 sbicabort(dev, "next"); 2518 2519 if ( dev->sc_flags & SBICF_INDMA ) { 2520 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2521 2522 #ifdef DEBUG 2523 dev->sc_dmatimo = 0; 2524 if ( data_pointer_debug > 1 ) 2525 printf("next dmastop: %d(%x:%x)\n", dev->target, 2526 dev->sc_cur->dc_addr, 2527 dev->sc_tcnt); 2528 #endif 2529 sbic_scsidone(acb, -1); 2530 } 2531 2532 return SBIC_STATE_ERROR; 2533 } 2534 } 2535 2536 return(SBIC_STATE_RUNNING); 2537 } 2538 2539 2540 /* 2541 * Check if DMA can not be used with specified buffer 2542 */ 2543 int 2544 sbiccheckdmap(bp, len, mask) 2545 void *bp; 2546 u_long len, 2547 mask; 2548 { 2549 u_char *buffer; 2550 u_long phy_buf; 2551 u_long phy_len; 2552 2553 buffer = bp; 2554 2555 if ( len == 0 ) 2556 return(1); 2557 2558 while ( len ) { 2559 2560 phy_buf = kvtop(buffer); 2561 phy_len = NBPG - ((int) buffer & PGOFSET); 2562 2563 if ( len < phy_len ) 2564 phy_len = len; 2565 2566 if ( phy_buf & mask ) 2567 return(1); 2568 2569 buffer += phy_len; 2570 len -= phy_len; 2571 } 2572 2573 return(0); 2574 } 2575 2576 int 2577 sbictoscsiperiod(dev, a) 2578 struct sbic_softc *dev; 2579 int a; 2580 { 2581 unsigned int fs; 2582 2583 /* 2584 * cycle = DIV / (2 * CLK) 2585 * DIV = FS + 2 2586 * best we can do is 200ns at 20Mhz, 2 cycles 2587 */ 2588 2589 GET_SBIC_myid(dev->sc_sbicp, fs); 2590 2591 fs = (fs >> 6) + 2; /* DIV */ 2592 2593 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2594 2595 if ( a < 2 ) 2596 a = 8; /* map to Cycles */ 2597 2598 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2599 } 2600 2601 int 2602 sbicfromscsiperiod(dev, p) 2603 struct sbic_softc *dev; 2604 int p; 2605 { 2606 unsigned fs, 2607 ret; 2608 2609 /* 2610 * Just the inverse of the above 2611 */ 2612 GET_SBIC_myid(dev->sc_sbicp, fs); 2613 2614 fs = (fs >> 6) + 2; /* DIV */ 2615 2616 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2617 2618 ret = p << 2; /* in ns units */ 2619 ret = ret / fs; /* in Cycles */ 2620 2621 if ( ret < sbic_min_period ) 2622 return(sbic_min_period); 2623 2624 /* 2625 * verify rounding 2626 */ 2627 if ( sbictoscsiperiod(dev, ret) < p ) 2628 ret++; 2629 2630 return( (ret >= 8) ? 0 : ret ); 2631 } 2632 2633 #ifdef DEBUG 2634 void 2635 sbictimeout(dev) 2636 struct sbic_softc *dev; 2637 { 2638 int s, 2639 asr; 2640 2641 s = splbio(); 2642 2643 if ( dev->sc_dmatimo ) { 2644 2645 if ( dev->sc_dmatimo > 1 ) { 2646 2647 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2648 dev->sc_dmatimo - 1); 2649 2650 GET_SBIC_asr(dev->sc_sbicp, asr); 2651 2652 if ( asr & SBIC_ASR_INT ) { 2653 /* 2654 * We need to service a missed IRQ 2655 */ 2656 sbicintr(dev); 2657 } 2658 } 2659 2660 dev->sc_dmatimo++; 2661 } 2662 2663 splx(s); 2664 2665 timeout((void *)sbictimeout, dev, 30 * hz); 2666 } 2667 #endif 2668
Indexes created Sun Sep 28 07:09:56 GMT 2025