sbic.c revision 1.10
1 /* $NetBSD: sbic.c,v 1.10 1999/09/30 23:01:12 thorpej Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 #include <vm/vm.h> 68 #include <vm/vm_kern.h> 69 #include <vm/vm_page.h> 70 #include <vm/pmap.h> 71 #include <machine/pmap.h> 72 #include <mvme68k/mvme68k/isr.h> 73 #include <mvme68k/dev/dmavar.h> 74 #include <mvme68k/dev/sbicreg.h> 75 #include <mvme68k/dev/sbicvar.h> 76 77 78 /* 79 * Since I can't find this in any other header files 80 */ 81 #define SCSI_PHASE(reg) (reg&0x07) 82 83 /* 84 * SCSI delays 85 * In u-seconds, primarily for state changes on the SPC. 86 */ 87 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 88 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 89 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 90 91 /* 92 * Convenience macro for waiting for a particular sbic event 93 */ 94 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 95 96 extern u_int kvtop(); 97 98 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 99 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 101 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 102 int sbiccheckdmap __P((void *, u_long, u_long)); 103 u_char sbicselectbus __P((struct sbic_softc *)); 104 int sbicxfout __P((sbic_regmap_p, int, void *)); 105 int sbicxfin __P((sbic_regmap_p, int, void *)); 106 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 107 int sbictoscsiperiod __P((struct sbic_softc *, int)); 108 int sbicintr __P((struct sbic_softc *)); 109 int sbicpoll __P((struct sbic_softc *)); 110 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 111 int sbicmsgin __P((struct sbic_softc *)); 112 int sbicabort __P((struct sbic_softc *, char *)); 113 void sbicxfdone __P((struct sbic_softc *)); 114 void sbicerror __P((struct sbic_softc *,u_char)); 115 void sbicreset __P((struct sbic_softc *)); 116 void sbic_scsidone __P((struct sbic_acb *, int)); 117 void sbic_sched __P((struct sbic_softc *)); 118 void sbic_save_ptrs __P((struct sbic_softc *)); 119 void sbic_load_ptrs __P((struct sbic_softc *)); 120 121 /* 122 * Synch xfer parameters, and timing conversions 123 */ 124 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 125 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 126 int sbic_cmd_wait = SBIC_CMD_WAIT; 127 int sbic_data_wait = SBIC_DATA_WAIT; 128 int sbic_init_wait = SBIC_INIT_WAIT; 129 130 /* 131 * was broken before.. now if you want this you get it for all drives 132 * on sbic controllers. 133 */ 134 u_char sbic_inhibit_sync[8]; 135 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 136 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 137 int sbic_parallel_operations = 1; /* Allow command queues */ 138 139 /* 140 * Some useful stuff for debugging purposes 141 */ 142 #ifdef DEBUG 143 int sbicdma_ops = 0; /* total DMA operations */ 144 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 145 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 146 int sbicdma_saves = 0; 147 148 #define QPRINTF(a) if (sbic_debug > 1) printf a 149 150 int sbic_debug = 0; /* Debug all chip related things */ 151 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 152 int reselect_debug = 0; /* Debug all reselection related things */ 153 int report_sense = 0; /* Always print Sense information */ 154 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 155 156 void sbictimeout __P((struct sbic_softc *dev)); 157 158 #else 159 #define QPRINTF(a) /* */ 160 #endif 161 162 163 /* 164 * default minphys routine for sbic based controllers 165 */ 166 void 167 sbic_minphys(bp) 168 struct buf *bp; 169 { 170 /* 171 * No max transfer at this level. 172 */ 173 minphys(bp); 174 } 175 176 177 /* 178 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 179 */ 180 void 181 sbic_save_ptrs(dev) 182 struct sbic_softc *dev; 183 { 184 sbic_regmap_p regs; 185 struct sbic_acb* acb; 186 int count, 187 asr, 188 s; 189 190 /* 191 * Only need to save pointers if DMA was active... 192 */ 193 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 194 return; 195 196 regs = dev->sc_sbicp; 197 198 s = splbio(); 199 200 /* 201 * Wait until WD chip is idle 202 */ 203 do { 204 GET_SBIC_asr(regs, asr); 205 if( asr & SBIC_ASR_DBR ) { 206 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 207 splx(s); 208 return; 209 } 210 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 211 212 213 /* 214 * Save important state. 215 * must be done before dmastop 216 */ 217 acb = dev->sc_nexus; 218 acb->sc_dmacmd = dev->sc_dmacmd; 219 220 /* 221 * Fetch the residual count 222 */ 223 SBIC_TC_GET(regs, count); 224 225 /* 226 * Shut down DMA 227 */ 228 dev->sc_dmastop(dev); 229 230 /* 231 * No longer in DMA 232 */ 233 dev->sc_flags &= ~SBICF_INDMA; 234 235 /* 236 * Ensure the WD chip is back in polled I/O mode, with nothing to 237 * transfer. 238 */ 239 SBIC_TC_PUT(regs, 0); 240 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 241 242 /* 243 * Update current count... 244 */ 245 acb->sc_tcnt = count; 246 247 /* 248 * Work out how many bytes were actually transferred 249 */ 250 count = dev->sc_tcnt - count; 251 dev->sc_tcnt = acb->sc_tcnt; 252 253 /* 254 * Fixup partial xfers 255 */ 256 acb->sc_kv.dc_addr += count; 257 acb->sc_kv.dc_count -= count; 258 acb->sc_pa.dc_addr += count; 259 acb->sc_pa.dc_count -= count >> 1; 260 261 #ifdef DEBUG 262 if ( data_pointer_debug ) 263 printf("save at (%x,%x):%x\n", 264 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 265 sbicdma_saves++; 266 #endif 267 268 splx(s); 269 } 270 271 272 /* 273 * DOES NOT RESTART DMA!!! 274 */ 275 void 276 sbic_load_ptrs(dev) 277 struct sbic_softc *dev; 278 { 279 struct sbic_acb *acb = dev->sc_nexus; 280 int s; 281 282 if ( acb->sc_kv.dc_count == 0 ) { 283 /* 284 * No data to xfer 285 */ 286 return; 287 } 288 289 s = splbio(); 290 291 /* 292 * Reset the Scatter-Gather chain 293 */ 294 dev->sc_last = dev->sc_cur = &acb->sc_pa; 295 296 /* 297 * Restore the Transfer Count and DMA specific data 298 */ 299 dev->sc_tcnt = acb->sc_tcnt; 300 dev->sc_dmacmd = acb->sc_dmacmd; 301 302 #ifdef DEBUG 303 sbicdma_ops++; 304 #endif 305 306 /* 307 * Need to fixup new segment? 308 */ 309 if ( dev->sc_tcnt == 0 ) { 310 /* 311 * sc_tcnt == 0 implies end of segment 312 */ 313 char *vaddr, *paddr; 314 int count; 315 316 /* 317 * do kvm to pa mappings 318 */ 319 vaddr = acb->sc_kv.dc_addr; 320 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 321 322 for (count = (NBPG - ((int)vaddr & PGOFSET)); 323 count < acb->sc_kv.dc_count && 324 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 325 count += NBPG) 326 ; /* Do nothing */ 327 328 /* 329 * If it's all contiguous... 330 */ 331 if ( count > acb->sc_kv.dc_count ) { 332 count = acb->sc_kv.dc_count; 333 #ifdef DEBUG 334 sbicdma_hits++; 335 #endif 336 } 337 #ifdef DEBUG 338 else 339 sbicdma_misses++; 340 #endif 341 342 acb->sc_tcnt = count; 343 acb->sc_pa.dc_count = count >> 1; 344 345 #ifdef DEBUG 346 if ( data_pointer_debug ) 347 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 348 acb->sc_kv.dc_count, 349 acb->sc_pa.dc_addr, 350 acb->sc_tcnt); 351 #endif 352 353 } 354 355 splx(s); 356 } 357 358 /* 359 * used by specific sbic controller 360 * 361 * it appears that the higher level code does nothing with LUN's 362 * so I will too. I could plug it in, however so could they 363 * in scsi_scsipi_cmd(). 364 */ 365 int 366 sbic_scsicmd(xs) 367 struct scsipi_xfer *xs; 368 { 369 struct scsipi_link *slp = xs->sc_link; 370 struct sbic_softc *dev = slp->adapter_softc; 371 struct sbic_acb *acb; 372 int flags = xs->xs_control, 373 s; 374 375 if ( flags & XS_CTL_DATA_UIO ) 376 panic("sbic: scsi data uio requested"); 377 378 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 379 panic("sbic_scsicmd: busy"); 380 381 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 382 return ESCAPE_NOT_SUPPORTED; 383 384 s = splbio(); 385 386 if ( (acb = dev->free_list.tqh_first) != NULL ) 387 TAILQ_REMOVE(&dev->free_list, acb, chain); 388 389 splx(s); 390 391 if ( acb == NULL ) { 392 #ifdef DEBUG 393 printf("sbic_scsicmd: unable to queue request for target %d\n", 394 slp->scsipi_scsi.target); 395 #ifdef DDB 396 Debugger(); 397 #endif 398 #endif 399 xs->error = XS_DRIVER_STUFFUP; 400 401 return(TRY_AGAIN_LATER); 402 } 403 404 if ( flags & XS_CTL_DATA_IN ) 405 acb->flags = ACB_ACTIVE | ACB_DATAIN; 406 else 407 acb->flags = ACB_ACTIVE; 408 409 acb->xs = xs; 410 acb->clen = xs->cmdlen; 411 acb->sc_kv.dc_addr = xs->data; 412 acb->sc_kv.dc_count = xs->datalen; 413 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 414 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 415 416 if ( flags & XS_CTL_POLL ) { 417 /* 418 * This has major side effects -- it locks up the machine 419 */ 420 int stat; 421 422 s = splbio(); 423 424 dev->sc_flags |= SBICF_ICMD; 425 426 do { 427 /* 428 * If we already had a nexus, while away the time until idle... 429 * This is likely only to happen if a reselection occurs between 430 * here and our earlier check for ICMD && sc_nexus (which would 431 * have resulted in a panic() had it been true). 432 */ 433 while ( dev->sc_nexus ) 434 sbicpoll(dev); 435 436 /* 437 * Fix up the new nexus 438 */ 439 dev->sc_nexus = acb; 440 dev->sc_xs = xs; 441 dev->target = slp->scsipi_scsi.target; 442 dev->lun = slp->scsipi_scsi.lun; 443 444 stat = sbicicmd(dev, &acb->cmd, acb->clen, 445 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 446 447 } while ( dev->sc_nexus != acb ); 448 449 sbic_scsidone(acb, stat); 450 451 splx(s); 452 453 return(COMPLETE); 454 } 455 456 s = splbio(); 457 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 458 459 /* 460 * If nothing is active, try to start it now. 461 */ 462 if ( dev->sc_nexus == NULL ) 463 sbic_sched(dev); 464 465 splx(s); 466 467 return(SUCCESSFULLY_QUEUED); 468 } 469 470 /* 471 * attempt to start the next available command 472 */ 473 void 474 sbic_sched(dev) 475 struct sbic_softc *dev; 476 { 477 struct scsipi_xfer *xs; 478 struct scsipi_link *slp = NULL; /* Gag the compiler */ 479 struct sbic_acb *acb; 480 int flags, 481 stat; 482 483 /* 484 * XXXSCW 485 * I'll keep this test here, even though I can't see any obvious way 486 * in which sbic_sched() could be called with sc_nexus non NULL 487 */ 488 if ( dev->sc_nexus ) 489 return; /* a command is current active */ 490 491 /* 492 * Loop through the ready list looking for work to do... 493 */ 494 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 495 int i, j; 496 497 slp = acb->xs->sc_link; 498 i = slp->scsipi_scsi.target; 499 j = 1 << slp->scsipi_scsi.lun; 500 501 /* 502 * We've found a potential command, but is the target/lun busy? 503 */ 504 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 505 /* 506 * Nope, it's not busy, so we can use it. 507 */ 508 dev->sc_tinfo[i].lubusy |= j; 509 TAILQ_REMOVE(&dev->ready_list, acb, chain); 510 dev->sc_nexus = acb; 511 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 512 break; 513 } 514 } 515 516 if ( acb == NULL ) { 517 QPRINTF(("sbicsched: no work\n")); 518 return; /* did not find an available command */ 519 } 520 521 #ifdef DEBUG 522 if ( data_pointer_debug > 1 ) 523 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 524 slp->scsipi_scsi.lun); 525 #endif 526 527 dev->sc_xs = xs = acb->xs; 528 flags = xs->xs_control; 529 530 if ( flags & XS_CTL_RESET ) 531 sbicreset(dev); 532 533 dev->sc_stat[0] = -1; 534 dev->target = slp->scsipi_scsi.target; 535 dev->lun = slp->scsipi_scsi.lun; 536 537 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 538 (sbicdmaok(dev, xs) == 0)) ) 539 stat = sbicicmd(dev, &acb->cmd, acb->clen, 540 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 541 else 542 if ( sbicgo(dev, xs) == 0 ) 543 return; 544 else 545 stat = dev->sc_stat[0]; 546 547 sbic_scsidone(acb, stat); 548 } 549 550 void 551 sbic_scsidone(acb, stat) 552 struct sbic_acb *acb; 553 int stat; 554 { 555 struct scsipi_xfer *xs = acb->xs; 556 struct scsipi_link *slp = xs->sc_link; 557 struct sbic_softc *dev = slp->adapter_softc; 558 int dosched = 0; 559 560 #ifdef DIAGNOSTIC 561 if ( acb == NULL || xs == NULL ) { 562 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 563 #ifdef DDB 564 Debugger(); 565 #endif 566 return; 567 } 568 #endif 569 570 /* 571 * is this right? 572 */ 573 xs->status = stat; 574 575 #ifdef DEBUG 576 if ( data_pointer_debug > 1 ) 577 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 578 slp->scsipi_scsi.lun, 579 dev->target, dev->lun, stat); 580 581 if ( xs->sc_link->scsipi_scsi.target == 582 dev->sc_link.scsipi_scsi.adapter_target ) 583 panic("target == hostid"); 584 #endif 585 586 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 587 588 if ( stat == SCSI_CHECK ) { 589 /* 590 * Schedule a REQUEST SENSE 591 */ 592 struct scsipi_sense *ss = (void *)&acb->cmd; 593 594 #ifdef DEBUG 595 if ( report_sense ) 596 printf("sbic_scsidone: autosense %02x targ %d lun %d", 597 acb->cmd.opcode, slp->scsipi_scsi.target, 598 slp->scsipi_scsi.lun); 599 #endif 600 601 bzero(ss, sizeof(*ss)); 602 603 ss->opcode = REQUEST_SENSE; 604 ss->byte2 = slp->scsipi_scsi.lun << 5; 605 ss->length = sizeof(struct scsipi_sense_data); 606 607 acb->clen = sizeof(*ss); 608 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 609 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 610 acb->pa_addr = (char *)kvtop(&xs->sense.scsi_sense); /* XXX check */ 611 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 612 613 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 614 615 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 616 ~(1 << slp->scsipi_scsi.lun); 617 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 618 619 if ( dev->sc_nexus == acb ) { 620 dev->sc_nexus = NULL; 621 dev->sc_xs = NULL; 622 sbic_sched(dev); 623 } 624 return; 625 } 626 } 627 628 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 629 630 xs->error = XS_SENSE; 631 632 #ifdef DEBUG 633 if (report_sense) 634 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 635 xs->sense.scsi_sense.extra_bytes[3]); 636 #endif 637 638 } else { 639 xs->resid = 0; /* XXXX */ 640 } 641 642 xs->xs_status |= XS_STS_DONE; 643 644 /* 645 * Remove the ACB from whatever queue it's on. We have to do a bit of 646 * a hack to figure out which queue it's on. Note that it is *not* 647 * necessary to cdr down the ready queue, but we must cdr down the 648 * nexus queue and see if it's there, so we can mark the unit as no 649 * longer busy. This code is sickening, but it works. 650 */ 651 if ( acb == dev->sc_nexus ) { 652 653 dev->sc_nexus = NULL; 654 dev->sc_xs = NULL; 655 656 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 657 ~(1 << slp->scsipi_scsi.lun); 658 659 if ( dev->ready_list.tqh_first ) 660 dosched = 1; /* start next command */ 661 662 } else 663 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 664 665 TAILQ_REMOVE(&dev->ready_list, acb, chain); 666 667 } else { 668 669 struct sbic_acb *a; 670 671 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 672 if ( a == acb ) { 673 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 674 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 675 ~(1 << slp->scsipi_scsi.lun); 676 break; 677 } 678 } 679 680 if ( a ) 681 ; 682 else if ( acb->chain.tqe_next ) { 683 TAILQ_REMOVE(&dev->ready_list, acb, chain); 684 } else { 685 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 686 #ifdef DDB 687 Debugger(); 688 #endif 689 } 690 } 691 692 /* 693 * Put it on the free list. 694 */ 695 acb->flags = ACB_FREE; 696 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 697 698 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 699 700 scsipi_done(xs); 701 702 if ( dosched ) 703 sbic_sched(dev); 704 } 705 706 int 707 sbicdmaok(dev, xs) 708 struct sbic_softc *dev; 709 struct scsipi_xfer *xs; 710 { 711 if ( sbic_no_dma || xs->datalen & 0x03 || (int)xs->data & 0x03) 712 return(0); 713 714 /* 715 * controller supports dma to any addresses? 716 */ 717 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 718 return(1); 719 720 /* 721 * this address is ok for dma? 722 */ 723 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 724 return(1); 725 726 return(0); 727 } 728 729 int 730 sbicwait(regs, until, timeo, line) 731 sbic_regmap_p regs; 732 u_char until; 733 int timeo; 734 int line; 735 { 736 u_char val; 737 738 if ( timeo == 0 ) 739 timeo = 1000000; /* some large value.. */ 740 741 GET_SBIC_asr(regs, val); 742 743 while ( (val & until) == 0 ) { 744 745 if ( timeo-- == 0 ) { 746 int csr; 747 GET_SBIC_csr(regs, csr); 748 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 749 #if defined(DDB) && defined(DEBUG) 750 Debugger(); 751 #endif 752 return(val); /* Maybe I should abort */ 753 break; 754 } 755 756 DELAY(1); 757 GET_SBIC_asr(regs, val); 758 } 759 760 return(val); 761 } 762 763 int 764 sbicabort(dev, where) 765 struct sbic_softc *dev; 766 char *where; 767 { 768 sbic_regmap_p regs = dev->sc_sbicp; 769 u_char csr, 770 asr; 771 772 GET_SBIC_asr(regs, asr); 773 GET_SBIC_csr(regs, csr); 774 775 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 776 dev->sc_dev.dv_xname, where, csr, asr); 777 778 /* 779 * Clean up chip itself 780 */ 781 if ( dev->sc_flags & SBICF_SELECTED ) { 782 783 while ( asr & SBIC_ASR_DBR ) { 784 /* 785 * sbic is jammed w/data. need to clear it 786 * But we don't know what direction it needs to go 787 */ 788 GET_SBIC_data(regs, asr); 789 printf("%s: abort %s: clearing data buffer 0x%02x\n", 790 dev->sc_dev.dv_xname, where, asr); 791 GET_SBIC_asr(regs, asr); 792 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 793 SET_SBIC_data(regs, asr); 794 GET_SBIC_asr(regs, asr); 795 } 796 797 WAIT_CIP(regs); 798 799 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 800 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 801 WAIT_CIP(regs); 802 803 GET_SBIC_asr(regs, asr); 804 805 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 806 /* 807 * ok, get more drastic.. 808 */ 809 printf("%s: sbicabort - asr %x, trying to reset\n", 810 dev->sc_dev.dv_xname, asr); 811 sbicreset(dev); 812 dev->sc_flags &= ~SBICF_SELECTED; 813 return SBIC_STATE_ERROR; 814 } 815 816 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 817 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 818 819 do { 820 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 821 GET_SBIC_asr(regs, asr); 822 GET_SBIC_csr (regs, csr); 823 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 824 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 825 (csr != SBIC_CSR_CMD_INVALID) ); 826 827 /* 828 * lets just hope it worked.. 829 */ 830 dev->sc_flags &= ~SBICF_SELECTED; 831 } 832 833 return SBIC_STATE_ERROR; 834 } 835 836 837 /* 838 * Initialize driver-private structures 839 */ 840 void 841 sbicinit(dev) 842 struct sbic_softc *dev; 843 { 844 u_int i; 845 846 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 847 848 struct sbic_acb *acb; 849 850 TAILQ_INIT(&dev->ready_list); 851 TAILQ_INIT(&dev->nexus_list); 852 TAILQ_INIT(&dev->free_list); 853 854 dev->sc_nexus = NULL; 855 dev->sc_xs = NULL; 856 857 acb = dev->sc_acb; 858 bzero(acb, sizeof(dev->sc_acb)); 859 860 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 861 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 862 acb++; 863 } 864 865 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 866 867 #ifdef DEBUG 868 /* 869 * make sure timeout is really not needed 870 */ 871 timeout((void *)sbictimeout, dev, 30 * hz); 872 #endif 873 874 } else 875 panic("sbic: reinitializing driver!"); 876 877 dev->sc_flags |= SBICF_ALIVE; 878 dev->sc_flags &= ~SBICF_SELECTED; 879 880 /* 881 * initialize inhibit array 882 * Never enable Sync, since it just doesn't work on mvme147 :( 883 */ 884 for (i = 0; i < 8; ++i) 885 sbic_inhibit_sync[i] = 1; 886 887 sbicreset(dev); 888 } 889 890 void 891 sbicreset(dev) 892 struct sbic_softc *dev; 893 { 894 sbic_regmap_p regs = dev->sc_sbicp; 895 u_int my_id, 896 s; 897 u_char csr; 898 899 s = splbio(); 900 901 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 902 903 if (dev->sc_clkfreq < 110) 904 my_id |= SBIC_ID_FS_8_10; 905 else if (dev->sc_clkfreq < 160) 906 my_id |= SBIC_ID_FS_12_15; 907 else if (dev->sc_clkfreq < 210) 908 my_id |= SBIC_ID_FS_16_20; 909 910 SET_SBIC_myid(regs, my_id); 911 912 /* 913 * Reset the chip 914 */ 915 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 916 DELAY(25); 917 918 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 919 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 920 921 /* 922 * Set up various chip parameters 923 */ 924 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 925 926 /* 927 * don't allow Selection (SBIC_RID_ES) 928 * until we can handle target mode!! 929 */ 930 SET_SBIC_rselid(regs, SBIC_RID_ER); 931 932 /* 933 * Asynchronous for now 934 */ 935 SET_SBIC_syn(regs, 0); 936 937 /* 938 * Anything else was zeroed by reset 939 */ 940 splx(s); 941 942 dev->sc_flags &= ~SBICF_SELECTED; 943 } 944 945 void 946 sbicerror(dev, csr) 947 struct sbic_softc *dev; 948 u_char csr; 949 { 950 struct scsipi_xfer *xs = dev->sc_xs; 951 952 #ifdef DIAGNOSTIC 953 if ( xs == NULL ) 954 panic("sbicerror: dev->sc_xs == NULL"); 955 #endif 956 957 if ( xs->xs_control & XS_CTL_SILENT ) 958 return; 959 960 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 961 } 962 963 /* 964 * select the bus, return when selected or error. 965 * 966 * Returns the current CSR following selection and optionally MSG out phase. 967 * i.e. the returned CSR *should* indicate CMD phase... 968 * If the return value is 0, some error happened. 969 */ 970 u_char 971 sbicselectbus(dev) 972 struct sbic_softc *dev; 973 { 974 sbic_regmap_p regs = dev->sc_sbicp; 975 u_char target = dev->target, 976 lun = dev->lun, 977 asr, 978 csr, 979 id; 980 981 /* 982 * if we're already selected, return (XXXX panic maybe?) 983 */ 984 if ( dev->sc_flags & SBICF_SELECTED ) 985 return(0); 986 987 QPRINTF(("sbicselectbus %d: ", target)); 988 989 /* 990 * issue select 991 */ 992 SET_SBIC_selid(regs, target); 993 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 994 995 GET_SBIC_asr(regs, asr); 996 997 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 998 /* 999 * This means we got ourselves reselected upon 1000 */ 1001 QPRINTF(("WD busy (reselect?)\n")); 1002 return 0; 1003 } 1004 1005 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1006 1007 /* 1008 * wait for select (merged from seperate function may need 1009 * cleanup) 1010 */ 1011 WAIT_CIP(regs); 1012 1013 do { 1014 1015 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1016 1017 if ( asr & SBIC_ASR_LCI ) { 1018 QPRINTF(("late LCI: asr %02x\n", asr)); 1019 return 0; 1020 } 1021 1022 /* 1023 * Clear interrupt 1024 */ 1025 GET_SBIC_csr (regs, csr); 1026 1027 QPRINTF(("%02x ", csr)); 1028 1029 /* 1030 * Reselected from under our feet? 1031 */ 1032 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1033 QPRINTF(("got reselected, asr %02x\n", asr)); 1034 /* 1035 * We need to handle this now so we don't lock up later 1036 */ 1037 sbicnextstate(dev, csr, asr); 1038 1039 return 0; 1040 } 1041 1042 /* 1043 * Whoops! 1044 */ 1045 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1046 panic("sbicselectbus: target issued select!"); 1047 return 0; 1048 } 1049 1050 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1051 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1052 csr != SBIC_CSR_SEL_TIMEO); 1053 1054 /* 1055 * Anyone at home? 1056 */ 1057 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1058 dev->sc_xs->error = XS_SELTIMEOUT; 1059 QPRINTF(("Selection Timeout\n")); 1060 return 0; 1061 } 1062 1063 QPRINTF(("Selection Complete\n")); 1064 1065 /* 1066 * Assume we're now selected 1067 */ 1068 GET_SBIC_selid(regs, id); 1069 dev->target = id; 1070 dev->lun = lun; 1071 dev->sc_flags |= SBICF_SELECTED; 1072 1073 /* 1074 * Enable (or not) reselection 1075 * XXXSCW This is probably not necessary since we don't use use the 1076 * Select-and-Xfer-with-ATN command to initiate a selection... 1077 */ 1078 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1079 SET_SBIC_rselid (regs, 0); 1080 else 1081 SET_SBIC_rselid (regs, SBIC_RID_ER); 1082 1083 /* 1084 * We only really need to do anything when the target goes to MSG out 1085 * If the device ignored ATN, it's probably old and brain-dead, 1086 * but we'll try to support it anyhow. 1087 * If it doesn't support message out, it definately doesn't 1088 * support synchronous transfers, so no point in even asking... 1089 */ 1090 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1091 /* 1092 * Send identify message (SCSI-2 requires an identify msg) 1093 */ 1094 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1095 /* 1096 * Handle drives that don't want to be asked 1097 * whether to go sync at all. 1098 */ 1099 dev->sc_sync[id].offset = 0; 1100 dev->sc_sync[id].period = sbic_min_period; 1101 dev->sc_sync[id].state = SYNC_DONE; 1102 } 1103 1104 /* 1105 * Do we need to negotiate Synchronous Xfers for this target? 1106 */ 1107 if ( dev->sc_sync[id].state != SYNC_START ) { 1108 /* 1109 * Nope, we've already negotiated. 1110 * Now see if we should allow the target to disconnect/reselect... 1111 */ 1112 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1113 !sbic_enable_reselect ) 1114 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1115 else 1116 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1117 1118 } else { 1119 /* 1120 * try to initiate a sync transfer. 1121 * So compose the sync message we're going 1122 * to send to the target 1123 */ 1124 #ifdef DEBUG 1125 if ( sync_debug ) 1126 printf("\nSending sync request to target %d ... ", id); 1127 #endif 1128 /* 1129 * setup scsi message sync message request 1130 */ 1131 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1132 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1133 dev->sc_msg[2] = 3; 1134 dev->sc_msg[3] = MSG_SYNC_REQ; 1135 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1136 dev->sc_msg[5] = sbic_max_offset; 1137 1138 sbicxfout(regs, 6, dev->sc_msg); 1139 1140 dev->sc_sync[id].state = SYNC_SENT; 1141 #ifdef DEBUG 1142 if ( sync_debug ) 1143 printf ("sent\n"); 1144 #endif 1145 } 1146 1147 /* 1148 * There's one interrupt still to come: the change to CMD phase... 1149 */ 1150 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1151 GET_SBIC_csr(regs, csr); 1152 } 1153 1154 /* 1155 * set sync or async 1156 */ 1157 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1158 #ifdef DEBUG 1159 if ( sync_debug ) 1160 printf("select(%d): sync reg = 0x%02x\n", target, 1161 SBIC_SYN(dev->sc_sync[target].offset, 1162 dev->sc_sync[target].period)); 1163 #endif 1164 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1165 dev->sc_sync[target].period)); 1166 } else { 1167 #ifdef DEBUG 1168 if ( sync_debug ) 1169 printf("select(%d): sync reg = 0x%02x\n", target, 1170 SBIC_SYN(0,sbic_min_period)); 1171 #endif 1172 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1173 } 1174 1175 return csr; 1176 } 1177 1178 /* 1179 * Information Transfer *to* a Scsi Target. 1180 * 1181 * Note: Don't expect there to be an interrupt immediately after all 1182 * the data is transferred out. The WD spec sheet says that the Transfer- 1183 * Info command for non-MSG_IN phases only completes when the target 1184 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1185 * 1186 * This can have a nasty effect on commands which take a relatively long 1187 * time to complete, for example a START/STOP unit command may remain in 1188 * CMD phase until the disk has spun up. Only then will the target change 1189 * to STATUS phase. This is really only a problem for immediate commands 1190 * since we don't allow disconnection for them (yet). 1191 */ 1192 int 1193 sbicxfout(regs, len, bp) 1194 sbic_regmap_p regs; 1195 int len; 1196 void *bp; 1197 { 1198 int wait = sbic_data_wait; 1199 u_char asr, 1200 *buf = bp; 1201 1202 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1203 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1204 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1205 1206 /* 1207 * sigh.. WD-PROTO strikes again.. sending the command in one go 1208 * causes the chip to lock up if talking to certain (misbehaving?) 1209 * targets. Anyway, this procedure should work for all targets, but 1210 * it's slightly slower due to the overhead 1211 */ 1212 WAIT_CIP (regs); 1213 1214 SBIC_TC_PUT (regs, 0); 1215 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1216 SBIC_TC_PUT (regs, (unsigned)len); 1217 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1218 1219 /* 1220 * Loop for each byte transferred 1221 */ 1222 do { 1223 1224 GET_SBIC_asr (regs, asr); 1225 1226 if ( asr & SBIC_ASR_DBR ) { 1227 if ( len ) { 1228 SET_SBIC_data (regs, *buf); 1229 buf++; 1230 len--; 1231 } else { 1232 SET_SBIC_data (regs, 0); 1233 } 1234 wait = sbic_data_wait; 1235 } 1236 1237 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1238 1239 #ifdef DEBUG 1240 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1241 #endif 1242 1243 /* 1244 * Normally, an interrupt will be pending when this routing returns. 1245 */ 1246 return(len); 1247 } 1248 1249 /* 1250 * Information Transfer *from* a Scsi Target 1251 * returns # bytes left to read 1252 */ 1253 int 1254 sbicxfin(regs, len, bp) 1255 sbic_regmap_p regs; 1256 int len; 1257 void *bp; 1258 { 1259 int wait = sbic_data_wait; 1260 u_char *buf = bp; 1261 u_char asr; 1262 #ifdef DEBUG 1263 u_char *obp = bp; 1264 #endif 1265 1266 WAIT_CIP (regs); 1267 1268 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1269 SBIC_TC_PUT (regs, (unsigned)len); 1270 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1271 1272 /* 1273 * Loop for each byte transferred 1274 */ 1275 do { 1276 1277 GET_SBIC_asr (regs, asr); 1278 1279 if ( asr & SBIC_ASR_DBR ) { 1280 if ( len ) { 1281 GET_SBIC_data (regs, *buf); 1282 buf++; 1283 len--; 1284 } else { 1285 u_char foo; 1286 GET_SBIC_data (regs, foo); 1287 } 1288 wait = sbic_data_wait; 1289 } 1290 1291 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1292 1293 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1294 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1295 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1296 1297 SBIC_TC_PUT (regs, 0); 1298 1299 /* 1300 * this leaves with one csr to be read 1301 */ 1302 return len; 1303 } 1304 1305 /* 1306 * SCSI 'immediate' command: issue a command to some SCSI device 1307 * and get back an 'immediate' response (i.e., do programmed xfer 1308 * to get the response data). 'cbuf' is a buffer containing a scsi 1309 * command of length clen bytes. 'buf' is a buffer of length 'len' 1310 * bytes for data. The transfer direction is determined by the device 1311 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1312 * command must supply no data. 1313 * 1314 * Note that although this routine looks like it can handle disconnect/ 1315 * reselect, the fact is that it can't. There is still some work to be 1316 * done to clean this lot up. 1317 */ 1318 int 1319 sbicicmd(dev, cbuf, clen, buf, len) 1320 struct sbic_softc *dev; 1321 void *cbuf, 1322 *buf; 1323 int clen, 1324 len; 1325 { 1326 sbic_regmap_p regs = dev->sc_sbicp; 1327 struct sbic_acb *acb = dev->sc_nexus; 1328 u_char csr, 1329 asr; 1330 int still_busy = SBIC_STATE_RUNNING; 1331 #ifdef DEBUG 1332 int counter = 0; 1333 #endif 1334 1335 /* 1336 * Make sure pointers are OK 1337 */ 1338 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1339 dev->sc_tcnt = acb->sc_tcnt = 0; 1340 1341 acb->sc_dmacmd = 0; 1342 acb->sc_pa.dc_count = 0; /* No DMA */ 1343 acb->sc_kv.dc_addr = buf; 1344 acb->sc_kv.dc_count = len; 1345 1346 #ifdef DEBUG 1347 if ( data_pointer_debug > 1 ) 1348 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1349 #endif 1350 1351 /* 1352 * set the sbic into non-DMA mode 1353 */ 1354 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1355 1356 dev->sc_stat[0] = 0xff; 1357 dev->sc_msg[0] = 0xff; 1358 1359 /* 1360 * We're stealing the SCSI bus 1361 */ 1362 dev->sc_flags |= SBICF_ICMD; 1363 1364 do { 1365 GET_SBIC_asr (regs, asr); 1366 1367 /* 1368 * select the SCSI bus (it's an error if bus isn't free) 1369 */ 1370 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1371 still_busy != SBIC_STATE_DISCONNECT ) { 1372 if ( (csr = sbicselectbus(dev)) == 0 ) { 1373 dev->sc_flags &= ~SBICF_ICMD; 1374 return(-1); 1375 } 1376 } else 1377 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1378 GET_SBIC_csr(regs, csr); 1379 else 1380 csr = 0; 1381 1382 if ( csr ) { 1383 1384 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1385 1386 switch ( csr ) { 1387 1388 case SBIC_CSR_S_XFERRED: 1389 case SBIC_CSR_DISC: 1390 case SBIC_CSR_DISC_1: 1391 { 1392 u_char phase; 1393 1394 dev->sc_flags &= ~SBICF_SELECTED; 1395 GET_SBIC_cmd_phase (regs, phase); 1396 1397 if ( phase == 0x60 ) { 1398 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1399 still_busy = SBIC_STATE_DONE; /* done */ 1400 } else { 1401 #ifdef DEBUG 1402 if ( reselect_debug > 1 ) 1403 printf("sbicicmd: handling disconnect\n"); 1404 #endif 1405 still_busy = SBIC_STATE_DISCONNECT; 1406 } 1407 } 1408 break; 1409 1410 case SBIC_CSR_XFERRED | CMD_PHASE: 1411 case SBIC_CSR_MIS | CMD_PHASE: 1412 case SBIC_CSR_MIS_1 | CMD_PHASE: 1413 case SBIC_CSR_MIS_2 | CMD_PHASE: 1414 { 1415 if ( sbicxfout(regs, clen, cbuf) ) 1416 still_busy = sbicabort(dev, "icmd sending cmd"); 1417 } 1418 break; 1419 1420 case SBIC_CSR_XFERRED | STATUS_PHASE: 1421 case SBIC_CSR_MIS | STATUS_PHASE: 1422 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1423 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1424 { 1425 /* 1426 * The sbic does the status/cmd-complete reading ok, 1427 * so do this with its hi-level commands. 1428 */ 1429 #ifdef DEBUG 1430 if ( sbic_debug ) 1431 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1432 #endif 1433 SET_SBIC_cmd_phase(regs, 0x46); 1434 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1435 } 1436 break; 1437 1438 default: 1439 { 1440 still_busy = sbicnextstate(dev, csr, asr); 1441 } 1442 break; 1443 } 1444 1445 /* 1446 * make sure the last command was taken, 1447 * ie. we're not hunting after an ignored command.. 1448 */ 1449 GET_SBIC_asr(regs, asr); 1450 1451 /* 1452 * tapes may take a loooong time.. 1453 */ 1454 while (asr & SBIC_ASR_BSY ) { 1455 1456 if ( asr & SBIC_ASR_DBR ) { 1457 int i; 1458 1459 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1460 #ifdef DDB 1461 Debugger(); 1462 #endif 1463 /* 1464 * SBIC is jammed 1465 * DUNNO which direction 1466 * Try old direction 1467 */ 1468 GET_SBIC_data(regs, i); 1469 GET_SBIC_asr(regs, asr); 1470 1471 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1472 SET_SBIC_data(regs, i); 1473 } 1474 1475 GET_SBIC_asr(regs, asr); 1476 } 1477 } 1478 1479 /* 1480 * wait for last command to complete 1481 */ 1482 if ( asr & SBIC_ASR_LCI ) { 1483 printf("sbicicmd: last command ignored\n"); 1484 } 1485 else 1486 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1487 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1488 1489 /* 1490 * do it again 1491 */ 1492 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1493 1494 /* 1495 * Sometimes we need to do an extra read of the CSR 1496 */ 1497 GET_SBIC_csr(regs, csr); 1498 1499 #ifdef DEBUG 1500 if ( data_pointer_debug > 1 ) 1501 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1502 acb->sc_kv.dc_count, 1503 dev->sc_stat[0]); 1504 #endif 1505 1506 dev->sc_flags &= ~SBICF_ICMD; 1507 1508 return(dev->sc_stat[0]); 1509 } 1510 1511 /* 1512 * Finish SCSI xfer command: After the completion interrupt from 1513 * a read/write operation, sequence through the final phases in 1514 * programmed i/o. This routine is a lot like sbicicmd except we 1515 * skip (and don't allow) the select, cmd out and data in/out phases. 1516 */ 1517 void 1518 sbicxfdone(dev) 1519 struct sbic_softc *dev; 1520 { 1521 sbic_regmap_p regs = dev->sc_sbicp; 1522 u_char phase, 1523 csr; 1524 int s; 1525 1526 QPRINTF(("{")); 1527 s = splbio(); 1528 1529 /* 1530 * have the sbic complete on its own 1531 */ 1532 SBIC_TC_PUT(regs, 0); 1533 SET_SBIC_cmd_phase(regs, 0x46); 1534 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1535 1536 do { 1537 1538 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1539 GET_SBIC_csr (regs, csr); 1540 QPRINTF(("%02x:", csr)); 1541 1542 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1543 (csr != SBIC_CSR_S_XFERRED)); 1544 1545 dev->sc_flags &= ~SBICF_SELECTED; 1546 1547 GET_SBIC_cmd_phase (regs, phase); 1548 QPRINTF(("}%02x", phase)); 1549 1550 if ( phase == 0x60 ) 1551 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1552 else 1553 sbicerror(dev, csr); 1554 1555 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1556 1557 splx(s); 1558 } 1559 1560 /* 1561 * No DMA chains 1562 */ 1563 int 1564 sbicgo(dev, xs) 1565 struct sbic_softc *dev; 1566 struct scsipi_xfer *xs; 1567 { 1568 struct sbic_acb *acb = dev->sc_nexus; 1569 sbic_regmap_p regs = dev->sc_sbicp; 1570 int i, 1571 dmaflags, 1572 count, 1573 usedma; 1574 u_char csr, 1575 asr, 1576 *addr; 1577 1578 dev->target = xs->sc_link->scsipi_scsi.target; 1579 dev->lun = xs->sc_link->scsipi_scsi.lun; 1580 1581 usedma = sbicdmaok(dev, xs); 1582 1583 #ifdef DEBUG 1584 if ( data_pointer_debug > 1 ) 1585 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1586 #endif 1587 1588 /* 1589 * select the SCSI bus (it's an error if bus isn't free) 1590 */ 1591 if ( (csr = sbicselectbus(dev)) == 0 ) 1592 return(0); /* Not done: needs to be rescheduled */ 1593 1594 dev->sc_stat[0] = 0xff; 1595 1596 /* 1597 * Calculate DMA chains now 1598 */ 1599 if ( acb->flags & ACB_DATAIN ) 1600 dmaflags = DMAGO_READ; 1601 else 1602 dmaflags = 0; 1603 1604 addr = acb->sc_kv.dc_addr; 1605 count = acb->sc_kv.dc_count; 1606 1607 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1608 printf("sbic: DMA buffer mapping changed %x->%x\n", 1609 acb->sc_pa.dc_addr, kvtop(addr)); 1610 #ifdef DDB 1611 Debugger(); 1612 #endif 1613 } 1614 1615 #ifdef DEBUG 1616 ++sbicdma_ops; /* count total DMA operations */ 1617 #endif 1618 1619 /* 1620 * Allocate the DMA chain 1621 * Mark end of segment... 1622 */ 1623 acb->sc_tcnt = dev->sc_tcnt = 0; 1624 acb->sc_pa.dc_count = 0; 1625 1626 sbic_load_ptrs(dev); 1627 1628 /* 1629 * Enable interrupts but don't do any DMA 1630 * enintr() also enables interrupts for the sbic 1631 */ 1632 dev->sc_enintr(dev); 1633 1634 if ( usedma ) { 1635 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1636 acb->sc_pa.dc_count, dmaflags); 1637 #ifdef DEBUG 1638 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1639 #endif 1640 } else 1641 dev->sc_dmacmd = 0; /* Don't use DMA */ 1642 1643 acb->sc_dmacmd = dev->sc_dmacmd; 1644 1645 #ifdef DEBUG 1646 if ( data_pointer_debug > 1 ) { 1647 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1648 dev->sc_cur->dc_addr, 1649 dev->sc_tcnt, 1650 dev->sc_dmacmd); 1651 } 1652 #endif 1653 1654 /* 1655 * Lets cycle a while then let the interrupt handler take over. 1656 */ 1657 GET_SBIC_asr(regs, asr); 1658 1659 do { 1660 1661 QPRINTF(("go ")); 1662 1663 /* 1664 * Handle the new phase 1665 */ 1666 i = sbicnextstate(dev, csr, asr); 1667 #if 0 1668 WAIT_CIP(regs); 1669 #endif 1670 if ( i == SBIC_STATE_RUNNING ) { 1671 GET_SBIC_asr(regs, asr); 1672 1673 if ( asr & SBIC_ASR_LCI ) 1674 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1675 1676 if ( asr & SBIC_ASR_INT ) 1677 GET_SBIC_csr(regs, csr); 1678 } 1679 1680 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1681 1682 if ( i == SBIC_STATE_DONE ) { 1683 if ( dev->sc_stat[0] == 0xff ) 1684 #if 0 1685 printf("sbicgo: done & stat = 0xff\n"); 1686 #else 1687 ; 1688 #endif 1689 else 1690 return 1; /* Did we really finish that fast? */ 1691 } 1692 1693 return 0; 1694 } 1695 1696 1697 int 1698 sbicintr(dev) 1699 struct sbic_softc *dev; 1700 { 1701 sbic_regmap_p regs = dev->sc_sbicp; 1702 u_char asr, 1703 csr; 1704 int i; 1705 1706 /* 1707 * pending interrupt? 1708 */ 1709 GET_SBIC_asr (regs, asr); 1710 if ( (asr & SBIC_ASR_INT) == 0 ) 1711 return(0); 1712 1713 GET_SBIC_csr(regs, csr); 1714 1715 do { 1716 1717 QPRINTF(("intr[0x%x]", csr)); 1718 1719 i = sbicnextstate(dev, csr, asr); 1720 #if 0 1721 WAIT_CIP(regs); 1722 #endif 1723 if ( i == SBIC_STATE_RUNNING ) { 1724 GET_SBIC_asr(regs, asr); 1725 1726 if ( asr & SBIC_ASR_LCI ) 1727 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1728 1729 if ( asr & SBIC_ASR_INT ) 1730 GET_SBIC_csr(regs, csr); 1731 } 1732 1733 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1734 1735 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1736 1737 return(1); 1738 } 1739 1740 /* 1741 * Run commands and wait for disconnect. 1742 * This is only ever called when a command is in progress, when we 1743 * want to busy wait for it to finish. 1744 */ 1745 int 1746 sbicpoll(dev) 1747 struct sbic_softc *dev; 1748 { 1749 sbic_regmap_p regs = dev->sc_sbicp; 1750 u_char asr, 1751 csr; 1752 int i; 1753 1754 /* 1755 * Wait for the next interrupt 1756 */ 1757 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1758 1759 do { 1760 GET_SBIC_asr (regs, asr); 1761 1762 if ( asr & SBIC_ASR_INT ) 1763 GET_SBIC_csr(regs, csr); 1764 1765 QPRINTF(("poll[0x%x]", csr)); 1766 1767 /* 1768 * Handle it 1769 */ 1770 i = sbicnextstate(dev, csr, asr); 1771 1772 WAIT_CIP(regs); 1773 GET_SBIC_asr(regs, asr); 1774 1775 /* 1776 * tapes may take a loooong time.. 1777 */ 1778 while ( asr & SBIC_ASR_BSY ) { 1779 u_char z = 0; 1780 1781 if ( asr & SBIC_ASR_DBR ) { 1782 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1783 #ifdef DDB 1784 Debugger(); 1785 #endif 1786 /* 1787 * SBIC is jammed 1788 * DUNNO which direction 1789 * Try old direction 1790 */ 1791 GET_SBIC_data(regs, z); 1792 GET_SBIC_asr(regs, asr); 1793 1794 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1795 SET_SBIC_data(regs, z); 1796 } 1797 1798 GET_SBIC_asr(regs, asr); 1799 } 1800 1801 if ( asr & SBIC_ASR_LCI ) 1802 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1803 else 1804 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1805 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1806 1807 } while ( i == SBIC_STATE_RUNNING ); 1808 1809 return(1); 1810 } 1811 1812 /* 1813 * Handle a single msgin 1814 */ 1815 int 1816 sbicmsgin(dev) 1817 struct sbic_softc *dev; 1818 { 1819 sbic_regmap_p regs = dev->sc_sbicp; 1820 int recvlen = 1; 1821 u_char asr, 1822 csr, 1823 *tmpaddr, 1824 *msgaddr; 1825 1826 tmpaddr = msgaddr = dev->sc_msg; 1827 1828 tmpaddr[0] = 0xff; 1829 tmpaddr[1] = 0xff; 1830 1831 GET_SBIC_asr(regs, asr); 1832 1833 #ifdef DEBUG 1834 if ( reselect_debug > 1 ) 1835 printf("sbicmsgin asr=%02x\n", asr); 1836 #endif 1837 1838 GET_SBIC_selid (regs, csr); 1839 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1840 1841 SBIC_TC_PUT(regs, 0); 1842 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1843 1844 do { 1845 while( recvlen-- ) { 1846 1847 /* 1848 * Fetch the next byte of the message 1849 */ 1850 RECV_BYTE(regs, *tmpaddr); 1851 1852 /* 1853 * get the command completion interrupt, or we 1854 * can't send a new command (LCI) 1855 */ 1856 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1857 GET_SBIC_csr(regs, csr); 1858 1859 #ifdef DEBUG 1860 if ( reselect_debug > 1 ) 1861 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1862 #endif 1863 1864 tmpaddr++; 1865 1866 if ( recvlen ) { 1867 /* 1868 * Clear ACK, and wait for the interrupt for the next byte 1869 */ 1870 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1871 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1872 GET_SBIC_csr(regs, csr); 1873 } 1874 } 1875 1876 if ( msgaddr[0] == 0xff ) { 1877 printf("sbicmsgin: sbic swallowed our message\n"); 1878 break; 1879 } 1880 1881 #ifdef DEBUG 1882 if ( sync_debug ) { 1883 GET_SBIC_asr(regs, asr); 1884 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1885 } 1886 #endif 1887 /* 1888 * test whether this is a reply to our sync 1889 * request 1890 */ 1891 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1892 1893 /* 1894 * Got IFFY msg -- ack it 1895 */ 1896 QPRINTF(("IFFY")); 1897 1898 } else 1899 if ( msgaddr[0] == MSG_REJECT && 1900 dev->sc_sync[dev->target].state == SYNC_SENT) { 1901 1902 /* 1903 * Target probably rejected our Sync negotiation. 1904 */ 1905 QPRINTF(("REJECT of SYN")); 1906 1907 #ifdef DEBUG 1908 if ( sync_debug ) 1909 printf("target %d rejected sync, going async\n", dev->target); 1910 #endif 1911 1912 dev->sc_sync[dev->target].period = sbic_min_period; 1913 dev->sc_sync[dev->target].offset = 0; 1914 dev->sc_sync[dev->target].state = SYNC_DONE; 1915 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1916 dev->sc_sync[dev->target].period)); 1917 1918 } else 1919 if ( msgaddr[0] == MSG_REJECT ) { 1920 1921 /* 1922 * we'll never REJECt a REJECT message.. 1923 */ 1924 QPRINTF(("REJECT")); 1925 1926 } else 1927 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1928 1929 /* 1930 * don't reject this either. 1931 */ 1932 QPRINTF(("MSG_SAVE_DATA_PTR")); 1933 1934 } else 1935 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1936 1937 /* 1938 * don't reject this either. 1939 */ 1940 QPRINTF(("MSG_RESTORE_PTR")); 1941 1942 } else 1943 if ( msgaddr[0] == MSG_DISCONNECT ) { 1944 1945 /* 1946 * Target is disconnecting... 1947 */ 1948 QPRINTF(("DISCONNECT")); 1949 1950 #ifdef DEBUG 1951 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1952 printf("sbicmsgin: got disconnect msg %s\n", 1953 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1954 #endif 1955 1956 if ( dev->sc_flags & SBICF_ICMD ) { 1957 /* 1958 * We're in immediate mode. Prevent disconnects. 1959 * prepare to reject the message, NACK 1960 */ 1961 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1962 WAIT_CIP(regs); 1963 } 1964 1965 } else 1966 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1967 1968 /* 1969 * !! KLUDGE ALERT !! quite a few drives don't seem to 1970 * really like the current way of sending the 1971 * sync-handshake together with the ident-message, and 1972 * they react by sending command-complete and 1973 * disconnecting right after returning the valid sync 1974 * handshake. So, all I can do is reselect the drive, 1975 * and hope it won't disconnect again. I don't think 1976 * this is valid behavior, but I can't help fixing a 1977 * problem that apparently exists. 1978 * 1979 * Note: we should not get here on `normal' command 1980 * completion, as that condition is handled by the 1981 * high-level sel&xfer resume command used to walk 1982 * thru status/cc-phase. 1983 */ 1984 QPRINTF(("CMD_COMPLETE")); 1985 1986 #ifdef DEBUG 1987 if ( sync_debug ) 1988 printf ("GOT MSG %d! target %d acting weird.." 1989 " waiting for disconnect...\n", msgaddr[0], dev->target); 1990 #endif 1991 1992 /* 1993 * Check to see if sbic is handling this 1994 */ 1995 GET_SBIC_asr(regs, asr); 1996 1997 /* 1998 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 1999 */ 2000 if ( asr & SBIC_ASR_BSY ) 2001 return SBIC_STATE_RUNNING; 2002 2003 /* 2004 * Let's try this: Assume it works and set status to 00 2005 */ 2006 dev->sc_stat[0] = 0; 2007 2008 } else 2009 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2010 2011 /* 2012 * Target is sending us an extended message. We'll assume it's 2013 * the response to our Sync. negotiation. 2014 */ 2015 QPRINTF(("ExtMSG\n")); 2016 2017 /* 2018 * Read in whole extended message. First, negate ACK to accept 2019 * the MSG_EXT_MESSAGE byte... 2020 */ 2021 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2022 2023 /* 2024 * Wait for the interrupt for the next byte (length) 2025 */ 2026 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2027 GET_SBIC_csr(regs, csr); 2028 2029 #ifdef DEBUG 2030 QPRINTF(("CLR ACK csr %02x\n", csr)); 2031 #endif 2032 2033 /* 2034 * Read the length byte 2035 */ 2036 RECV_BYTE(regs, *tmpaddr); 2037 2038 /* 2039 * Wait for command completion IRQ 2040 */ 2041 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2042 GET_SBIC_csr(regs, csr); 2043 2044 /* 2045 * Reload the loop counter 2046 */ 2047 recvlen = *tmpaddr++; 2048 2049 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2050 2051 } else 2052 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2053 msgaddr[2] == MSG_SYNC_REQ ) { 2054 2055 /* 2056 * We've received the complete Extended Message Sync. Request... 2057 */ 2058 QPRINTF(("SYN")); 2059 2060 /* 2061 * Compute the required Transfer Period for the WD chip... 2062 */ 2063 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2064 dev->sc_sync[dev->target].offset = msgaddr[4]; 2065 dev->sc_sync[dev->target].state = SYNC_DONE; 2066 2067 /* 2068 * Put the WD chip in synchronous mode 2069 */ 2070 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2071 dev->sc_sync[dev->target].period)); 2072 #ifdef DEBUG 2073 if ( sync_debug ) 2074 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2075 SBIC_SYN(dev->sc_sync[dev->target].offset, 2076 dev->sc_sync[dev->target].period)); 2077 #endif 2078 2079 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2080 dev->sc_dev.dv_xname, dev->target, 2081 msgaddr[3] * 4, msgaddr[4]); 2082 2083 } else { 2084 2085 /* 2086 * We don't support whatever this message is... 2087 */ 2088 #ifdef DEBUG 2089 if ( sbic_debug || sync_debug ) 2090 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2091 #endif 2092 2093 /* 2094 * prepare to reject the message, NACK 2095 */ 2096 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2097 WAIT_CIP(regs); 2098 } 2099 2100 /* 2101 * Negate ACK to complete the transfer 2102 */ 2103 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2104 2105 /* 2106 * Wait for the interrupt for the next byte, or phase change. 2107 * Only read the CSR if we have more data to transfer. 2108 * XXXSCW: We should really verify that we're still in MSG IN phase 2109 * before blindly going back around this loop, but that would mean 2110 * we read the CSR... <sigh> 2111 */ 2112 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2113 if ( recvlen > 0 ) 2114 GET_SBIC_csr(regs, csr); 2115 2116 } while ( recvlen > 0 ); 2117 2118 /* 2119 * Should still have one CSR to read 2120 */ 2121 return SBIC_STATE_RUNNING; 2122 } 2123 2124 2125 /* 2126 * sbicnextstate() 2127 * return: 2128 * SBIC_STATE_DONE == done 2129 * SBIC_STATE_RUNNING == working 2130 * SBIC_STATE_DISCONNECT == disconnected 2131 * SBIC_STATE_ERROR == error 2132 */ 2133 int 2134 sbicnextstate(dev, csr, asr) 2135 struct sbic_softc *dev; 2136 u_char csr, 2137 asr; 2138 { 2139 sbic_regmap_p regs = dev->sc_sbicp; 2140 struct sbic_acb *acb = dev->sc_nexus; 2141 2142 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2143 2144 switch (csr) { 2145 2146 case SBIC_CSR_XFERRED | CMD_PHASE: 2147 case SBIC_CSR_MIS | CMD_PHASE: 2148 case SBIC_CSR_MIS_1 | CMD_PHASE: 2149 case SBIC_CSR_MIS_2 | CMD_PHASE: 2150 { 2151 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2152 goto abort; 2153 } 2154 break; 2155 2156 case SBIC_CSR_XFERRED | STATUS_PHASE: 2157 case SBIC_CSR_MIS | STATUS_PHASE: 2158 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2159 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2160 { 2161 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2162 2163 /* 2164 * this should be the normal i/o completion case. 2165 * get the status & cmd complete msg then let the 2166 * device driver look at what happened. 2167 */ 2168 sbicxfdone(dev); 2169 2170 #ifdef DEBUG 2171 dev->sc_dmatimo = 0; 2172 if ( data_pointer_debug > 1 ) 2173 printf("next dmastop: %d(%x:%x)\n", dev->target, 2174 dev->sc_cur->dc_addr, 2175 dev->sc_tcnt); 2176 #endif 2177 /* 2178 * Stop the DMA chip 2179 */ 2180 dev->sc_dmastop(dev); 2181 2182 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2183 2184 /* 2185 * Indicate to the upper layers that the command is done 2186 */ 2187 sbic_scsidone(acb, dev->sc_stat[0]); 2188 2189 return SBIC_STATE_DONE; 2190 } 2191 2192 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2193 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2194 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2195 case SBIC_CSR_MIS | DATA_IN_PHASE: 2196 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2197 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2198 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2199 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2200 { 2201 /* 2202 * Verify that we expected to transfer data... 2203 */ 2204 if ( acb->sc_kv.dc_count <= 0 ) { 2205 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2206 acb->sc_kv.dc_count, asr, csr); 2207 goto abort; 2208 } 2209 2210 /* 2211 * Should we transfer using PIO or DMA ? 2212 */ 2213 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2214 acb->sc_dmacmd == 0 ) { 2215 2216 /* 2217 * Do PIO transfer 2218 */ 2219 int i; 2220 2221 #ifdef DEBUG 2222 if ( data_pointer_debug > 1 ) 2223 printf("next PIO: %d(%x:%x)\n", dev->target, 2224 acb->sc_kv.dc_addr, 2225 acb->sc_kv.dc_count); 2226 #endif 2227 2228 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2229 /* 2230 * data in 2231 */ 2232 i = sbicxfin(regs, acb->sc_kv.dc_count, 2233 acb->sc_kv.dc_addr); 2234 else 2235 /* 2236 * data out 2237 */ 2238 i = sbicxfout(regs, acb->sc_kv.dc_count, 2239 acb->sc_kv.dc_addr); 2240 2241 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2242 acb->sc_kv.dc_count = i; 2243 2244 /* 2245 * Update current count... 2246 */ 2247 acb->sc_tcnt = dev->sc_tcnt = i; 2248 2249 dev->sc_flags &= ~SBICF_INDMA; 2250 2251 } else { 2252 2253 /* 2254 * Do DMA transfer 2255 * set next dma addr and dec count 2256 */ 2257 sbic_save_ptrs(dev); 2258 sbic_load_ptrs(dev); 2259 2260 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2261 SBIC_MACHINE_DMA_MODE); 2262 2263 #ifdef DEBUG 2264 dev->sc_dmatimo = 1; 2265 if ( data_pointer_debug > 1 ) 2266 printf("next DMA: %d(%x:%x)\n", dev->target, 2267 dev->sc_cur->dc_addr, 2268 dev->sc_tcnt); 2269 #endif 2270 /* 2271 * Start the DMA chip going 2272 */ 2273 dev->sc_tcnt = dev->sc_dmanext(dev); 2274 2275 /* 2276 * Tell the WD chip how much to transfer this time around 2277 */ 2278 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2279 2280 /* 2281 * Start the transfer 2282 */ 2283 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2284 2285 /* 2286 * Indicate that we're in DMA mode 2287 */ 2288 dev->sc_flags |= SBICF_INDMA; 2289 } 2290 } 2291 break; 2292 2293 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2294 case SBIC_CSR_MIS | MESG_IN_PHASE: 2295 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2296 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2297 { 2298 sbic_save_ptrs(dev); 2299 2300 /* 2301 * Handle a single message in... 2302 */ 2303 return sbicmsgin(dev); 2304 } 2305 2306 case SBIC_CSR_MSGIN_W_ACK: 2307 { 2308 /* 2309 * We should never see this since it's handled in 'sbicmsgin()' 2310 * but just for the sake of paranoia... 2311 */ 2312 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2313 printf("Acking unknown msgin CSR:%02x",csr); 2314 } 2315 break; 2316 2317 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2318 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2319 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2320 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2321 { 2322 /* 2323 * We only ever handle a message out phase here for sending a 2324 * REJECT message. 2325 */ 2326 sbic_save_ptrs(dev); 2327 2328 #ifdef DEBUG 2329 if (sync_debug) 2330 printf ("sending REJECT msg to last msg.\n"); 2331 #endif 2332 2333 SEND_BYTE(regs, MSG_REJECT); 2334 WAIT_CIP(regs); 2335 } 2336 break; 2337 2338 case SBIC_CSR_DISC: 2339 case SBIC_CSR_DISC_1: 2340 { 2341 /* 2342 * Try to schedule another target 2343 */ 2344 sbic_save_ptrs(dev); 2345 2346 dev->sc_flags &= ~SBICF_SELECTED; 2347 2348 #ifdef DEBUG 2349 if ( reselect_debug > 1 ) 2350 printf("sbicnext target %d disconnected\n", dev->target); 2351 #endif 2352 2353 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2354 2355 ++dev->sc_tinfo[dev->target].dconns; 2356 2357 dev->sc_nexus = NULL; 2358 dev->sc_xs = NULL; 2359 2360 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2361 !sbic_parallel_operations ) 2362 return SBIC_STATE_DISCONNECT; 2363 2364 QPRINTF(("sbicnext: calling sbic_sched\n")); 2365 2366 sbic_sched(dev); 2367 2368 QPRINTF(("sbicnext: sbic_sched returned\n")); 2369 2370 return SBIC_STATE_DISCONNECT; 2371 } 2372 2373 case SBIC_CSR_RSLT_NI: 2374 case SBIC_CSR_RSLT_IFY: 2375 { 2376 /* 2377 * A reselection. 2378 * Note that since we don't enable Advanced Features (assuming 2379 * the WD chip is at least the 'A' revision), we're only ever 2380 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2381 * hell of it, we'll handle it anyway, for all the extra code 2382 * it needs... 2383 */ 2384 u_char newtarget, 2385 newlun; 2386 2387 GET_SBIC_rselid(regs, newtarget); 2388 2389 /* 2390 * check SBIC_RID_SIV? 2391 */ 2392 newtarget &= SBIC_RID_MASK; 2393 2394 if ( csr == SBIC_CSR_RSLT_IFY ) { 2395 2396 /* 2397 * Read Identify msg to avoid lockup 2398 */ 2399 GET_SBIC_data(regs, newlun); 2400 WAIT_CIP(regs); 2401 newlun &= SBIC_TLUN_MASK; 2402 2403 } else { 2404 2405 /* 2406 * Need to read Identify message the hard way, assuming 2407 * the target even sends us one... 2408 */ 2409 for (newlun = 255; newlun; --newlun) { 2410 GET_SBIC_asr(regs, asr); 2411 if (asr & SBIC_ASR_INT) 2412 break; 2413 delay(10); 2414 } 2415 2416 /* 2417 * If we didn't get an interrupt, somethink's up 2418 */ 2419 if ( (asr & SBIC_ASR_INT) == 0 ) { 2420 printf("%s: Reselect without identify? asr %x\n", 2421 dev->sc_dev.dv_xname, asr); 2422 newlun = 0; /* XXXX */ 2423 } else { 2424 /* 2425 * We got an interrupt, verify that it's a change to 2426 * message in phase, and if so read the message. 2427 */ 2428 GET_SBIC_csr(regs,csr); 2429 2430 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2431 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2432 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2433 /* 2434 * Yup, gone to message in. Fetch the target LUN 2435 */ 2436 sbicmsgin(dev); 2437 newlun = dev->sc_msg[0] & 0x07; 2438 2439 } else { 2440 /* 2441 * Whoops! Target didn't go to message in phase!! 2442 */ 2443 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2444 newlun = 0; /* XXXSCW */ 2445 } 2446 } 2447 } 2448 2449 /* 2450 * Ok, we have the identity of the reselecting target. 2451 */ 2452 #ifdef DEBUG 2453 if ( reselect_debug > 1 || 2454 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2455 printf("sbicnext: reselect %s from targ %d lun %d\n", 2456 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2457 } 2458 #endif 2459 2460 if ( dev->sc_nexus ) { 2461 /* 2462 * Whoops! We've been reselected with an command in progress! 2463 * The best we can do is to put the current command back on the 2464 * ready list and hope for the best. 2465 */ 2466 #ifdef DEBUG 2467 if ( reselect_debug > 1 ) { 2468 printf("%s: reselect %s with active command\n", 2469 dev->sc_dev.dv_xname, 2470 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2471 } 2472 #endif 2473 2474 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2475 2476 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2477 2478 dev->sc_nexus = NULL; 2479 dev->sc_xs = NULL; 2480 } 2481 2482 /* 2483 * Reload sync values for this target 2484 */ 2485 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2486 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2487 dev->sc_sync[newtarget].period)); 2488 else 2489 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2490 2491 /* 2492 * Loop through the nexus list until we find the saved entry 2493 * for the reselecting target... 2494 */ 2495 for (acb = dev->nexus_list.tqh_first; acb; 2496 acb = acb->chain.tqe_next) { 2497 2498 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2499 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2500 /* 2501 * We've found the saved entry. Dequeue it, and 2502 * make it current again. 2503 */ 2504 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2505 2506 dev->sc_nexus = acb; 2507 dev->sc_xs = acb->xs; 2508 dev->sc_flags |= SBICF_SELECTED; 2509 dev->target = newtarget; 2510 dev->lun = newlun; 2511 break; 2512 } 2513 } 2514 2515 if ( acb == NULL ) { 2516 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2517 dev->sc_dev.dv_xname, 2518 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2519 &dev->nexus_list.tqh_first); 2520 panic("bad reselect in sbic"); 2521 } 2522 2523 if ( csr == SBIC_CSR_RSLT_IFY ) 2524 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2525 } 2526 break; 2527 2528 default: 2529 abort: 2530 { 2531 /* 2532 * Something unexpected happened -- deal with it. 2533 */ 2534 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2535 2536 #ifdef DDB 2537 Debugger(); 2538 #endif 2539 2540 #ifdef DEBUG 2541 dev->sc_dmatimo = 0; 2542 if ( data_pointer_debug > 1 ) 2543 printf("next dmastop: %d(%x:%x)\n", dev->target, 2544 dev->sc_cur->dc_addr, 2545 dev->sc_tcnt); 2546 #endif 2547 2548 dev->sc_dmastop(dev); 2549 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2550 if ( dev->sc_xs ) sbicerror(dev, csr); 2551 sbicabort(dev, "next"); 2552 2553 if ( dev->sc_flags & SBICF_INDMA ) { 2554 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2555 2556 #ifdef DEBUG 2557 dev->sc_dmatimo = 0; 2558 if ( data_pointer_debug > 1 ) 2559 printf("next dmastop: %d(%x:%x)\n", dev->target, 2560 dev->sc_cur->dc_addr, 2561 dev->sc_tcnt); 2562 #endif 2563 sbic_scsidone(acb, -1); 2564 } 2565 2566 return SBIC_STATE_ERROR; 2567 } 2568 } 2569 2570 return(SBIC_STATE_RUNNING); 2571 } 2572 2573 2574 /* 2575 * Check if DMA can not be used with specified buffer 2576 */ 2577 int 2578 sbiccheckdmap(bp, len, mask) 2579 void *bp; 2580 u_long len, 2581 mask; 2582 { 2583 u_char *buffer; 2584 u_long phy_buf; 2585 u_long phy_len; 2586 2587 buffer = bp; 2588 2589 if ( len == 0 ) 2590 return(1); 2591 2592 while ( len ) { 2593 2594 phy_buf = kvtop(buffer); 2595 phy_len = NBPG - ((int) buffer & PGOFSET); 2596 2597 if ( len < phy_len ) 2598 phy_len = len; 2599 2600 if ( phy_buf & mask ) 2601 return(1); 2602 2603 buffer += phy_len; 2604 len -= phy_len; 2605 } 2606 2607 return(0); 2608 } 2609 2610 int 2611 sbictoscsiperiod(dev, a) 2612 struct sbic_softc *dev; 2613 int a; 2614 { 2615 unsigned int fs; 2616 2617 /* 2618 * cycle = DIV / (2 * CLK) 2619 * DIV = FS + 2 2620 * best we can do is 200ns at 20Mhz, 2 cycles 2621 */ 2622 2623 GET_SBIC_myid(dev->sc_sbicp, fs); 2624 2625 fs = (fs >> 6) + 2; /* DIV */ 2626 2627 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2628 2629 if ( a < 2 ) 2630 a = 8; /* map to Cycles */ 2631 2632 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2633 } 2634 2635 int 2636 sbicfromscsiperiod(dev, p) 2637 struct sbic_softc *dev; 2638 int p; 2639 { 2640 unsigned fs, 2641 ret; 2642 2643 /* 2644 * Just the inverse of the above 2645 */ 2646 GET_SBIC_myid(dev->sc_sbicp, fs); 2647 2648 fs = (fs >> 6) + 2; /* DIV */ 2649 2650 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2651 2652 ret = p << 2; /* in ns units */ 2653 ret = ret / fs; /* in Cycles */ 2654 2655 if ( ret < sbic_min_period ) 2656 return(sbic_min_period); 2657 2658 /* 2659 * verify rounding 2660 */ 2661 if ( sbictoscsiperiod(dev, ret) < p ) 2662 ret++; 2663 2664 return( (ret >= 8) ? 0 : ret ); 2665 } 2666 2667 #ifdef DEBUG 2668 void 2669 sbictimeout(dev) 2670 struct sbic_softc *dev; 2671 { 2672 int s, 2673 asr; 2674 2675 s = splbio(); 2676 2677 if ( dev->sc_dmatimo ) { 2678 2679 if ( dev->sc_dmatimo > 1 ) { 2680 2681 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2682 dev->sc_dmatimo - 1); 2683 2684 GET_SBIC_asr(dev->sc_sbicp, asr); 2685 2686 if ( asr & SBIC_ASR_INT ) { 2687 /* 2688 * We need to service a missed IRQ 2689 */ 2690 sbicintr(dev); 2691 } else { 2692 (void) sbicabort(dev, "timeout"); 2693 splx(s); 2694 return; 2695 } 2696 } 2697 2698 dev->sc_dmatimo++; 2699 } 2700 2701 splx(s); 2702 2703 timeout((void *)sbictimeout, dev, 30 * hz); 2704 } 2705 #endif 2706
Indexes created Sat Sep 27 22:09:54 GMT 2025