sbic.c revision 1.11
1 /* $NetBSD: sbic.c,v 1.11 1999/11/13 15:33:57 scw Exp $ */ 2 3 /* 4 * Changes Copyright (c) 1996 Steve Woodford 5 * Original Copyright (c) 1994 Christian E. Hopps 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * Van Jacobson of Lawrence Berkeley Laboratory. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 41 */ 42 43 /* 44 * Steve Woodford (SCW), Apr, 1996 45 * MVME147S WD33C93 Scsi Bus Interface Controller driver, 46 * 47 * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver. 48 * 49 * The original driver used features which required at least a WD33C93A 50 * chip. The '147 has the original WD33C93 chip (no 'A' suffix). 51 * 52 * This version of the driver is pretty well generic, so should work with 53 * any flavour of WD33C93 chip. 54 */ 55 #include "opt_ddb.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/kernel.h> /* For hz */ 61 #include <sys/disklabel.h> 62 #include <sys/dkstat.h> 63 #include <sys/buf.h> 64 #include <dev/scsipi/scsi_all.h> 65 #include <dev/scsipi/scsipi_all.h> 66 #include <dev/scsipi/scsiconf.h> 67 #include <vm/vm.h> 68 #include <vm/vm_kern.h> 69 #include <vm/vm_page.h> 70 #include <vm/pmap.h> 71 #include <machine/pmap.h> 72 #include <mvme68k/mvme68k/isr.h> 73 #include <mvme68k/dev/dmavar.h> 74 #include <mvme68k/dev/sbicreg.h> 75 #include <mvme68k/dev/sbicvar.h> 76 77 78 /* 79 * Since I can't find this in any other header files 80 */ 81 #define SCSI_PHASE(reg) (reg&0x07) 82 83 /* 84 * SCSI delays 85 * In u-seconds, primarily for state changes on the SPC. 86 */ 87 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 88 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 89 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 90 91 /* 92 * Convenience macro for waiting for a particular sbic event 93 */ 94 #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) 95 96 extern u_int kvtop(); 97 98 int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); 99 int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); 100 int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); 101 int sbicwait __P((sbic_regmap_p, u_char, int , int)); 102 int sbiccheckdmap __P((void *, u_long, u_long)); 103 u_char sbicselectbus __P((struct sbic_softc *)); 104 int sbicxfout __P((sbic_regmap_p, int, void *)); 105 int sbicxfin __P((sbic_regmap_p, int, void *)); 106 int sbicfromscsiperiod __P((struct sbic_softc *, int)); 107 int sbictoscsiperiod __P((struct sbic_softc *, int)); 108 int sbicintr __P((struct sbic_softc *)); 109 int sbicpoll __P((struct sbic_softc *)); 110 int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); 111 int sbicmsgin __P((struct sbic_softc *)); 112 int sbicabort __P((struct sbic_softc *, char *)); 113 void sbicxfdone __P((struct sbic_softc *)); 114 void sbicerror __P((struct sbic_softc *,u_char)); 115 void sbicreset __P((struct sbic_softc *)); 116 void sbic_scsidone __P((struct sbic_acb *, int)); 117 void sbic_sched __P((struct sbic_softc *)); 118 void sbic_save_ptrs __P((struct sbic_softc *)); 119 void sbic_load_ptrs __P((struct sbic_softc *)); 120 121 /* 122 * Synch xfer parameters, and timing conversions 123 */ 124 int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */ 125 int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */ 126 int sbic_cmd_wait = SBIC_CMD_WAIT; 127 int sbic_data_wait = SBIC_DATA_WAIT; 128 int sbic_init_wait = SBIC_INIT_WAIT; 129 130 /* 131 * was broken before.. now if you want this you get it for all drives 132 * on sbic controllers. 133 */ 134 u_char sbic_inhibit_sync[8]; 135 int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */ 136 int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */ 137 int sbic_parallel_operations = 1; /* Allow command queues */ 138 139 /* 140 * Some useful stuff for debugging purposes 141 */ 142 #ifdef DEBUG 143 int sbicdma_ops = 0; /* total DMA operations */ 144 int sbicdma_hits = 0; /* number of DMA chains that were contiguous */ 145 int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */ 146 int sbicdma_saves = 0; 147 148 #define QPRINTF(a) if (sbic_debug > 1) printf a 149 150 int sbic_debug = 0; /* Debug all chip related things */ 151 int sync_debug = 0; /* Debug all Synchronous Scsi related things */ 152 int reselect_debug = 0; /* Debug all reselection related things */ 153 int report_sense = 0; /* Always print Sense information */ 154 int data_pointer_debug = 0; /* Debug Data Pointer related things */ 155 156 void sbictimeout __P((struct sbic_softc *dev)); 157 158 #else 159 #define QPRINTF(a) /* */ 160 #endif 161 162 163 /* 164 * default minphys routine for sbic based controllers 165 */ 166 void 167 sbic_minphys(bp) 168 struct buf *bp; 169 { 170 /* 171 * No max transfer at this level. 172 */ 173 minphys(bp); 174 } 175 176 177 /* 178 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 179 */ 180 void 181 sbic_save_ptrs(dev) 182 struct sbic_softc *dev; 183 { 184 sbic_regmap_p regs; 185 struct sbic_acb* acb; 186 int count, 187 asr, 188 s; 189 190 /* 191 * Only need to save pointers if DMA was active... 192 */ 193 if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) 194 return; 195 196 regs = dev->sc_sbicp; 197 198 s = splbio(); 199 200 /* 201 * Wait until WD chip is idle 202 */ 203 do { 204 GET_SBIC_asr(regs, asr); 205 if( asr & SBIC_ASR_DBR ) { 206 printf("sbic_save_ptrs: asr %02x canceled!\n", asr); 207 splx(s); 208 return; 209 } 210 } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); 211 212 213 /* 214 * Save important state. 215 * must be done before dmastop 216 */ 217 acb = dev->sc_nexus; 218 acb->sc_dmacmd = dev->sc_dmacmd; 219 220 /* 221 * Fetch the residual count 222 */ 223 SBIC_TC_GET(regs, count); 224 225 /* 226 * Shut down DMA 227 */ 228 dev->sc_dmastop(dev); 229 230 /* 231 * No longer in DMA 232 */ 233 dev->sc_flags &= ~SBICF_INDMA; 234 235 /* 236 * Ensure the WD chip is back in polled I/O mode, with nothing to 237 * transfer. 238 */ 239 SBIC_TC_PUT(regs, 0); 240 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 241 242 /* 243 * Update current count... 244 */ 245 acb->sc_tcnt = count; 246 247 /* 248 * Work out how many bytes were actually transferred 249 */ 250 count = dev->sc_tcnt - count; 251 dev->sc_tcnt = acb->sc_tcnt; 252 253 /* 254 * Fixup partial xfers 255 */ 256 acb->sc_kv.dc_addr += count; 257 acb->sc_kv.dc_count -= count; 258 acb->sc_pa.dc_addr += count; 259 acb->sc_pa.dc_count -= count >> 1; 260 261 #ifdef DEBUG 262 if ( data_pointer_debug ) 263 printf("save at (%x,%x):%x\n", 264 dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); 265 sbicdma_saves++; 266 #endif 267 268 splx(s); 269 } 270 271 272 /* 273 * DOES NOT RESTART DMA!!! 274 */ 275 void 276 sbic_load_ptrs(dev) 277 struct sbic_softc *dev; 278 { 279 struct sbic_acb *acb = dev->sc_nexus; 280 int s; 281 282 if ( acb->sc_kv.dc_count == 0 ) { 283 /* 284 * No data to xfer 285 */ 286 return; 287 } 288 289 s = splbio(); 290 291 /* 292 * Reset the Scatter-Gather chain 293 */ 294 dev->sc_last = dev->sc_cur = &acb->sc_pa; 295 296 /* 297 * Restore the Transfer Count and DMA specific data 298 */ 299 dev->sc_tcnt = acb->sc_tcnt; 300 dev->sc_dmacmd = acb->sc_dmacmd; 301 302 #ifdef DEBUG 303 sbicdma_ops++; 304 #endif 305 306 /* 307 * Need to fixup new segment? 308 */ 309 if ( dev->sc_tcnt == 0 ) { 310 /* 311 * sc_tcnt == 0 implies end of segment 312 */ 313 char *vaddr, *paddr; 314 int count; 315 316 /* 317 * do kvm to pa mappings 318 */ 319 vaddr = acb->sc_kv.dc_addr; 320 paddr = acb->sc_pa.dc_addr = (char *) kvtop(vaddr); 321 322 for (count = (NBPG - ((int)vaddr & PGOFSET)); 323 count < acb->sc_kv.dc_count && 324 (char*)kvtop(vaddr + count + 4) == paddr + count + 4; 325 count += NBPG) 326 ; /* Do nothing */ 327 328 /* 329 * If it's all contiguous... 330 */ 331 if ( count > acb->sc_kv.dc_count ) { 332 count = acb->sc_kv.dc_count; 333 #ifdef DEBUG 334 sbicdma_hits++; 335 #endif 336 } 337 #ifdef DEBUG 338 else 339 sbicdma_misses++; 340 #endif 341 342 acb->sc_tcnt = count; 343 acb->sc_pa.dc_count = count >> 1; 344 345 #ifdef DEBUG 346 if ( data_pointer_debug ) 347 printf("DMA recalc:kv(%x,%x)pa(%x,%x)\n", acb->sc_kv.dc_addr, 348 acb->sc_kv.dc_count, 349 acb->sc_pa.dc_addr, 350 acb->sc_tcnt); 351 #endif 352 353 } 354 355 splx(s); 356 } 357 358 /* 359 * used by specific sbic controller 360 * 361 * it appears that the higher level code does nothing with LUN's 362 * so I will too. I could plug it in, however so could they 363 * in scsi_scsipi_cmd(). 364 */ 365 int 366 sbic_scsicmd(xs) 367 struct scsipi_xfer *xs; 368 { 369 struct scsipi_link *slp = xs->sc_link; 370 struct sbic_softc *dev = slp->adapter_softc; 371 struct sbic_acb *acb; 372 int flags = xs->xs_control, 373 s; 374 375 if ( flags & XS_CTL_DATA_UIO ) 376 panic("sbic: scsi data uio requested"); 377 378 if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) 379 panic("sbic_scsicmd: busy"); 380 381 if ( slp->scsipi_scsi.target == slp->scsipi_scsi.adapter_target ) 382 return ESCAPE_NOT_SUPPORTED; 383 384 s = splbio(); 385 386 if ( (acb = dev->free_list.tqh_first) != NULL ) 387 TAILQ_REMOVE(&dev->free_list, acb, chain); 388 389 splx(s); 390 391 if ( acb == NULL ) { 392 #ifdef DEBUG 393 printf("sbic_scsicmd: unable to queue request for target %d\n", 394 slp->scsipi_scsi.target); 395 #ifdef DDB 396 Debugger(); 397 #endif 398 #endif 399 xs->error = XS_DRIVER_STUFFUP; 400 401 return(TRY_AGAIN_LATER); 402 } 403 404 if ( flags & XS_CTL_DATA_IN ) 405 acb->flags = ACB_ACTIVE | ACB_DATAIN; 406 else 407 acb->flags = ACB_ACTIVE; 408 409 acb->xs = xs; 410 acb->clen = xs->cmdlen; 411 acb->sc_kv.dc_addr = xs->data; 412 acb->sc_kv.dc_count = xs->datalen; 413 acb->pa_addr = xs->data ? (char *)kvtop(xs->data) : 0; 414 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 415 416 if ( flags & XS_CTL_POLL ) { 417 /* 418 * This has major side effects -- it locks up the machine 419 */ 420 int stat; 421 422 s = splbio(); 423 424 dev->sc_flags |= SBICF_ICMD; 425 426 do { 427 /* 428 * If we already had a nexus, while away the time until idle... 429 * This is likely only to happen if a reselection occurs between 430 * here and our earlier check for ICMD && sc_nexus (which would 431 * have resulted in a panic() had it been true). 432 */ 433 while ( dev->sc_nexus ) 434 sbicpoll(dev); 435 436 /* 437 * Fix up the new nexus 438 */ 439 dev->sc_nexus = acb; 440 dev->sc_xs = xs; 441 dev->target = slp->scsipi_scsi.target; 442 dev->lun = slp->scsipi_scsi.lun; 443 444 stat = sbicicmd(dev, &acb->cmd, acb->clen, 445 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 446 447 } while ( dev->sc_nexus != acb ); 448 449 sbic_scsidone(acb, stat); 450 451 splx(s); 452 453 return(COMPLETE); 454 } 455 456 s = splbio(); 457 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 458 459 /* 460 * If nothing is active, try to start it now. 461 */ 462 if ( dev->sc_nexus == NULL ) 463 sbic_sched(dev); 464 465 splx(s); 466 467 return(SUCCESSFULLY_QUEUED); 468 } 469 470 /* 471 * attempt to start the next available command 472 */ 473 void 474 sbic_sched(dev) 475 struct sbic_softc *dev; 476 { 477 struct scsipi_xfer *xs; 478 struct scsipi_link *slp = NULL; /* Gag the compiler */ 479 struct sbic_acb *acb; 480 int flags, 481 stat; 482 483 /* 484 * XXXSCW 485 * I'll keep this test here, even though I can't see any obvious way 486 * in which sbic_sched() could be called with sc_nexus non NULL 487 */ 488 if ( dev->sc_nexus ) 489 return; /* a command is current active */ 490 491 /* 492 * Loop through the ready list looking for work to do... 493 */ 494 for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { 495 int i, j; 496 497 slp = acb->xs->sc_link; 498 i = slp->scsipi_scsi.target; 499 j = 1 << slp->scsipi_scsi.lun; 500 501 /* 502 * We've found a potential command, but is the target/lun busy? 503 */ 504 if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { 505 /* 506 * Nope, it's not busy, so we can use it. 507 */ 508 dev->sc_tinfo[i].lubusy |= j; 509 TAILQ_REMOVE(&dev->ready_list, acb, chain); 510 dev->sc_nexus = acb; 511 acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ 512 break; 513 } 514 } 515 516 if ( acb == NULL ) { 517 QPRINTF(("sbicsched: no work\n")); 518 return; /* did not find an available command */ 519 } 520 521 #ifdef DEBUG 522 if ( data_pointer_debug > 1 ) 523 printf("sbic_sched(%d,%d)\n", slp->scsipi_scsi.target, 524 slp->scsipi_scsi.lun); 525 #endif 526 527 dev->sc_xs = xs = acb->xs; 528 flags = xs->xs_control; 529 530 if ( flags & XS_CTL_RESET ) 531 sbicreset(dev); 532 533 dev->sc_stat[0] = -1; 534 dev->target = slp->scsipi_scsi.target; 535 dev->lun = slp->scsipi_scsi.lun; 536 537 if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && 538 (sbicdmaok(dev, xs) == 0)) ) 539 stat = sbicicmd(dev, &acb->cmd, acb->clen, 540 acb->sc_kv.dc_addr, acb->sc_kv.dc_count); 541 else 542 if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) 543 return; 544 else 545 stat = dev->sc_stat[0]; 546 547 sbic_scsidone(acb, stat); 548 } 549 550 void 551 sbic_scsidone(acb, stat) 552 struct sbic_acb *acb; 553 int stat; 554 { 555 struct scsipi_xfer *xs = acb->xs; 556 struct scsipi_link *slp = xs->sc_link; 557 struct sbic_softc *dev = slp->adapter_softc; 558 int dosched = 0; 559 560 #ifdef DIAGNOSTIC 561 if ( acb == NULL || xs == NULL ) { 562 printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); 563 #ifdef DDB 564 Debugger(); 565 #endif 566 return; 567 } 568 #endif 569 570 /* 571 * is this right? 572 */ 573 xs->status = stat; 574 575 #ifdef DEBUG 576 if ( data_pointer_debug > 1 ) 577 printf("scsidone: (%d,%d)->(%d,%d)%02x\n", slp->scsipi_scsi.target, 578 slp->scsipi_scsi.lun, 579 dev->target, dev->lun, stat); 580 581 if ( xs->sc_link->scsipi_scsi.target == 582 dev->sc_link.scsipi_scsi.adapter_target ) 583 panic("target == hostid"); 584 #endif 585 586 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) == 0 ) { 587 588 if ( stat == SCSI_CHECK ) { 589 /* 590 * Schedule a REQUEST SENSE 591 */ 592 struct scsipi_sense *ss = (void *)&acb->cmd; 593 594 #ifdef DEBUG 595 if ( report_sense ) 596 printf("sbic_scsidone: autosense %02x targ %d lun %d", 597 acb->cmd.opcode, slp->scsipi_scsi.target, 598 slp->scsipi_scsi.lun); 599 #endif 600 601 bzero(ss, sizeof(*ss)); 602 603 ss->opcode = REQUEST_SENSE; 604 ss->byte2 = slp->scsipi_scsi.lun << 5; 605 ss->length = sizeof(struct scsipi_sense_data); 606 607 acb->clen = sizeof(*ss); 608 acb->sc_kv.dc_addr = (char *)&xs->sense.scsi_sense; 609 acb->sc_kv.dc_count = sizeof(struct scsipi_sense_data); 610 acb->pa_addr = (char *)kvtop(&xs->sense.scsi_sense); /* XXX check */ 611 acb->flags = ACB_ACTIVE | ACB_CHKSENSE | ACB_DATAIN; 612 613 TAILQ_INSERT_HEAD(&dev->ready_list, acb, chain); 614 615 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 616 ~(1 << slp->scsipi_scsi.lun); 617 dev->sc_tinfo[slp->scsipi_scsi.target].senses++; 618 619 if ( dev->sc_nexus == acb ) { 620 dev->sc_nexus = NULL; 621 dev->sc_xs = NULL; 622 sbic_sched(dev); 623 } 624 return; 625 } 626 } 627 628 if ( xs->error == XS_NOERROR && (acb->flags & ACB_CHKSENSE) != 0 ) { 629 630 xs->error = XS_SENSE; 631 632 #ifdef DEBUG 633 if (report_sense) 634 printf(" => %02x %02x\n", xs->sense.scsi_sense.flags, 635 xs->sense.scsi_sense.extra_bytes[3]); 636 #endif 637 638 } else { 639 xs->resid = 0; /* XXXX */ 640 } 641 642 xs->xs_status |= XS_STS_DONE; 643 644 /* 645 * Remove the ACB from whatever queue it's on. We have to do a bit of 646 * a hack to figure out which queue it's on. Note that it is *not* 647 * necessary to cdr down the ready queue, but we must cdr down the 648 * nexus queue and see if it's there, so we can mark the unit as no 649 * longer busy. This code is sickening, but it works. 650 */ 651 if ( acb == dev->sc_nexus ) { 652 653 dev->sc_nexus = NULL; 654 dev->sc_xs = NULL; 655 656 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 657 ~(1 << slp->scsipi_scsi.lun); 658 659 if ( dev->ready_list.tqh_first ) 660 dosched = 1; /* start next command */ 661 662 } else 663 if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { 664 665 TAILQ_REMOVE(&dev->ready_list, acb, chain); 666 667 } else { 668 669 struct sbic_acb *a; 670 671 for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { 672 if ( a == acb ) { 673 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 674 dev->sc_tinfo[slp->scsipi_scsi.target].lubusy &= 675 ~(1 << slp->scsipi_scsi.lun); 676 break; 677 } 678 } 679 680 if ( a ) 681 ; 682 else if ( acb->chain.tqe_next ) { 683 TAILQ_REMOVE(&dev->ready_list, acb, chain); 684 } else { 685 printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); 686 #ifdef DDB 687 Debugger(); 688 #endif 689 } 690 } 691 692 /* 693 * Put it on the free list. 694 */ 695 acb->flags = ACB_FREE; 696 TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); 697 698 dev->sc_tinfo[slp->scsipi_scsi.target].cmds++; 699 700 scsipi_done(xs); 701 702 if ( dosched ) 703 sbic_sched(dev); 704 } 705 706 int 707 sbicdmaok(dev, xs) 708 struct sbic_softc *dev; 709 struct scsipi_xfer *xs; 710 { 711 if ( sbic_no_dma || xs->datalen == 0 || 712 xs->datalen & 0x03 || (int)xs->data & 0x03) 713 return(0); 714 715 /* 716 * controller supports dma to any addresses? 717 */ 718 if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) 719 return(1); 720 721 /* 722 * this address is ok for dma? 723 */ 724 if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) 725 return(1); 726 727 return(0); 728 } 729 730 int 731 sbicwait(regs, until, timeo, line) 732 sbic_regmap_p regs; 733 u_char until; 734 int timeo; 735 int line; 736 { 737 u_char val; 738 739 if ( timeo == 0 ) 740 timeo = 1000000; /* some large value.. */ 741 742 GET_SBIC_asr(regs, val); 743 744 while ( (val & until) == 0 ) { 745 746 if ( timeo-- == 0 ) { 747 int csr; 748 GET_SBIC_csr(regs, csr); 749 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); 750 #if defined(DDB) && defined(DEBUG) 751 Debugger(); 752 #endif 753 return(val); /* Maybe I should abort */ 754 break; 755 } 756 757 DELAY(1); 758 GET_SBIC_asr(regs, val); 759 } 760 761 return(val); 762 } 763 764 int 765 sbicabort(dev, where) 766 struct sbic_softc *dev; 767 char *where; 768 { 769 sbic_regmap_p regs = dev->sc_sbicp; 770 u_char csr, 771 asr; 772 773 GET_SBIC_asr(regs, asr); 774 GET_SBIC_csr(regs, csr); 775 776 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", 777 dev->sc_dev.dv_xname, where, csr, asr); 778 779 /* 780 * Clean up chip itself 781 */ 782 if ( dev->sc_flags & SBICF_SELECTED ) { 783 784 while ( asr & SBIC_ASR_DBR ) { 785 /* 786 * sbic is jammed w/data. need to clear it 787 * But we don't know what direction it needs to go 788 */ 789 GET_SBIC_data(regs, asr); 790 printf("%s: abort %s: clearing data buffer 0x%02x\n", 791 dev->sc_dev.dv_xname, where, asr); 792 GET_SBIC_asr(regs, asr); 793 if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ 794 SET_SBIC_data(regs, asr); 795 GET_SBIC_asr(regs, asr); 796 } 797 798 WAIT_CIP(regs); 799 800 printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); 801 SET_SBIC_cmd(regs, SBIC_CMD_ABORT); 802 WAIT_CIP(regs); 803 804 GET_SBIC_asr(regs, asr); 805 806 if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { 807 /* 808 * ok, get more drastic.. 809 */ 810 printf("%s: sbicabort - asr %x, trying to reset\n", 811 dev->sc_dev.dv_xname, asr); 812 sbicreset(dev); 813 dev->sc_flags &= ~SBICF_SELECTED; 814 return SBIC_STATE_ERROR; 815 } 816 817 printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); 818 SET_SBIC_cmd(regs, SBIC_CMD_DISC); 819 820 do { 821 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 822 GET_SBIC_asr(regs, asr); 823 GET_SBIC_csr (regs, csr); 824 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); 825 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 826 (csr != SBIC_CSR_CMD_INVALID) ); 827 828 /* 829 * lets just hope it worked.. 830 */ 831 dev->sc_flags &= ~SBICF_SELECTED; 832 } 833 834 return SBIC_STATE_ERROR; 835 } 836 837 838 /* 839 * Initialize driver-private structures 840 */ 841 void 842 sbicinit(dev) 843 struct sbic_softc *dev; 844 { 845 u_int i; 846 847 if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { 848 849 struct sbic_acb *acb; 850 851 TAILQ_INIT(&dev->ready_list); 852 TAILQ_INIT(&dev->nexus_list); 853 TAILQ_INIT(&dev->free_list); 854 855 dev->sc_nexus = NULL; 856 dev->sc_xs = NULL; 857 858 acb = dev->sc_acb; 859 bzero(acb, sizeof(dev->sc_acb)); 860 861 for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { 862 TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); 863 acb++; 864 } 865 866 bzero(dev->sc_tinfo, sizeof(dev->sc_tinfo)); 867 868 #ifdef DEBUG 869 /* 870 * make sure timeout is really not needed 871 */ 872 timeout((void *)sbictimeout, dev, 30 * hz); 873 #endif 874 875 } else 876 panic("sbic: reinitializing driver!"); 877 878 dev->sc_flags |= SBICF_ALIVE; 879 dev->sc_flags &= ~SBICF_SELECTED; 880 881 /* 882 * initialize inhibit array 883 * Never enable Sync, since it just doesn't work on mvme147 :( 884 */ 885 for (i = 0; i < 8; ++i) 886 sbic_inhibit_sync[i] = 1; 887 888 sbicreset(dev); 889 } 890 891 void 892 sbicreset(dev) 893 struct sbic_softc *dev; 894 { 895 sbic_regmap_p regs = dev->sc_sbicp; 896 u_int my_id, 897 s; 898 u_char csr; 899 900 s = splbio(); 901 902 my_id = dev->sc_link.scsipi_scsi.adapter_target & SBIC_ID_MASK; 903 904 if (dev->sc_clkfreq < 110) 905 my_id |= SBIC_ID_FS_8_10; 906 else if (dev->sc_clkfreq < 160) 907 my_id |= SBIC_ID_FS_12_15; 908 else if (dev->sc_clkfreq < 210) 909 my_id |= SBIC_ID_FS_16_20; 910 911 SET_SBIC_myid(regs, my_id); 912 913 /* 914 * Reset the chip 915 */ 916 SET_SBIC_cmd(regs, SBIC_CMD_RESET); 917 DELAY(25); 918 919 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 920 GET_SBIC_csr(regs, csr); /* clears interrupt also */ 921 922 /* 923 * Set up various chip parameters 924 */ 925 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 926 927 /* 928 * don't allow Selection (SBIC_RID_ES) 929 * until we can handle target mode!! 930 */ 931 SET_SBIC_rselid(regs, SBIC_RID_ER); 932 933 /* 934 * Asynchronous for now 935 */ 936 SET_SBIC_syn(regs, 0); 937 938 /* 939 * Anything else was zeroed by reset 940 */ 941 splx(s); 942 943 dev->sc_flags &= ~SBICF_SELECTED; 944 } 945 946 void 947 sbicerror(dev, csr) 948 struct sbic_softc *dev; 949 u_char csr; 950 { 951 struct scsipi_xfer *xs = dev->sc_xs; 952 953 #ifdef DIAGNOSTIC 954 if ( xs == NULL ) 955 panic("sbicerror: dev->sc_xs == NULL"); 956 #endif 957 958 if ( xs->xs_control & XS_CTL_SILENT ) 959 return; 960 961 printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); 962 } 963 964 /* 965 * select the bus, return when selected or error. 966 * 967 * Returns the current CSR following selection and optionally MSG out phase. 968 * i.e. the returned CSR *should* indicate CMD phase... 969 * If the return value is 0, some error happened. 970 */ 971 u_char 972 sbicselectbus(dev) 973 struct sbic_softc *dev; 974 { 975 sbic_regmap_p regs = dev->sc_sbicp; 976 u_char target = dev->target, 977 lun = dev->lun, 978 asr, 979 csr, 980 id; 981 982 /* 983 * if we're already selected, return (XXXX panic maybe?) 984 */ 985 if ( dev->sc_flags & SBICF_SELECTED ) 986 return(0); 987 988 QPRINTF(("sbicselectbus %d: ", target)); 989 990 /* 991 * issue select 992 */ 993 SET_SBIC_selid(regs, target); 994 SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 995 996 GET_SBIC_asr(regs, asr); 997 998 if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { 999 /* 1000 * This means we got ourselves reselected upon 1001 */ 1002 QPRINTF(("WD busy (reselect?)\n")); 1003 return 0; 1004 } 1005 1006 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); 1007 1008 /* 1009 * wait for select (merged from seperate function may need 1010 * cleanup) 1011 */ 1012 WAIT_CIP(regs); 1013 1014 do { 1015 1016 asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 1017 1018 if ( asr & SBIC_ASR_LCI ) { 1019 QPRINTF(("late LCI: asr %02x\n", asr)); 1020 return 0; 1021 } 1022 1023 /* 1024 * Clear interrupt 1025 */ 1026 GET_SBIC_csr (regs, csr); 1027 1028 QPRINTF(("%02x ", csr)); 1029 1030 /* 1031 * Reselected from under our feet? 1032 */ 1033 if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { 1034 QPRINTF(("got reselected, asr %02x\n", asr)); 1035 /* 1036 * We need to handle this now so we don't lock up later 1037 */ 1038 sbicnextstate(dev, csr, asr); 1039 1040 return 0; 1041 } 1042 1043 /* 1044 * Whoops! 1045 */ 1046 if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { 1047 panic("sbicselectbus: target issued select!"); 1048 return 0; 1049 } 1050 1051 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 1052 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 1053 csr != SBIC_CSR_SEL_TIMEO); 1054 1055 /* 1056 * Anyone at home? 1057 */ 1058 if ( csr == SBIC_CSR_SEL_TIMEO ) { 1059 dev->sc_xs->error = XS_SELTIMEOUT; 1060 QPRINTF(("Selection Timeout\n")); 1061 return 0; 1062 } 1063 1064 QPRINTF(("Selection Complete\n")); 1065 1066 /* 1067 * Assume we're now selected 1068 */ 1069 GET_SBIC_selid(regs, id); 1070 dev->target = id; 1071 dev->lun = lun; 1072 dev->sc_flags |= SBICF_SELECTED; 1073 1074 /* 1075 * Enable (or not) reselection 1076 * XXXSCW This is probably not necessary since we don't use use the 1077 * Select-and-Xfer-with-ATN command to initiate a selection... 1078 */ 1079 if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) 1080 SET_SBIC_rselid (regs, 0); 1081 else 1082 SET_SBIC_rselid (regs, SBIC_RID_ER); 1083 1084 /* 1085 * We only really need to do anything when the target goes to MSG out 1086 * If the device ignored ATN, it's probably old and brain-dead, 1087 * but we'll try to support it anyhow. 1088 * If it doesn't support message out, it definately doesn't 1089 * support synchronous transfers, so no point in even asking... 1090 */ 1091 if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { 1092 /* 1093 * Send identify message (SCSI-2 requires an identify msg) 1094 */ 1095 if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { 1096 /* 1097 * Handle drives that don't want to be asked 1098 * whether to go sync at all. 1099 */ 1100 dev->sc_sync[id].offset = 0; 1101 dev->sc_sync[id].period = sbic_min_period; 1102 dev->sc_sync[id].state = SYNC_DONE; 1103 } 1104 1105 /* 1106 * Do we need to negotiate Synchronous Xfers for this target? 1107 */ 1108 if ( dev->sc_sync[id].state != SYNC_START ) { 1109 /* 1110 * Nope, we've already negotiated. 1111 * Now see if we should allow the target to disconnect/reselect... 1112 */ 1113 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 1114 !sbic_enable_reselect ) 1115 SEND_BYTE (regs, MSG_IDENTIFY | lun); 1116 else 1117 SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); 1118 1119 } else { 1120 /* 1121 * try to initiate a sync transfer. 1122 * So compose the sync message we're going 1123 * to send to the target 1124 */ 1125 #ifdef DEBUG 1126 if ( sync_debug ) 1127 printf("\nSending sync request to target %d ... ", id); 1128 #endif 1129 /* 1130 * setup scsi message sync message request 1131 */ 1132 dev->sc_msg[0] = MSG_IDENTIFY | lun; 1133 dev->sc_msg[1] = MSG_EXT_MESSAGE; 1134 dev->sc_msg[2] = 3; 1135 dev->sc_msg[3] = MSG_SYNC_REQ; 1136 dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); 1137 dev->sc_msg[5] = sbic_max_offset; 1138 1139 sbicxfout(regs, 6, dev->sc_msg); 1140 1141 dev->sc_sync[id].state = SYNC_SENT; 1142 #ifdef DEBUG 1143 if ( sync_debug ) 1144 printf ("sent\n"); 1145 #endif 1146 } 1147 1148 /* 1149 * There's one interrupt still to come: the change to CMD phase... 1150 */ 1151 SBIC_WAIT(regs, SBIC_ASR_INT , 0); 1152 GET_SBIC_csr(regs, csr); 1153 } 1154 1155 /* 1156 * set sync or async 1157 */ 1158 if ( dev->sc_sync[target].state == SYNC_DONE ) { 1159 #ifdef DEBUG 1160 if ( sync_debug ) 1161 printf("select(%d): sync reg = 0x%02x\n", target, 1162 SBIC_SYN(dev->sc_sync[target].offset, 1163 dev->sc_sync[target].period)); 1164 #endif 1165 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, 1166 dev->sc_sync[target].period)); 1167 } else { 1168 #ifdef DEBUG 1169 if ( sync_debug ) 1170 printf("select(%d): sync reg = 0x%02x\n", target, 1171 SBIC_SYN(0,sbic_min_period)); 1172 #endif 1173 SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); 1174 } 1175 1176 return csr; 1177 } 1178 1179 /* 1180 * Information Transfer *to* a Scsi Target. 1181 * 1182 * Note: Don't expect there to be an interrupt immediately after all 1183 * the data is transferred out. The WD spec sheet says that the Transfer- 1184 * Info command for non-MSG_IN phases only completes when the target 1185 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1186 * 1187 * This can have a nasty effect on commands which take a relatively long 1188 * time to complete, for example a START/STOP unit command may remain in 1189 * CMD phase until the disk has spun up. Only then will the target change 1190 * to STATUS phase. This is really only a problem for immediate commands 1191 * since we don't allow disconnection for them (yet). 1192 */ 1193 int 1194 sbicxfout(regs, len, bp) 1195 sbic_regmap_p regs; 1196 int len; 1197 void *bp; 1198 { 1199 int wait = sbic_data_wait; 1200 u_char asr, 1201 *buf = bp; 1202 1203 QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " 1204 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1205 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1206 1207 /* 1208 * sigh.. WD-PROTO strikes again.. sending the command in one go 1209 * causes the chip to lock up if talking to certain (misbehaving?) 1210 * targets. Anyway, this procedure should work for all targets, but 1211 * it's slightly slower due to the overhead 1212 */ 1213 WAIT_CIP (regs); 1214 1215 SBIC_TC_PUT (regs, 0); 1216 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1217 SBIC_TC_PUT (regs, (unsigned)len); 1218 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1219 1220 /* 1221 * Loop for each byte transferred 1222 */ 1223 do { 1224 1225 GET_SBIC_asr (regs, asr); 1226 1227 if ( asr & SBIC_ASR_DBR ) { 1228 if ( len ) { 1229 SET_SBIC_data (regs, *buf); 1230 buf++; 1231 len--; 1232 } else { 1233 SET_SBIC_data (regs, 0); 1234 } 1235 wait = sbic_data_wait; 1236 } 1237 1238 } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1239 1240 #ifdef DEBUG 1241 QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1242 #endif 1243 1244 /* 1245 * Normally, an interrupt will be pending when this routing returns. 1246 */ 1247 return(len); 1248 } 1249 1250 /* 1251 * Information Transfer *from* a Scsi Target 1252 * returns # bytes left to read 1253 */ 1254 int 1255 sbicxfin(regs, len, bp) 1256 sbic_regmap_p regs; 1257 int len; 1258 void *bp; 1259 { 1260 int wait = sbic_data_wait; 1261 u_char *buf = bp; 1262 u_char asr; 1263 #ifdef DEBUG 1264 u_char *obp = bp; 1265 #endif 1266 1267 WAIT_CIP (regs); 1268 1269 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1270 SBIC_TC_PUT (regs, (unsigned)len); 1271 SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); 1272 1273 /* 1274 * Loop for each byte transferred 1275 */ 1276 do { 1277 1278 GET_SBIC_asr (regs, asr); 1279 1280 if ( asr & SBIC_ASR_DBR ) { 1281 if ( len ) { 1282 GET_SBIC_data (regs, *buf); 1283 buf++; 1284 len--; 1285 } else { 1286 u_char foo; 1287 GET_SBIC_data (regs, foo); 1288 } 1289 wait = sbic_data_wait; 1290 } 1291 1292 } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); 1293 1294 QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " 1295 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1296 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1297 1298 SBIC_TC_PUT (regs, 0); 1299 1300 /* 1301 * this leaves with one csr to be read 1302 */ 1303 return len; 1304 } 1305 1306 /* 1307 * SCSI 'immediate' command: issue a command to some SCSI device 1308 * and get back an 'immediate' response (i.e., do programmed xfer 1309 * to get the response data). 'cbuf' is a buffer containing a scsi 1310 * command of length clen bytes. 'buf' is a buffer of length 'len' 1311 * bytes for data. The transfer direction is determined by the device 1312 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 1313 * command must supply no data. 1314 * 1315 * Note that although this routine looks like it can handle disconnect/ 1316 * reselect, the fact is that it can't. There is still some work to be 1317 * done to clean this lot up. 1318 */ 1319 int 1320 sbicicmd(dev, cbuf, clen, buf, len) 1321 struct sbic_softc *dev; 1322 void *cbuf, 1323 *buf; 1324 int clen, 1325 len; 1326 { 1327 sbic_regmap_p regs = dev->sc_sbicp; 1328 struct sbic_acb *acb = dev->sc_nexus; 1329 u_char csr, 1330 asr; 1331 int still_busy = SBIC_STATE_RUNNING; 1332 #ifdef DEBUG 1333 int counter = 0; 1334 #endif 1335 1336 /* 1337 * Make sure pointers are OK 1338 */ 1339 dev->sc_last = dev->sc_cur = &acb->sc_pa; 1340 dev->sc_tcnt = acb->sc_tcnt = 0; 1341 1342 acb->sc_dmacmd = 0; 1343 acb->sc_pa.dc_count = 0; /* No DMA */ 1344 acb->sc_kv.dc_addr = buf; 1345 acb->sc_kv.dc_count = len; 1346 1347 #ifdef DEBUG 1348 if ( data_pointer_debug > 1 ) 1349 printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); 1350 #endif 1351 1352 /* 1353 * set the sbic into non-DMA mode 1354 */ 1355 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1356 1357 dev->sc_stat[0] = 0xff; 1358 dev->sc_msg[0] = 0xff; 1359 1360 /* 1361 * We're stealing the SCSI bus 1362 */ 1363 dev->sc_flags |= SBICF_ICMD; 1364 1365 do { 1366 GET_SBIC_asr (regs, asr); 1367 1368 /* 1369 * select the SCSI bus (it's an error if bus isn't free) 1370 */ 1371 if ( (dev->sc_flags & SBICF_SELECTED) == 0 && 1372 still_busy != SBIC_STATE_DISCONNECT ) { 1373 if ( (csr = sbicselectbus(dev)) == 0 ) { 1374 dev->sc_flags &= ~SBICF_ICMD; 1375 return(-1); 1376 } 1377 } else 1378 if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) 1379 GET_SBIC_csr(regs, csr); 1380 else 1381 csr = 0; 1382 1383 if ( csr ) { 1384 1385 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); 1386 1387 switch ( csr ) { 1388 1389 case SBIC_CSR_S_XFERRED: 1390 case SBIC_CSR_DISC: 1391 case SBIC_CSR_DISC_1: 1392 { 1393 u_char phase; 1394 1395 dev->sc_flags &= ~SBICF_SELECTED; 1396 GET_SBIC_cmd_phase (regs, phase); 1397 1398 if ( phase == 0x60 ) { 1399 GET_SBIC_tlun (regs, dev->sc_stat[0]); 1400 still_busy = SBIC_STATE_DONE; /* done */ 1401 } else { 1402 #ifdef DEBUG 1403 if ( reselect_debug > 1 ) 1404 printf("sbicicmd: handling disconnect\n"); 1405 #endif 1406 still_busy = SBIC_STATE_DISCONNECT; 1407 } 1408 } 1409 break; 1410 1411 case SBIC_CSR_XFERRED | CMD_PHASE: 1412 case SBIC_CSR_MIS | CMD_PHASE: 1413 case SBIC_CSR_MIS_1 | CMD_PHASE: 1414 case SBIC_CSR_MIS_2 | CMD_PHASE: 1415 { 1416 if ( sbicxfout(regs, clen, cbuf) ) 1417 still_busy = sbicabort(dev, "icmd sending cmd"); 1418 } 1419 break; 1420 1421 case SBIC_CSR_XFERRED | STATUS_PHASE: 1422 case SBIC_CSR_MIS | STATUS_PHASE: 1423 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1424 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1425 { 1426 /* 1427 * The sbic does the status/cmd-complete reading ok, 1428 * so do this with its hi-level commands. 1429 */ 1430 #ifdef DEBUG 1431 if ( sbic_debug ) 1432 printf("SBICICMD status phase (bsy=%d)\n", still_busy); 1433 #endif 1434 SET_SBIC_cmd_phase(regs, 0x46); 1435 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1436 } 1437 break; 1438 1439 default: 1440 { 1441 still_busy = sbicnextstate(dev, csr, asr); 1442 } 1443 break; 1444 } 1445 1446 /* 1447 * make sure the last command was taken, 1448 * ie. we're not hunting after an ignored command.. 1449 */ 1450 GET_SBIC_asr(regs, asr); 1451 1452 /* 1453 * tapes may take a loooong time.. 1454 */ 1455 while (asr & SBIC_ASR_BSY ) { 1456 1457 if ( asr & SBIC_ASR_DBR ) { 1458 int i; 1459 1460 printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1461 #ifdef DDB 1462 Debugger(); 1463 #endif 1464 /* 1465 * SBIC is jammed 1466 * DUNNO which direction 1467 * Try old direction 1468 */ 1469 GET_SBIC_data(regs, i); 1470 GET_SBIC_asr(regs, asr); 1471 1472 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1473 SET_SBIC_data(regs, i); 1474 } 1475 1476 GET_SBIC_asr(regs, asr); 1477 } 1478 } 1479 1480 /* 1481 * wait for last command to complete 1482 */ 1483 if ( asr & SBIC_ASR_LCI ) { 1484 printf("sbicicmd: last command ignored\n"); 1485 } 1486 else 1487 if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ 1488 SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); 1489 1490 /* 1491 * do it again 1492 */ 1493 } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); 1494 1495 /* 1496 * Sometimes we need to do an extra read of the CSR 1497 */ 1498 GET_SBIC_csr(regs, csr); 1499 1500 #ifdef DEBUG 1501 if ( data_pointer_debug > 1 ) 1502 printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, 1503 acb->sc_kv.dc_count, 1504 dev->sc_stat[0]); 1505 #endif 1506 1507 dev->sc_flags &= ~SBICF_ICMD; 1508 1509 return(dev->sc_stat[0]); 1510 } 1511 1512 /* 1513 * Finish SCSI xfer command: After the completion interrupt from 1514 * a read/write operation, sequence through the final phases in 1515 * programmed i/o. This routine is a lot like sbicicmd except we 1516 * skip (and don't allow) the select, cmd out and data in/out phases. 1517 */ 1518 void 1519 sbicxfdone(dev) 1520 struct sbic_softc *dev; 1521 { 1522 sbic_regmap_p regs = dev->sc_sbicp; 1523 u_char phase, 1524 csr; 1525 int s; 1526 1527 QPRINTF(("{")); 1528 s = splbio(); 1529 1530 /* 1531 * have the sbic complete on its own 1532 */ 1533 SBIC_TC_PUT(regs, 0); 1534 SET_SBIC_cmd_phase(regs, 0x46); 1535 SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); 1536 1537 do { 1538 1539 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 1540 GET_SBIC_csr (regs, csr); 1541 QPRINTF(("%02x:", csr)); 1542 1543 } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && 1544 (csr != SBIC_CSR_S_XFERRED)); 1545 1546 dev->sc_flags &= ~SBICF_SELECTED; 1547 1548 GET_SBIC_cmd_phase (regs, phase); 1549 QPRINTF(("}%02x", phase)); 1550 1551 if ( phase == 0x60 ) 1552 GET_SBIC_tlun(regs, dev->sc_stat[0]); 1553 else 1554 sbicerror(dev, csr); 1555 1556 QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); 1557 1558 splx(s); 1559 } 1560 1561 /* 1562 * No DMA chains 1563 */ 1564 int 1565 sbicgo(dev, xs) 1566 struct sbic_softc *dev; 1567 struct scsipi_xfer *xs; 1568 { 1569 struct sbic_acb *acb = dev->sc_nexus; 1570 sbic_regmap_p regs = dev->sc_sbicp; 1571 int i, 1572 dmaflags, 1573 count, 1574 usedma; 1575 u_char csr, 1576 asr, 1577 *addr; 1578 1579 dev->target = xs->sc_link->scsipi_scsi.target; 1580 dev->lun = xs->sc_link->scsipi_scsi.lun; 1581 1582 usedma = sbicdmaok(dev, xs); 1583 1584 #ifdef DEBUG 1585 if ( data_pointer_debug > 1 ) 1586 printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); 1587 #endif 1588 1589 /* 1590 * select the SCSI bus (it's an error if bus isn't free) 1591 */ 1592 if ( (csr = sbicselectbus(dev)) == 0 ) 1593 return(0); /* Not done: needs to be rescheduled */ 1594 1595 dev->sc_stat[0] = 0xff; 1596 1597 /* 1598 * Calculate DMA chains now 1599 */ 1600 if ( acb->flags & ACB_DATAIN ) 1601 dmaflags = DMAGO_READ; 1602 else 1603 dmaflags = 0; 1604 1605 addr = acb->sc_kv.dc_addr; 1606 count = acb->sc_kv.dc_count; 1607 1608 if ( count && ((char *)kvtop(addr) != acb->sc_pa.dc_addr) ) { 1609 printf("sbic: DMA buffer mapping changed %x->%x\n", 1610 acb->sc_pa.dc_addr, kvtop(addr)); 1611 #ifdef DDB 1612 Debugger(); 1613 #endif 1614 } 1615 1616 #ifdef DEBUG 1617 ++sbicdma_ops; /* count total DMA operations */ 1618 #endif 1619 1620 /* 1621 * Allocate the DMA chain 1622 * Mark end of segment... 1623 */ 1624 acb->sc_tcnt = dev->sc_tcnt = 0; 1625 acb->sc_pa.dc_count = 0; 1626 1627 sbic_load_ptrs(dev); 1628 1629 /* 1630 * Enable interrupts but don't do any DMA 1631 * enintr() also enables interrupts for the sbic 1632 */ 1633 dev->sc_enintr(dev); 1634 1635 if ( usedma ) { 1636 dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, 1637 acb->sc_pa.dc_count, dmaflags); 1638 #ifdef DEBUG 1639 dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; 1640 #endif 1641 } else 1642 dev->sc_dmacmd = 0; /* Don't use DMA */ 1643 1644 acb->sc_dmacmd = dev->sc_dmacmd; 1645 1646 #ifdef DEBUG 1647 if ( data_pointer_debug > 1 ) { 1648 printf("sbicgo dmago:%d(%x:%x) dmacmd=0x%02x\n", dev->target, 1649 dev->sc_cur->dc_addr, 1650 dev->sc_tcnt, 1651 dev->sc_dmacmd); 1652 } 1653 #endif 1654 1655 /* 1656 * Lets cycle a while then let the interrupt handler take over. 1657 */ 1658 GET_SBIC_asr(regs, asr); 1659 1660 do { 1661 1662 QPRINTF(("go ")); 1663 1664 /* 1665 * Handle the new phase 1666 */ 1667 i = sbicnextstate(dev, csr, asr); 1668 #if 0 1669 WAIT_CIP(regs); 1670 #endif 1671 if ( i == SBIC_STATE_RUNNING ) { 1672 GET_SBIC_asr(regs, asr); 1673 1674 if ( asr & SBIC_ASR_LCI ) 1675 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1676 1677 if ( asr & SBIC_ASR_INT ) 1678 GET_SBIC_csr(regs, csr); 1679 } 1680 1681 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1682 1683 if ( i == SBIC_STATE_DONE ) { 1684 if ( dev->sc_stat[0] == 0xff ) 1685 #if 0 1686 printf("sbicgo: done & stat = 0xff\n"); 1687 #else 1688 ; 1689 #endif 1690 else 1691 return 1; /* Did we really finish that fast? */ 1692 } 1693 1694 return 0; 1695 } 1696 1697 1698 int 1699 sbicintr(dev) 1700 struct sbic_softc *dev; 1701 { 1702 sbic_regmap_p regs = dev->sc_sbicp; 1703 u_char asr, 1704 csr; 1705 int i; 1706 1707 /* 1708 * pending interrupt? 1709 */ 1710 GET_SBIC_asr (regs, asr); 1711 if ( (asr & SBIC_ASR_INT) == 0 ) 1712 return(0); 1713 1714 GET_SBIC_csr(regs, csr); 1715 1716 do { 1717 1718 QPRINTF(("intr[0x%x]", csr)); 1719 1720 i = sbicnextstate(dev, csr, asr); 1721 #if 0 1722 WAIT_CIP(regs); 1723 #endif 1724 if ( i == SBIC_STATE_RUNNING ) { 1725 GET_SBIC_asr(regs, asr); 1726 1727 if ( asr & SBIC_ASR_LCI ) 1728 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); 1729 1730 if ( asr & SBIC_ASR_INT ) 1731 GET_SBIC_csr(regs, csr); 1732 } 1733 1734 } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); 1735 1736 QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); 1737 1738 return(1); 1739 } 1740 1741 /* 1742 * Run commands and wait for disconnect. 1743 * This is only ever called when a command is in progress, when we 1744 * want to busy wait for it to finish. 1745 */ 1746 int 1747 sbicpoll(dev) 1748 struct sbic_softc *dev; 1749 { 1750 sbic_regmap_p regs = dev->sc_sbicp; 1751 u_char asr, 1752 csr; 1753 int i; 1754 1755 /* 1756 * Wait for the next interrupt 1757 */ 1758 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1759 1760 do { 1761 GET_SBIC_asr (regs, asr); 1762 1763 if ( asr & SBIC_ASR_INT ) 1764 GET_SBIC_csr(regs, csr); 1765 1766 QPRINTF(("poll[0x%x]", csr)); 1767 1768 /* 1769 * Handle it 1770 */ 1771 i = sbicnextstate(dev, csr, asr); 1772 1773 WAIT_CIP(regs); 1774 GET_SBIC_asr(regs, asr); 1775 1776 /* 1777 * tapes may take a loooong time.. 1778 */ 1779 while ( asr & SBIC_ASR_BSY ) { 1780 u_char z = 0; 1781 1782 if ( asr & SBIC_ASR_DBR ) { 1783 printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); 1784 #ifdef DDB 1785 Debugger(); 1786 #endif 1787 /* 1788 * SBIC is jammed 1789 * DUNNO which direction 1790 * Try old direction 1791 */ 1792 GET_SBIC_data(regs, z); 1793 GET_SBIC_asr(regs, asr); 1794 1795 if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ 1796 SET_SBIC_data(regs, z); 1797 } 1798 1799 GET_SBIC_asr(regs, asr); 1800 } 1801 1802 if ( asr & SBIC_ASR_LCI ) 1803 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); 1804 else 1805 if ( i == SBIC_STATE_RUNNING ) /* BSY */ 1806 SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); 1807 1808 } while ( i == SBIC_STATE_RUNNING ); 1809 1810 return(1); 1811 } 1812 1813 /* 1814 * Handle a single msgin 1815 */ 1816 int 1817 sbicmsgin(dev) 1818 struct sbic_softc *dev; 1819 { 1820 sbic_regmap_p regs = dev->sc_sbicp; 1821 int recvlen = 1; 1822 u_char asr, 1823 csr, 1824 *tmpaddr, 1825 *msgaddr; 1826 1827 tmpaddr = msgaddr = dev->sc_msg; 1828 1829 tmpaddr[0] = 0xff; 1830 tmpaddr[1] = 0xff; 1831 1832 GET_SBIC_asr(regs, asr); 1833 1834 #ifdef DEBUG 1835 if ( reselect_debug > 1 ) 1836 printf("sbicmsgin asr=%02x\n", asr); 1837 #endif 1838 1839 GET_SBIC_selid (regs, csr); 1840 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); 1841 1842 SBIC_TC_PUT(regs, 0); 1843 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 1844 1845 do { 1846 while( recvlen-- ) { 1847 1848 /* 1849 * Fetch the next byte of the message 1850 */ 1851 RECV_BYTE(regs, *tmpaddr); 1852 1853 /* 1854 * get the command completion interrupt, or we 1855 * can't send a new command (LCI) 1856 */ 1857 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1858 GET_SBIC_csr(regs, csr); 1859 1860 #ifdef DEBUG 1861 if ( reselect_debug > 1 ) 1862 printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); 1863 #endif 1864 1865 tmpaddr++; 1866 1867 if ( recvlen ) { 1868 /* 1869 * Clear ACK, and wait for the interrupt for the next byte 1870 */ 1871 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 1872 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 1873 GET_SBIC_csr(regs, csr); 1874 } 1875 } 1876 1877 if ( msgaddr[0] == 0xff ) { 1878 printf("sbicmsgin: sbic swallowed our message\n"); 1879 break; 1880 } 1881 1882 #ifdef DEBUG 1883 if ( sync_debug ) { 1884 GET_SBIC_asr(regs, asr); 1885 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); 1886 } 1887 #endif 1888 /* 1889 * test whether this is a reply to our sync 1890 * request 1891 */ 1892 if ( MSG_ISIDENTIFY(msgaddr[0]) ) { 1893 1894 /* 1895 * Got IFFY msg -- ack it 1896 */ 1897 QPRINTF(("IFFY")); 1898 1899 } else 1900 if ( msgaddr[0] == MSG_REJECT && 1901 dev->sc_sync[dev->target].state == SYNC_SENT) { 1902 1903 /* 1904 * Target probably rejected our Sync negotiation. 1905 */ 1906 QPRINTF(("REJECT of SYN")); 1907 1908 #ifdef DEBUG 1909 if ( sync_debug ) 1910 printf("target %d rejected sync, going async\n", dev->target); 1911 #endif 1912 1913 dev->sc_sync[dev->target].period = sbic_min_period; 1914 dev->sc_sync[dev->target].offset = 0; 1915 dev->sc_sync[dev->target].state = SYNC_DONE; 1916 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 1917 dev->sc_sync[dev->target].period)); 1918 1919 } else 1920 if ( msgaddr[0] == MSG_REJECT ) { 1921 1922 /* 1923 * we'll never REJECt a REJECT message.. 1924 */ 1925 QPRINTF(("REJECT")); 1926 1927 } else 1928 if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { 1929 1930 /* 1931 * don't reject this either. 1932 */ 1933 QPRINTF(("MSG_SAVE_DATA_PTR")); 1934 1935 } else 1936 if ( msgaddr[0] == MSG_RESTORE_PTR ) { 1937 1938 /* 1939 * don't reject this either. 1940 */ 1941 QPRINTF(("MSG_RESTORE_PTR")); 1942 1943 } else 1944 if ( msgaddr[0] == MSG_DISCONNECT ) { 1945 1946 /* 1947 * Target is disconnecting... 1948 */ 1949 QPRINTF(("DISCONNECT")); 1950 1951 #ifdef DEBUG 1952 if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) 1953 printf("sbicmsgin: got disconnect msg %s\n", 1954 (dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); 1955 #endif 1956 1957 if ( dev->sc_flags & SBICF_ICMD ) { 1958 /* 1959 * We're in immediate mode. Prevent disconnects. 1960 * prepare to reject the message, NACK 1961 */ 1962 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 1963 WAIT_CIP(regs); 1964 } 1965 1966 } else 1967 if ( msgaddr[0] == MSG_CMD_COMPLETE ) { 1968 1969 /* 1970 * !! KLUDGE ALERT !! quite a few drives don't seem to 1971 * really like the current way of sending the 1972 * sync-handshake together with the ident-message, and 1973 * they react by sending command-complete and 1974 * disconnecting right after returning the valid sync 1975 * handshake. So, all I can do is reselect the drive, 1976 * and hope it won't disconnect again. I don't think 1977 * this is valid behavior, but I can't help fixing a 1978 * problem that apparently exists. 1979 * 1980 * Note: we should not get here on `normal' command 1981 * completion, as that condition is handled by the 1982 * high-level sel&xfer resume command used to walk 1983 * thru status/cc-phase. 1984 */ 1985 QPRINTF(("CMD_COMPLETE")); 1986 1987 #ifdef DEBUG 1988 if ( sync_debug ) 1989 printf ("GOT MSG %d! target %d acting weird.." 1990 " waiting for disconnect...\n", msgaddr[0], dev->target); 1991 #endif 1992 1993 /* 1994 * Check to see if sbic is handling this 1995 */ 1996 GET_SBIC_asr(regs, asr); 1997 1998 /* 1999 * XXXSCW: I'm not convinced of this, we haven't negated ACK yet... 2000 */ 2001 if ( asr & SBIC_ASR_BSY ) 2002 return SBIC_STATE_RUNNING; 2003 2004 /* 2005 * Let's try this: Assume it works and set status to 00 2006 */ 2007 dev->sc_stat[0] = 0; 2008 2009 } else 2010 if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { 2011 2012 /* 2013 * Target is sending us an extended message. We'll assume it's 2014 * the response to our Sync. negotiation. 2015 */ 2016 QPRINTF(("ExtMSG\n")); 2017 2018 /* 2019 * Read in whole extended message. First, negate ACK to accept 2020 * the MSG_EXT_MESSAGE byte... 2021 */ 2022 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2023 2024 /* 2025 * Wait for the interrupt for the next byte (length) 2026 */ 2027 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2028 GET_SBIC_csr(regs, csr); 2029 2030 #ifdef DEBUG 2031 QPRINTF(("CLR ACK csr %02x\n", csr)); 2032 #endif 2033 2034 /* 2035 * Read the length byte 2036 */ 2037 RECV_BYTE(regs, *tmpaddr); 2038 2039 /* 2040 * Wait for command completion IRQ 2041 */ 2042 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2043 GET_SBIC_csr(regs, csr); 2044 2045 /* 2046 * Reload the loop counter 2047 */ 2048 recvlen = *tmpaddr++; 2049 2050 QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); 2051 2052 } else 2053 if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && 2054 msgaddr[2] == MSG_SYNC_REQ ) { 2055 2056 /* 2057 * We've received the complete Extended Message Sync. Request... 2058 */ 2059 QPRINTF(("SYN")); 2060 2061 /* 2062 * Compute the required Transfer Period for the WD chip... 2063 */ 2064 dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); 2065 dev->sc_sync[dev->target].offset = msgaddr[4]; 2066 dev->sc_sync[dev->target].state = SYNC_DONE; 2067 2068 /* 2069 * Put the WD chip in synchronous mode 2070 */ 2071 SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, 2072 dev->sc_sync[dev->target].period)); 2073 #ifdef DEBUG 2074 if ( sync_debug ) 2075 printf("msgin(%d): sync reg = 0x%02x\n", dev->target, 2076 SBIC_SYN(dev->sc_sync[dev->target].offset, 2077 dev->sc_sync[dev->target].period)); 2078 #endif 2079 2080 printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", 2081 dev->sc_dev.dv_xname, dev->target, 2082 msgaddr[3] * 4, msgaddr[4]); 2083 2084 } else { 2085 2086 /* 2087 * We don't support whatever this message is... 2088 */ 2089 #ifdef DEBUG 2090 if ( sbic_debug || sync_debug ) 2091 printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); 2092 #endif 2093 2094 /* 2095 * prepare to reject the message, NACK 2096 */ 2097 SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); 2098 WAIT_CIP(regs); 2099 } 2100 2101 /* 2102 * Negate ACK to complete the transfer 2103 */ 2104 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2105 2106 /* 2107 * Wait for the interrupt for the next byte, or phase change. 2108 * Only read the CSR if we have more data to transfer. 2109 * XXXSCW: We should really verify that we're still in MSG IN phase 2110 * before blindly going back around this loop, but that would mean 2111 * we read the CSR... <sigh> 2112 */ 2113 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 2114 if ( recvlen > 0 ) 2115 GET_SBIC_csr(regs, csr); 2116 2117 } while ( recvlen > 0 ); 2118 2119 /* 2120 * Should still have one CSR to read 2121 */ 2122 return SBIC_STATE_RUNNING; 2123 } 2124 2125 2126 /* 2127 * sbicnextstate() 2128 * return: 2129 * SBIC_STATE_DONE == done 2130 * SBIC_STATE_RUNNING == working 2131 * SBIC_STATE_DISCONNECT == disconnected 2132 * SBIC_STATE_ERROR == error 2133 */ 2134 int 2135 sbicnextstate(dev, csr, asr) 2136 struct sbic_softc *dev; 2137 u_char csr, 2138 asr; 2139 { 2140 sbic_regmap_p regs = dev->sc_sbicp; 2141 struct sbic_acb *acb = dev->sc_nexus; 2142 2143 QPRINTF(("next[%02x,%02x]: ",asr,csr)); 2144 2145 switch (csr) { 2146 2147 case SBIC_CSR_XFERRED | CMD_PHASE: 2148 case SBIC_CSR_MIS | CMD_PHASE: 2149 case SBIC_CSR_MIS_1 | CMD_PHASE: 2150 case SBIC_CSR_MIS_2 | CMD_PHASE: 2151 { 2152 if ( sbicxfout(regs, acb->clen, &acb->cmd) ) 2153 goto abort; 2154 } 2155 break; 2156 2157 case SBIC_CSR_XFERRED | STATUS_PHASE: 2158 case SBIC_CSR_MIS | STATUS_PHASE: 2159 case SBIC_CSR_MIS_1 | STATUS_PHASE: 2160 case SBIC_CSR_MIS_2 | STATUS_PHASE: 2161 { 2162 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2163 2164 /* 2165 * this should be the normal i/o completion case. 2166 * get the status & cmd complete msg then let the 2167 * device driver look at what happened. 2168 */ 2169 sbicxfdone(dev); 2170 2171 #ifdef DEBUG 2172 dev->sc_dmatimo = 0; 2173 if ( data_pointer_debug > 1 ) 2174 printf("next dmastop: %d(%x:%x)\n", dev->target, 2175 dev->sc_cur->dc_addr, 2176 dev->sc_tcnt); 2177 #endif 2178 /* 2179 * Stop the DMA chip 2180 */ 2181 dev->sc_dmastop(dev); 2182 2183 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2184 2185 /* 2186 * Indicate to the upper layers that the command is done 2187 */ 2188 sbic_scsidone(acb, dev->sc_stat[0]); 2189 2190 return SBIC_STATE_DONE; 2191 } 2192 2193 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 2194 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 2195 case SBIC_CSR_MIS | DATA_OUT_PHASE: 2196 case SBIC_CSR_MIS | DATA_IN_PHASE: 2197 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 2198 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 2199 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 2200 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 2201 { 2202 /* 2203 * Verify that we expected to transfer data... 2204 */ 2205 if ( acb->sc_kv.dc_count <= 0 ) { 2206 printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", 2207 acb->sc_kv.dc_count, asr, csr); 2208 goto abort; 2209 } 2210 2211 /* 2212 * Should we transfer using PIO or DMA ? 2213 */ 2214 if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2215 acb->sc_dmacmd == 0 ) { 2216 2217 /* 2218 * Do PIO transfer 2219 */ 2220 int i; 2221 2222 #ifdef DEBUG 2223 if ( data_pointer_debug > 1 ) 2224 printf("next PIO: %d(%x:%x)\n", dev->target, 2225 acb->sc_kv.dc_addr, 2226 acb->sc_kv.dc_count); 2227 #endif 2228 2229 if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) 2230 /* 2231 * data in 2232 */ 2233 i = sbicxfin(regs, acb->sc_kv.dc_count, 2234 acb->sc_kv.dc_addr); 2235 else 2236 /* 2237 * data out 2238 */ 2239 i = sbicxfout(regs, acb->sc_kv.dc_count, 2240 acb->sc_kv.dc_addr); 2241 2242 acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); 2243 acb->sc_kv.dc_count = i; 2244 2245 /* 2246 * Update current count... 2247 */ 2248 acb->sc_tcnt = dev->sc_tcnt = i; 2249 2250 dev->sc_flags &= ~SBICF_INDMA; 2251 2252 } else { 2253 2254 /* 2255 * Do DMA transfer 2256 * set next dma addr and dec count 2257 */ 2258 sbic_save_ptrs(dev); 2259 sbic_load_ptrs(dev); 2260 2261 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | 2262 SBIC_MACHINE_DMA_MODE); 2263 2264 #ifdef DEBUG 2265 dev->sc_dmatimo = 1; 2266 if ( data_pointer_debug > 1 ) 2267 printf("next DMA: %d(%x:%x)\n", dev->target, 2268 dev->sc_cur->dc_addr, 2269 dev->sc_tcnt); 2270 #endif 2271 /* 2272 * Start the DMA chip going 2273 */ 2274 dev->sc_tcnt = dev->sc_dmanext(dev); 2275 2276 /* 2277 * Tell the WD chip how much to transfer this time around 2278 */ 2279 SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); 2280 2281 /* 2282 * Start the transfer 2283 */ 2284 SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); 2285 2286 /* 2287 * Indicate that we're in DMA mode 2288 */ 2289 dev->sc_flags |= SBICF_INDMA; 2290 } 2291 } 2292 break; 2293 2294 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 2295 case SBIC_CSR_MIS | MESG_IN_PHASE: 2296 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 2297 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 2298 { 2299 sbic_save_ptrs(dev); 2300 2301 /* 2302 * Handle a single message in... 2303 */ 2304 return sbicmsgin(dev); 2305 } 2306 2307 case SBIC_CSR_MSGIN_W_ACK: 2308 { 2309 /* 2310 * We should never see this since it's handled in 'sbicmsgin()' 2311 * but just for the sake of paranoia... 2312 */ 2313 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ 2314 printf("Acking unknown msgin CSR:%02x",csr); 2315 } 2316 break; 2317 2318 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 2319 case SBIC_CSR_MIS | MESG_OUT_PHASE: 2320 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 2321 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 2322 { 2323 /* 2324 * We only ever handle a message out phase here for sending a 2325 * REJECT message. 2326 */ 2327 sbic_save_ptrs(dev); 2328 2329 #ifdef DEBUG 2330 if (sync_debug) 2331 printf ("sending REJECT msg to last msg.\n"); 2332 #endif 2333 2334 SEND_BYTE(regs, MSG_REJECT); 2335 WAIT_CIP(regs); 2336 } 2337 break; 2338 2339 case SBIC_CSR_DISC: 2340 case SBIC_CSR_DISC_1: 2341 { 2342 /* 2343 * Try to schedule another target 2344 */ 2345 sbic_save_ptrs(dev); 2346 2347 dev->sc_flags &= ~SBICF_SELECTED; 2348 2349 #ifdef DEBUG 2350 if ( reselect_debug > 1 ) 2351 printf("sbicnext target %d disconnected\n", dev->target); 2352 #endif 2353 2354 TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); 2355 2356 ++dev->sc_tinfo[dev->target].dconns; 2357 2358 dev->sc_nexus = NULL; 2359 dev->sc_xs = NULL; 2360 2361 if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || 2362 !sbic_parallel_operations ) 2363 return SBIC_STATE_DISCONNECT; 2364 2365 QPRINTF(("sbicnext: calling sbic_sched\n")); 2366 2367 sbic_sched(dev); 2368 2369 QPRINTF(("sbicnext: sbic_sched returned\n")); 2370 2371 return SBIC_STATE_DISCONNECT; 2372 } 2373 2374 case SBIC_CSR_RSLT_NI: 2375 case SBIC_CSR_RSLT_IFY: 2376 { 2377 /* 2378 * A reselection. 2379 * Note that since we don't enable Advanced Features (assuming 2380 * the WD chip is at least the 'A' revision), we're only ever 2381 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 2382 * hell of it, we'll handle it anyway, for all the extra code 2383 * it needs... 2384 */ 2385 u_char newtarget, 2386 newlun; 2387 2388 GET_SBIC_rselid(regs, newtarget); 2389 2390 /* 2391 * check SBIC_RID_SIV? 2392 */ 2393 newtarget &= SBIC_RID_MASK; 2394 2395 if ( csr == SBIC_CSR_RSLT_IFY ) { 2396 2397 /* 2398 * Read Identify msg to avoid lockup 2399 */ 2400 GET_SBIC_data(regs, newlun); 2401 WAIT_CIP(regs); 2402 newlun &= SBIC_TLUN_MASK; 2403 2404 } else { 2405 2406 /* 2407 * Need to read Identify message the hard way, assuming 2408 * the target even sends us one... 2409 */ 2410 for (newlun = 255; newlun; --newlun) { 2411 GET_SBIC_asr(regs, asr); 2412 if (asr & SBIC_ASR_INT) 2413 break; 2414 delay(10); 2415 } 2416 2417 /* 2418 * If we didn't get an interrupt, somethink's up 2419 */ 2420 if ( (asr & SBIC_ASR_INT) == 0 ) { 2421 printf("%s: Reselect without identify? asr %x\n", 2422 dev->sc_dev.dv_xname, asr); 2423 newlun = 0; /* XXXX */ 2424 } else { 2425 /* 2426 * We got an interrupt, verify that it's a change to 2427 * message in phase, and if so read the message. 2428 */ 2429 GET_SBIC_csr(regs,csr); 2430 2431 if ( csr == SBIC_CSR_MIS | MESG_IN_PHASE || 2432 csr == SBIC_CSR_MIS_1 | MESG_IN_PHASE || 2433 csr == SBIC_CSR_MIS_2 | MESG_IN_PHASE ) { 2434 /* 2435 * Yup, gone to message in. Fetch the target LUN 2436 */ 2437 sbicmsgin(dev); 2438 newlun = dev->sc_msg[0] & 0x07; 2439 2440 } else { 2441 /* 2442 * Whoops! Target didn't go to message in phase!! 2443 */ 2444 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2445 newlun = 0; /* XXXSCW */ 2446 } 2447 } 2448 } 2449 2450 /* 2451 * Ok, we have the identity of the reselecting target. 2452 */ 2453 #ifdef DEBUG 2454 if ( reselect_debug > 1 || 2455 (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { 2456 printf("sbicnext: reselect %s from targ %d lun %d\n", 2457 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); 2458 } 2459 #endif 2460 2461 if ( dev->sc_nexus ) { 2462 /* 2463 * Whoops! We've been reselected with an command in progress! 2464 * The best we can do is to put the current command back on the 2465 * ready list and hope for the best. 2466 */ 2467 #ifdef DEBUG 2468 if ( reselect_debug > 1 ) { 2469 printf("%s: reselect %s with active command\n", 2470 dev->sc_dev.dv_xname, 2471 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); 2472 } 2473 #endif 2474 2475 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2476 2477 dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); 2478 2479 dev->sc_nexus = NULL; 2480 dev->sc_xs = NULL; 2481 } 2482 2483 /* 2484 * Reload sync values for this target 2485 */ 2486 if ( dev->sc_sync[newtarget].state == SYNC_DONE ) 2487 SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, 2488 dev->sc_sync[newtarget].period)); 2489 else 2490 SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); 2491 2492 /* 2493 * Loop through the nexus list until we find the saved entry 2494 * for the reselecting target... 2495 */ 2496 for (acb = dev->nexus_list.tqh_first; acb; 2497 acb = acb->chain.tqe_next) { 2498 2499 if ( acb->xs->sc_link->scsipi_scsi.target == newtarget && 2500 acb->xs->sc_link->scsipi_scsi.lun == newlun) { 2501 /* 2502 * We've found the saved entry. Dequeue it, and 2503 * make it current again. 2504 */ 2505 TAILQ_REMOVE(&dev->nexus_list, acb, chain); 2506 2507 dev->sc_nexus = acb; 2508 dev->sc_xs = acb->xs; 2509 dev->sc_flags |= SBICF_SELECTED; 2510 dev->target = newtarget; 2511 dev->lun = newlun; 2512 break; 2513 } 2514 } 2515 2516 if ( acb == NULL ) { 2517 printf("%s: reselect %s targ %d not in nexus_list %x\n", 2518 dev->sc_dev.dv_xname, 2519 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, 2520 &dev->nexus_list.tqh_first); 2521 panic("bad reselect in sbic"); 2522 } 2523 2524 if ( csr == SBIC_CSR_RSLT_IFY ) 2525 SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); 2526 } 2527 break; 2528 2529 default: 2530 abort: 2531 { 2532 /* 2533 * Something unexpected happened -- deal with it. 2534 */ 2535 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2536 2537 #ifdef DDB 2538 Debugger(); 2539 #endif 2540 2541 #ifdef DEBUG 2542 dev->sc_dmatimo = 0; 2543 if ( data_pointer_debug > 1 ) 2544 printf("next dmastop: %d(%x:%x)\n", dev->target, 2545 dev->sc_cur->dc_addr, 2546 dev->sc_tcnt); 2547 #endif 2548 2549 dev->sc_dmastop(dev); 2550 SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); 2551 if ( dev->sc_xs ) sbicerror(dev, csr); 2552 sbicabort(dev, "next"); 2553 2554 if ( dev->sc_flags & SBICF_INDMA ) { 2555 dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); 2556 2557 #ifdef DEBUG 2558 dev->sc_dmatimo = 0; 2559 if ( data_pointer_debug > 1 ) 2560 printf("next dmastop: %d(%x:%x)\n", dev->target, 2561 dev->sc_cur->dc_addr, 2562 dev->sc_tcnt); 2563 #endif 2564 sbic_scsidone(acb, -1); 2565 } 2566 2567 return SBIC_STATE_ERROR; 2568 } 2569 } 2570 2571 return(SBIC_STATE_RUNNING); 2572 } 2573 2574 2575 /* 2576 * Check if DMA can not be used with specified buffer 2577 */ 2578 int 2579 sbiccheckdmap(bp, len, mask) 2580 void *bp; 2581 u_long len, 2582 mask; 2583 { 2584 u_char *buffer; 2585 u_long phy_buf; 2586 u_long phy_len; 2587 2588 buffer = bp; 2589 2590 if ( len == 0 ) 2591 return(1); 2592 2593 while ( len ) { 2594 2595 phy_buf = kvtop(buffer); 2596 phy_len = NBPG - ((int) buffer & PGOFSET); 2597 2598 if ( len < phy_len ) 2599 phy_len = len; 2600 2601 if ( phy_buf & mask ) 2602 return(1); 2603 2604 buffer += phy_len; 2605 len -= phy_len; 2606 } 2607 2608 return(0); 2609 } 2610 2611 int 2612 sbictoscsiperiod(dev, a) 2613 struct sbic_softc *dev; 2614 int a; 2615 { 2616 unsigned int fs; 2617 2618 /* 2619 * cycle = DIV / (2 * CLK) 2620 * DIV = FS + 2 2621 * best we can do is 200ns at 20Mhz, 2 cycles 2622 */ 2623 2624 GET_SBIC_myid(dev->sc_sbicp, fs); 2625 2626 fs = (fs >> 6) + 2; /* DIV */ 2627 2628 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2629 2630 if ( a < 2 ) 2631 a = 8; /* map to Cycles */ 2632 2633 return ( (fs * a) >> 2 ); /* in 4 ns units */ 2634 } 2635 2636 int 2637 sbicfromscsiperiod(dev, p) 2638 struct sbic_softc *dev; 2639 int p; 2640 { 2641 unsigned fs, 2642 ret; 2643 2644 /* 2645 * Just the inverse of the above 2646 */ 2647 GET_SBIC_myid(dev->sc_sbicp, fs); 2648 2649 fs = (fs >> 6) + 2; /* DIV */ 2650 2651 fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ 2652 2653 ret = p << 2; /* in ns units */ 2654 ret = ret / fs; /* in Cycles */ 2655 2656 if ( ret < sbic_min_period ) 2657 return(sbic_min_period); 2658 2659 /* 2660 * verify rounding 2661 */ 2662 if ( sbictoscsiperiod(dev, ret) < p ) 2663 ret++; 2664 2665 return( (ret >= 8) ? 0 : ret ); 2666 } 2667 2668 #ifdef DEBUG 2669 void 2670 sbictimeout(dev) 2671 struct sbic_softc *dev; 2672 { 2673 int s, 2674 asr; 2675 2676 s = splbio(); 2677 2678 if ( dev->sc_dmatimo ) { 2679 2680 if ( dev->sc_dmatimo > 1 ) { 2681 2682 printf("%s: dma timeout #%d\n", dev->sc_dev.dv_xname, 2683 dev->sc_dmatimo - 1); 2684 2685 GET_SBIC_asr(dev->sc_sbicp, asr); 2686 2687 if ( asr & SBIC_ASR_INT ) { 2688 /* 2689 * We need to service a missed IRQ 2690 */ 2691 sbicintr(dev); 2692 } else { 2693 (void) sbicabort(dev, "timeout"); 2694 splx(s); 2695 return; 2696 } 2697 } 2698 2699 dev->sc_dmatimo++; 2700 } 2701 2702 splx(s); 2703 2704 timeout((void *)sbictimeout, dev, 30 * hz); 2705 } 2706 #endif 2707
Indexes created Sat Sep 27 22:09:54 GMT 2025